MOS Digital Circuits Chapter 16

In the late 70s as the era of LSI and VLSI began, NMOS became the fabrication technology choice. Later the design flexibility and other advantages of the CMOS were realized, CMOS technology then replaced NMOS at all level of integration. The small transistor size and low power dissipation of CMOS circuits, demonstration principal advantages of CMOS over NMOS circuits.

NMOS Inverter
For any IC technology used in digital circuit design, the basic circuit element is the logic inverter. Once the operation and characterization of the inverter circuits are thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits.

NMOS Inverter
If VI <VNT, the transistor is in cutoff and iD =0, there is no voltage drop across RD, and the out put voltage is Vo=VDD=VDS If VI >VNT, the transistor is on and initially is biased in saturation region, since
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NMOS Inverter Transfer Characteristics with load resister (Saturation Region)

As the input is increased slightly above the VTN, the transistor turns on and is in the saturation region. The output voltage is then vo = VDD iDRD (16.6 ) where the drain current is given by =VDD=VDS iD = Kn(VGS - VTN)2 = Kn(Vi - VTN)2 ( 16.7) By substituting the value of ID from Eq. 16.7 we get , VO = VDD - KnRD(VI - VTN)2 (16.8)
+

RD =VDD=VDS

RD

VGS=V
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VDS >VGS-VTN. As the input voltage increasesVGS=V (VGS) , the drain to source + voltage (VDS) decreases and the transistor inter into the non saturation region.

which relates the output and input voltages as long as the transistor is biased in the saturation region.

NMOS Inverter Transfer Characteristics with load resister (transition Region)

As the input voltage is further increases and voltage drop across the RD become sufficient to reduce the drain to source voltage such that
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NMOS Inverter Transfer Characteristics with load resister (Nonsaturation Region)

As the input voltage becomes greater than VIt, the Q-point continues to move up the load line, and the transistor becomes biased in the nonsaturation region. The drain current is then iD = Kn[2(VGS - VTN)VDS VDS2] = Kn[2(vI - VTN)VO Vo2] (16.11) The output voltage is then determined by vo = VDD iDRD Substitute the value of ID from above equation we get the output voltage relation when the transistor is biased in nonsaturation region.

RD =VDD=VDS

VDSVGS-VTN.
the - p of the transistor moves up the Q oint load line. At the transition point, we have

VGS=V
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vot = VIt - VTN

16.9

where Vo, and VI, are the drain to s - - ource and gate to s - - ource voltages, respectively, at the transition point. By substituting Equation (16.9) into (16.8), the input voltage at the transition point can be determined as,

KnRD(VIt - VTN)2+ (VIt - VTN) - VDD = 0

VO = VDD KnRD [2(vl - VTN)vo - vo2]

RD =VDD=VDS

VGS=V
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Summary of NMOS inverter C-V relationship with the resister load

Saturation region
+

VO = VDD - KnRD(VI - VTN)2

iD = Kn(VGS - VTN)2 = Kn(Vi - VTN)2
VGS=V
+

RD =VDD=VDS

Transition region

Nonsaturation region
iD = Kn[2(vI - VTN)VO Vo2]

vot = VIt - VTN

KnRD(VIt - VTN
It should be be noted that the minimum output voltage, or the logic 0 level, for a high input decreases with increasing load resistance, and the sharpness of the transition region between a low input and a high input increases with increasing load resistance.

)2+

(VIt - VTN) - VDD

VO = VDD KnRD [2(vl - VTN)vo - vo2]

NMOS Inverter with Enhancement Load

This basic inverter consist of two enhancement-only NMOS transistors and is much more practical than the resister loaded inverter, which is thousand of times larger than a MOSFET.

n-Channel MOSFET connected as saturated load device

An n-channel enhancement-mode MOSFET with the gate connected to the drain can be used as load device in an NMOS inverter. Since the gate and drain of the transistor are connected, we have VGS=VDS When VGS=VDS>VTN, a non zero drain current is induced in the transistor and thus the transistor operates in saturation only. And following condition is satisfied. VDS>(VGS-VTN) VDS (sat)= (VDS-VTN) because VGS=VDS or VDS (sat)= (VGS-VTN) In the saturation region the drain current is iD=Kn(VGS-VTN)2 = Kn(VDS-VTN)2

The iD versus vDS characteristics are shown in Figure 16.7(b), which indicates that this device acts as a nonlinear resistor.

NMOS Inverter with Enhancement Load/Saturated

In the saturation region the load drain current is iDL=KL(VGSL-VTNL)2 = KL(VDSL-VTNL)2 For VGSD<VTN ( driver transistor ) transistor is in cutoff mode and does not conduct drain current 0= iDL=KL(VGSL-VTNL)2 = KL(VDSLVTNL)2 VGSL=VTNL or VDSL=VTNL As a result the output high voltage VO is degraded by the threshold voltage or VO,, max= VOH =VDD-VTNL

NMOS inverter with Enhancement Load/Saturated (Cont.)

As the VI=>VTND A non zero drain current is induced in the transistor and thus the drive transistor operates in saturation only. As shown in the figure the following condition is satisfied iDD=iDL or KD(VGSD-VTND)2 = KL(VGSL-VTNL)2 Substituting VGSD=VI and VGSL=VDD-VO yields KD(VI - VTND)2 = KL(VDD - VO - VTNL)2 Solving for VO gives VO= VDD-VTNL- KD/KL(VI-VTND)

NMOS inverter with Enhancement Load/Saturated (driver at the transition point)

As the input voltage (VGS) further increases, the drive Q-point moves up and switch into the transition region., we have VDSD(sat)= VGSD-VTND In terms of input/output transition voltages or VOt=VIt-VTND Substituting above Equation into following equation VO= VDD-VTNL- KD/KL(VI-VTND) we find the input voltage at the transition point, which is VIt= [VDDVTNL+VTND(1+ KD/KL)]/(1+ KD/KL)

NMOS Inverter with Enhancement Load/Saturated (driver at the non saturation region))
As the input voltage becomes greater than VIt the driver transistor Q- point continues to move up the load curve and the driver becomes biased in the nonsaturation region. Since the driver and load drain currents are still equal, or iDD = iDL, we now have KD[2(VGSD - VTND)VDSD - VDSD2] = KL(VDSL -VTNL)2 Substituting VGSD=VI and VDSD=VO and VDSL= VDD-VO we get KD[2(vl -VTND) Vo- VO2 ] = KL(VDD - VO - VTNL)2

The ratio KDIKL is the aspect ratio and is related to the width to- length parameters of the driver and load transistors.
The slope of the VTC curves in the saturation region is known as inverter gain and is given by dVo/dVI= - KD/KL If the inverter gain is greater then unity, the inverter logic gate is belonged to restoring logic family.