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Considering the high impact of gettering of silicon on fabrication of wafer designing and optimize the designing with new innovative solutions
Pouria Ilka1, Mehdi Darbandi2*, Mohammad Golmakani3 1 NIGC (National Iranian Gas Company)
2

Department of Electrical Engineering and Computer Science at Iran University of Science and Technology (IUST); Tehran, Iran
3

Department of Industrial Engineering, Payame Noor University, I. R. of Iran

(*Corresponding author: Mehdi Darbandi)

Abstract: Real crystals differ from the

ideal in that they possess imperfections or defects [1]. Some defects, due to impurity dopant atoms, are absolutely necessary for creating devices in the crystal. Other crystalline defects may be helpful if present in moderate density. Most however are undesirable, regardless of the density in which they may be found in the crystal. Various forms of defects in single-crystal and their structures, mechanisms of their formation are described by, S. Wolf and R. N. Tauber, in great detail [2]. Unwanted crystalline defects and impurities can be introduced during silicon crystal growth or subsequent wafer fabrication processes. These defects and impurities, some are undesirable because both can degrade device characteristics and overall yield. Gettering is the process whereby impurity concentrations are reduced in the device region of the wafer by localizing them in separate, predefined regions of the wafer where they cannot affect device performance. The management of metal contamination is one of the most important aspects of successful integrated circuit manufacture. Gettering has long been an important part of the silicon fabrication process. Simply, gettering is a stand-by process whereby metal contamination is rendered harmless in the event of a failure of process contamination control. This article covers some of the fundamental principles that underlie this very important technology

and discusses various approaches to the problem, highlighting the issues associated with each of them.

Introduction: All gettering techniques

are based on the fundamental physical principles of non-equilibrium (relaxation) gettering and equilibrium (segregation) gettering. In relaxation gettering techniques, such as gettering by silicon oxide precipitates heterogeneous precipitation sites are intentionally formed in the regions away from the device surface. For example, oxideprecipitate regions beneath denuded zones (DZs) can be prepared during wafer manufacturing. The relaxation gettering process requires impurity super saturation, which typically occurs during a cooling from high temperatures. Any mobile and supersaturated impurity will quickly precipitate (relax) in regions of the silicon wafer with high concentrations of precipitation sites (e.g., at silicon oxide precipitates in the bulk). On the contrary, the device/surface region is depleted of oxygen (and therefore is called the denuded zone) by a prior out-diffusion heat treatment. Hence the DZ contains a low oxideprecipitate density and thus few nucleation sites, resulting in slow precipitation of supersaturated impurities. This difference in precipitation rates creates a dissolvedimpurity concentration gradient, which causes diffusion of supersaturated impurities

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away from the device surface and into the bulk, toward the gettering sites 1.

I. Getterring process:
Efforts undertaken to eliminate the effects of impurities and defects have involved four approaches [3]: One, suppression of extended defect nucleation; Two, annihilation of existing extended defects in the device region; Three, preventing device degrading impurities from being introduced into the wafer; and Four, preventing any remaining metallic impurities from being captured in the device region. Three, preventing device degrading impurities from being introduced into the wafer; and Four, preventing any remaining metallic impurities from being captured in the device region. The most important metal contaminants in silicon are iron, nickel and copper, with copper being perhaps the most dangerous of all. The behavior of a metal like copper in silicon can be compared to common experience with gases dissolved in liquids. Copper diffusion in solid silicon in fact has much in common with diffusion in liquids; it is extremely fast and its diffusivity is not strongly temperature dependent (at least until at or below room temperature). Copper has a rather high solubility at typical process temperatures. This means that any copper in contact with the wafer surface (originating, for instance, from an improperly cleaned surface or diffusion boat) is rapidly dissolved and uniformly distributed into the wafer at high temperature like 1000C within a second. (Its important to remember that at low temperatures - in spite of its high mobility - copper will not appreciably dissolve into silicon. It is constrained by a low solubility there are however exceptions: CMP under certain conditions
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for example). Depending upon the amount of copper actually dissolved in the silicon wafer, at certain temperature during the cooling of the wafer a copper solution will become supersaturated and progressively more so upon further cooling. At some point far from equilibrium, copper precipitates out of solution and the system relaxes toward equilibrium. The form that these precipitates take is that of a copper silicide: Cu3Si.

Gettering principles:
Practical gettering systems are divided into two categories: extrinsic and intrinsic. Extrinsic gettering involves the use of external means to create damage on the surface of the silicon wafer that leads to the creation of the extended defects or chemically reactive sites at which the mobile impurities are captured. The first external gettering system used in large volumes was a backside damage achieved by abrading the surface with sandpaper an almost unbelievably crude method from todays perspective. Intrinsic gettering involves the localization of impurities at extended defects or region of high concentration of electrical impurities which within the bulk material of the silicon wafer, and whose origin is due to an intrinsic property of starting wafer. External systems. A simple way to lower the barrier to metal precipitation at a free surface is to create disorder of nearly any kind in it. If this is applied to the back surface of the wafer only then a differential between the front and back surface is achieved which alters the balance in the metal precipitation preferences between the two surfaces. Over the past 30 years or so many different back surface-disordering processes have been applied to silicon wafers to achieve preferential metal precipitation at the back surface and thus effective suppression of precipitation at the front surface. The first external gettering system used in large volumes was a

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backside damage achieved by abrading the surface with sandpaper an almost unbelievably crude method from todays perspective. Almost any kind of damage to the wafer back surface will achieve this result. Refinements to this over the years included laser damage; sand blasting and CVD deposition of a highly disordered polysilicon film applied to the backside. Backside ion-implantation damage has also been used. Several of these techniques are still in use today and to great advantage. But there are several disadvantages to these external gettering approaches, which will no doubt limit or eliminate their applicability in advanced IC applications. The first requirement is that damage applied to wafer back-surfaces should live throughout the entire IC process. In addition to this, the disordering processes should themselves be device defect neutral. The sand-blasting of silicon surfaces is known to create particlegenerating sources which can result in the transfer of particles from the back side of silicon wafers to the front side of adjacent wafers in a diffusion boat, thus in some cases causing more damage than it sought to prevent. Poly-silicon backside coatings can be oxidized away and are certainly not applicable in future double-side polished wafers. Internal systems. Essentially all silicon wafers for IC applications are grown by the Czochralski (CZ) method. An important difference between this method and the Floating Zone (FZ) method is that the silicon melt is contained in a quartz crucible. The oxygen from the crucible is dissolved into the molten silicon and incorporated in the solid crystal ingot in rather high concentrations. This excess oxygen can precipitate homogeneously, at arbitrary sites, in a silicon crystal. This can occur during the cooling of the crystal during growth and in subsequent wafer heat treatments during use. Oxygen precipitates in bulk, or interior,

of silicon wafers create disorder, which can effectively lower the barrier for the subsequent precipitation of metals just like disorder on the wafer surface. The potential for using bulk oxygen precipitates as a gettering mechanism was first proposed in 1977 [4] although the mechanisms were not clear at the time. In fact, it is known [5] that even very tiny oxygen precipitates at very early stages of growth can result in energy barriers lower than that of a free surface and thus offer the potential for very effective suppression of surface precipitation and thus gettering. A huge effort has been extended in the years since the realization of this effect to harness the potential of bulk oxygen precipitates to manage metal contamination.

Figure 1: Independence of Application: Despite large differences in the IC thermal process details, the PFZ depths and BMD densities are nearly the same for all four different processes

The Magic Denuded Zone (MDZ) wafer: The new feature, called Magic Denuded Zone (MDZ), produces internal gettering action during device processing more reliably than has been previously possible. The control of oxygen behavior in silicon wafers has been a significant problem for semiconductor manufacturers during the last

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two decades. Companies have needed to use special wafer treatments, all customized to the specific crystal process and device processing sequence being used. MDZ preprograms a wafer to provide both a controlled denuded-zone depth and oxygenprecipitate density in essentially any deviceprocessing sequence with no extra intervention required by the device manufacturer. The engineering challenge is to insure that sufficient densities of oxygen precipitates are robustly and reliably produced in arbitrary IC processes and that a surface layer free of oxygen precipitates (a denuded zone) is produced in the wafer during the processing of the wafer. The denuded zone is required to avoid the presence of oxide precipitates in the near surface device layer in order to avoid detrimental effects of oxygen precipitates themselves. This is usually achieved by causing the dissolved oxygen in the wafer to out-diffuse at high temperature prior or during the nucleation of the oxygen precipitates in the bulk. A sufficient density in the bulk of the silicon wafer is required. This is to insure that, once metal precipitation starts at the oxide precipitate sites, these volume distributed sinks for metal diffusion are of a sufficiently high density to insure that a sufficient suppression of the metal concentration near the front surface in order to suppress metal precipitation. The MDZ process can be applied to any polished silicon wafer and to P/P-epitaxial wafers to provide a well-defined and predictable level of internal gettering and denuded zone depth during integrated-circuit fabrication. Because the process does not use long thermal treatments during IC fabrication, manufacturers can simplify their processes by eliminating a number of steps at the onset of device manufacturing. In addition to saving manufacturing costs, the technique has increased yields during the
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past 18 months of testing in both 150mm

Figure 2: An illustration of the phenomenon of surface precipitation of copper in the absence of effective gettering. Here a half-wafer has been contaminated with copper and then heated to 900C and cooled. After the heat treatment, the bottom half (below the bright line) was then angle etched with a non-defect delineating etch to an average depth of only about 2.5 microns below the surface. Then the entire sample was then defect etched to reveal copper silicide precipitates. These are found only in the upper half of the sample (seen here in (a) as a haze resulting from light scattering off a very high density of etch pits). In the lower half, the surface precipitates where etched away prior to the defect delineation. (b) shows illustrative micrographs of the etch pit structure in the two halves.

and 200mm MDZ-treated wafers.

II. Applications and research:

MEMC Electronic Materials, Inc.1 has announced the development of an advanced silicon wafer innovation for use in microelectronic applications. Wafers with this new feature, called Magic Denuded ZoneT (MDZT), produce internal gettering action during device processing far more reliably than has been achieved to date. This provides greater long-term manufacturing yield stability for customers. The principle
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behind the technique relies on patented technologies developed by MEMC that effectively and accurately control the distribution of crystal lattice vacancies in the wafers. The MDZT process can be applied to any polished silicon wafer and to P/Pepitaxial wafers to provide a well-defined and predictable level of internal gettering and denuded zone depth during integrated circuit fabrication. Department of Materials Science and Engineering, University of California at Berkeley, and Lawrence Berkeley National Laboratory [6], have jointly performed modeling of gettering and re-dissolution of iron during a variety of annealing sequences used in integrated circuits processing. The simulations are based on the new empirical equation obtained for the iron re-dissolution time constant which shows a significant binding between the gettered iron and oxide precipitates. The results show that a typical rapid thermal annealing does not completely dissolve the gettered iron. Physikalisches Institut, Universitt Gttingen, Bunsenstr. Germany [7]: have studied external gettering of radioactive 57Co in silicon containing different amounts of oxygen impurities. As a gettering layer we used a thin Au-layer. The amount of gettered cobalt was measured insitu. We find that for oxygen concentrations below of 1 6 10 17 cm 3 (ASTM F-121) cobalt diffuses into the Au:Si-layer according to the temperature dependent segregation coefficient which leads to an increase of the gettering effect with decreasing temperature. Oliver Schultz, Stephan Riepe and Stefan W. Glunz [8] in their paper described: several combinations of oxidation and phosphorus diffusion processes suitable for silicon solar cell processing were applied to solar grade multicrystalline silicon. This resulted in drastic changes of the minority carrier lifetime. The effect of extended light exposure of the samples was measured with

injection level dependent lifetime spectroscopy. This revealed iron as a contaminant source present in non-treated samples, which could significantly be reduced by an appropriate phosphorus diffusion. To monitor the changes with a high spatial resolution the Carrier Density Imaging (CDI) technique was applied showing distinct differences between oxidations and diffusions. Kittler and Seifert [10] from Germany, have discussed the effect of gettering and hydrogen passivation on the recombination activity of contaminated dislocations. It is demonstrated that a residual amount of dislocation states: in the order of 104 cm-1 remains active even under optimum processing conditions, which sets an upper limit to the diffusion length in dislocated solar-grade silicon. Based on an analysis of DLTS investigations on misfit dislocations, they show that impurities may either be accommodated in the dislocation core or in a cloud around the dislocation. They suggest that the former are at the origin of the limited efficiency of gettering and passivation. Department of Physics at University of Bolognaand and University of Konstanz, in Germany [9], have researched the present contribution the effect of the processing steps on the characteristics of ribbon-, castmulticrystalline and Cz monocrystalline Si is investigated by SPV (Surface PhotoVoltage) analyses. The minority carrier diffusion length LD has been measured by SPV in noncontact and nondestructive mode at the different processing steps employed in solar cell processing. Kittler and Seifert [10] from Germany, have discussed the effect of gettering and hydrogen passivation on the recombination activity of contaminated dislocations. It is demonstrated that a residual amount of dislocation states: in the order of 104 cm-1 remains active even under optimum

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processing conditions, which sets an upper limit to the diffusion length in dislocated solar-grade silicon. Based on an analysis of DLTS investigations on misfit dislocations, they show that impurities may either be accommodated in the dislocation core or in a cloud around the dislocation. They suggest that the former are at the origin of the limited efficiency of gettering and passivation.

Conclusion:
Effective gettering is required to produce high-yielding ULSI wafers. Variety of gettering techniques has been described. In practice more than one gettering mechanism is likely to be exploited in a wafer during fabrication. An extrinsic, backside technique and an intrinsic gettering process can be employed concurrently. As low temperature processes, and/or RTP, because more extensively utilized however, it is likely that the use of intrinsic gettering will no longer be left to chance. The reduced thermal cycles of these processes will be demand use of a gettering technique, which allows the placement of gettering sinks closer to active device regions. The intrinsic gettering model however does not require the strict control of a number of oxygen-related processes, and this can be a complex task. Recent reports indicate that extrinsic gettering is more effective at capturing some of the metallic impurities found in silicon (i.e. Cu and Ni), but that intrinsic gettering is better at capturing other metals (especially Fe). As a result, it is suggested that gettering is accomplished most successfully if both types are employed simultaneously1.

References:

1. K.V. Ravi, Imperfections and Impurities in Semiconductor Silicon, Wiley, New York, 1981. 2. S. Wolf and R.N. Tauber, Silicon Processing for VLSI Era, Volume 1Process Technology 2nd Edition, Lattice Press Sunset Beach, California 3. G. A. Rozgonyi, Trends in Defects and Impurity Control for Fine Line VLSI Processing, Defects in Silicon, Electrochem. Soc., Pennington, N.J., 1983, p.20. 4. T.Y. Tan, E.E. Gardner and W.K. Tice, Appl. Phys. Lett., 30, p. 175 (1977). 5. R Falster and W Bergholz, J. Electrochem. Soc., 137, 1548 (1990). 6. P. Zhang, A. Haarahiltunen, A. Istratov, E.R. Weber , Simulations of Iron ReDissolution from Oxygen Precipitates in Cz-Silicon and its Impact on Gettering Efficiency, Department of Materials Science and Engineering, University of California at Berkeley, and Lawrence Berkeley National Laboratory, MS 62R0203, 1 Cyclotron Road, Berkeley, CA 94720, USA 7. Seibt, V. Kveder , W. Schrter IV.,Interaction of Interstitially Dissolved Cobalt and Oxygen-Related Centres in Silicon, Physikalisches Institut, Universit t Gttingen, Bunsenstr. 13-15, D-37073 Gttingen, Germany now at: Wacker Siltronic, P.O.Box 1140, D-84479 Burghausen, Germany 8. Oliver Schultz, Stephan Riepe and Stefan W. Glunz,Properties of Cavities Induced by Helium Implantation in Silicon and their Applications to Devices Influence of High-Temperature Processes on Multicrystalline Silicone of High-temperature Processes on Multicrystalline Silicon, Fraunhofer ISE, Heidenhofstr. 2, 79110 Freiburg, Germany

S. Wolf and R.N. Tauber, Silicon Processing for VLSI Era Volume 1- Process Technology 2nd Edition

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9. D.Cavalcoli, A.Cavallini, M.Rossi and K.Peter, Minority Carrier Diffusion Lengths in Multi-Crystalline Silicon Wafers and Solar Cells Carrier Diffusion Lengths in Multi-crystalline Silicon Wafers and Solar Cells, INFM and Physics Department, University of Bologna, University of Konstanz, Department of Physics, D-78457 Konstanz Germany. 10. M. Kittler and W. Seifert IHP, Postfach, Limitation of the Action of Gettering and Passivation on Dislocations Limitation of the action of gettering and passivation on dislocations, 1466, 15204 Frankfurt (Oder), Germany 11. Eicke R. Weber, Materials Science & Engineering, 374 Hearst Memorial Mining BuildingUniversity of California at Berkeley, Berkeley CA 94720. BIOGRAPHIES:

Pouria Ilka:
MSc. Student at Department of Electrical Engineering and Computer Science at Iran University of Science and Technology (IUST); Tehran, Iran. His e-mail address is:

Mehdi Darbandi:
Department of Electrical Engineering and Computer Science at Iran University of Science and Technology (IUST); Tehran, Iran. His e-mail address is:

Mohammad Golmakani:
Department of Industrial Engineering, Payame Noor University, I. R. of Iran. His email address is:

2012 Journal of Computing Press, NY, USA, ISSN 2151-9617