APPLICATION

NOTE
AP-252
Maich 1985
Designing With The 80C51BH
TOM WILLIAMSON
MCO APPLICATIONS FNOINFFR
Order Number 270068-002
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoev-
er including infringement of any patent or copyright for sale and use of Intel products except as provided in
Intels Terms and Conditions of Sale for such products
Intel retains the right to make changes to these specifications at any time without notice Microcomputer
Products may have minor variations to this specification known as errata
Other brands and names are the property of their respective owners
Since publication of documents referenced in this document registration of the Pentium OverDrive and
iCOMP trademarks has been issued to Intel Corporation
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your
product order
Copies of documents which have an ordering number and are referenced in this document or other Intel
literature may be obtained from
Intel Corporation
PO Box 7641
Mt Prospect IL 60056-7641
or call 1-800-879-4683
COPYRIGHT INTEL CORPORATION 1996
DESIGNING WITH THE
80C51BH
CONTENTS PAGE
CMOS EVOLVES 1
WHAT IS CHMOS 1
THE MCS-51 FAMILY IN CHMOS 1
LATCHUP 2
LOGIC LEVELS AND INTERFACING
PROBLEMS 2
NOISE CONSIDERATIONS 2
UNUSED PINS 3
PULLUP RESISTORS 4
PULLDOWN RESISTORS 4
DRIVE CAPABILITY OF THE
INTERNAL PULLUPS 5
POWER CONSUMPTION 6
Idle 7
Power Down 7
USING THE POWER DOWN MODE 8
USING POWER MOSFETs TO
CONTROL V
CC
9
BATTERY BACKUP SYSTEMS 9
POWER SWITCHOVER CIRCUITS 11
80C31BH
a
CHMOS EPROM 12
SCANNING A KEYBOARD 13
DRIVING AN LCD 16
Using an LCD Driver 17
RESONANT TRANSDUCERS 18
Frequency Measurements 18
Period Measurements 20
Pulse Width Measurements 21
HMOSCHMOS
INTERCHANGEABILITY 21
External Clock Drive 21
Unused Pins 22
Logic Levels 22
Idle and Power Down 22
REFERENCES 23
AP-252
CMOS EVOLVES
The oiiginaI CMOS Iogic famiIies weie the 4000-seiies
and the 74C-seiies ciicuits. The 74C-seiies ciicuits aie
functionaI equivaIents to the coiiesponding numbeied
74-seiies TTL ciicuits, but have CMOS Iogic IeveIs and
ietain the othei weII known chaiacteiistics of CMOS
Iogic.
These chaiacteiistics aie: Iow powei consumption, high
noise immunity, and sIow speed. The Iow powei con-
sumption is inheient to the natuie of the CMOS ciicuit.
The noise immunity is due paitIy to the CMOS Iogic
IeveIs, and paitIy to the sIowness of the ciicuits. The
sIow speed is due to the technoIogy used to constiuct
the tiansistois in the ciicuit.
The technoIogy used is caIIed metaI-gate CMOS, be-
cause the tiansistoi gates aie foimed by metaI deposi-
tion. Moie impoitantIy, the gates aie foimed aftei the
diain and souice iegions have been defined, and must
oveiIap the souice and diain somewhat to aIIow foi
aIignment toIeiances. This oveiIap pIus the ieIativeIy
Iaige size of the tiansistois themseIves iesuIt in high
eIectiode capacitance, and that is what Iimits the speed
of the ciicuit.
High speed CMOS became feasibIe with the deveIop-
ment of the seIf-aIigning siIicon gate technoIogy. In this
piocess poIysiIicon gates aie deposited before the
souice and diain iegions aie defined. Then the souice
and diain iegions aie foimed by ion impIantation using
the gate itseIf as a mask foi the impIantation. This eIim-
inates most of the oveiIap capacitance. In addition, the
piocess aIIows smaIIei tiansistois. The iesuIt is a signif-
icant inciease in ciicuit speed. The 74HC-seiies of
CMOS Iogic ciicuits is based on this technoIogy, and
has speeds compaiabIe to LS TTL, which is to say
about 10 times fastei than the 74C-seiies ciicuits.
The size ieduction that contiibutes to the highei speed
aIso demands an accompanying ieduction in the maxi-
mum suppIy voItage. High-speed CMOS is geneiaIIy
Iimited to 6V.
WHAT IS CHMOS
CHMOS is the name given to InteIs high-speed CMOS
piocesses. Theie aie two CHMOS piocesses, one based
on an n-weII stiuctuie and one based on a p-weII stiuc-
tuie. In the n-weII stiuctuie, n-type weIIs aie diffused
into a p-type substiate. Then the n-channeI tiansistois
(nFFTs) aie buiIt into the substiate and pFFTs aie
buiIt into the n-weIIs. In the p-weII stiuctuie, p-type
weIIs aie diffused into an n-type substiate. Then the
nFFTs aie buiIt into the weIIs and pFFTs, into the
substiate. Both piocesses have theii advantages and
disadvantages, which aie IaigeIy tianspaient to the
usei.
Lowei opeiating voItages aie easiei to obtain with the
p-weII stiuctuie than with the n-weII stiuctuie. But the
p-weII stiuctuie does not easiIy adapt to an FPROM
which wouId be pin-foi-pin compatibIe with HMOS
FPROMs. On the othei hand the n-weII stiuctuie can
be based on the soIidIy founded HMOS piocess, in
which nFFTs aie buiIt into a p-type substiate. This
aIIows somewhat moie than haIf of the tiansistois in a
CHMOS chip to be constiucted by piocesses that aie
aIieady weII chaiacteiized.
CuiientIy InteIs CHMOS miciocontioIIeis and memo-
iy pioducts aie n-weII devices, wheieas CHMOS mi-
ciopiocessois aie p-weII devices.
Fuithei discussion of the CHMOS technoIogy is pio-
vided in Refeiences 1 and 2 (which aie iepiinted in the
MiciocontioIIei Handbook).
THE MCS-51 FAMILY IN CHMOS
The 80C51BH is the CHMOS veision of InteIs oiiginaI
8051. The 80C31BH is the ROMIess 80C51BH, equiva-
Ient to the 8031. These CHMOS devices aie aichitec-
tuiaIIy identicaI with theii HMOS counteipaits, except
that they have two added featuies foi ieduced powei.
These aie the IdIe and Powei Down modes of opeia-
tion.
In most cases, an 80C51BH can diiectIy iepIace the
8051 in existing appIications. It can execute the same
code at the same speed, accept signaIs fiom the same
souices, and diive the same Ioads. Howevei, the
80C51BH coveis a widei iange of speeds, wiII emit
CMOS Iogic IeveIs to CMOS Ioads, and wiII diaw about
1/10 the cuiient of an 8051 (and Iess yet in the ieduced
powei modes). InteichangeabiIity between the HMOS
and CHMOS devices is discussed in moie detaiI in the
finaI section of this AppIication Note.
It shouId be noted that the 80C51BH CPU is not static.
That means if the cIock fiequency is too Iow, the CPU
might foiget what it was doing. This is because the
ciicuitiy uses a numbei of dynamic nodes. A dynamic
node is one that uses the note-to-giound capacitance to
foim a tempoiaiy stoiage ceII. Dynamic nodes aie used
to ieduce the tiansistoi count, and hence the chip aiea,
thus to pioduce a moie economicaI device.
This is not to say that the on-chip RAM in CHMOS
miciocontioIIeis is dynamic. Its not. Its the CPU that
is dynamic, and that is what imposes the minimum
cIock fiequency specification.
1
AP-252
LATCHUP
Latchup is an SCR-type tuin-on phenomenon that is
the tiaditionaI nemesis of CMOS systems. The sub-
stiate, the weIIs, and the tiansistois foim paiasitic pnpn
stiuctuies within the device. These paiasitic stiuctuies
tuin on Iike an SCR if a sufficient amount of foiwaid
cuiient is diiven thiough one of the junctions. Fiom
the ciicuit designeis point of view it can happen when-
evei an input oi output pin is exteinaIIy diiven a diode
diop above V
CC
oi beIow V
SS
, by a souice that is capa-
bIe of suppIying the iequiied tiiggei cuiient.
Howevei much of a piobIem Iatchup has been in the
past, it is good to know that in most iecentIy deveIoped
CMOS devices, and specificaIIy in CHMOS devices, the
cuiient iequiied to tiiggei Iatchup is typicaIIy weII ovei
100 mA. The 80C51BH is viituaIIy immune to Iatchup.
(Refeiences 1 and 2 piesent a discussion of the Iatchup
mechanisms and the steps that aie taken on the chip to
guaid against it.) Modein CMOS is not absoIuteIy im-
mune to Iatchup, but with tiiggei cuiients in the hun-
dieds of mA, Iatchup is ceitainIy a Iot easiei to avoid
than it once was.
A caieIess powei-up sequence might tiiggei a Iatchup
in the oIdei CMOS famiIies, but its unIikeIy to be a
majoi piobIem in high-speed CMOS oi in CHMOS.
Theie is stiII some iisk incuiied in inseiting oi iemov-
ing chips oi boaids in a CMOS system whiIe the powei
is on. AIso, seveie tiansients, such as inductive kicks oi
momentaiy shoit-ciicuits, can exceed the tiiggei cui-
ient foi Iatchup.
Foi appIications in which some Iatchup iisk seems un-
avoidabIe, you can put a smaII iesistoi (100X oi so) in
seiies with signaI Iines to ensuie that the tiiggei cuiient
wiII nevei be ieached. This aIso heIps to contioI ovei-
shoot and RFI.
LOGIC LEVELS AND INTERFACING
PROBLEMS
CMOS Iogic IeveIs diffei fiom TTL IeveIs in two ways.
Fiist, foi equaI suppIy voItages, CMOS gives (and ie-
quiies) a highei Iogic 1 IeveI than TTL. SecondIy,
CMOS Iogic IeveIs aie V
CC
(oi VDD) dependent,
wheieas guaianteed TTL Iogic IeveIs aie fixed when
V
CC
is within TTL specs.
Standaid 74HC Iogic IeveIs aie as foIIows:
V
IH
MIN e 70% of V
CC
V
IL
MAX e 20% of V
CC
V
OH
MIN e V
CC
b 01V
l
I
OHl
s
20 mA
V
OL
MAX e 01V
l
I
OLl
s
20 mA
Figuie 1 compaies 74HC, LS TTL, and 74HCT Iogic
IeveIs with those of the HMOS 8051 and the CHMOS
80C51BH foi V
CC
e
5V.
Output Iogic IeveIs depend of couise on Ioad cuiient,
and aie noimaIIy specified at seveiaI Ioad cuiients.
When CMOS and TTL aie poweied by the same V
CC
,
the Iogic IeveIs guaianteed on the data sheets indicate
that CMOS can diive TTL, but TTL cant diive
CMOS. The incompatibiIity is that the TTL ciicuits
V
OH
IeveI is too Iow to ieIiabIy be iecognized by the
CMOS ciicuit as a vaIid V
IH
.
Since HMOS ciicuits weie designed to be TTL-compat-
ibIe, they have the same incompatibiIity.
FoitunateIy, 74HCT-seiies ciicuits aie avaiIabIe to ease
these inteifacing piobIems. They have TTL-compatibIe
Iogic IeveIs at the inputs and standaid CMOS IeveIs at
the outputs.
The 80C51BH is designed to woik with eithei TTL oi
CMOS. Theiefoie its Iogic IeveIs aie specified veiy
much Iike 74HCT ciicuits. That is, its input Iogic IeveIs
aie TTL-compatibIe, and its output chaiacteiistics aie
Iike standaid high-speed CMOS.
NOISE CONSIDERATIONS
One of the majoi ieasons foi going to CMOS has tiadi-
tionaIIy been that CMOS is Iess susceptibIe to noise. As
pieviousIy noted, its Iow susceptibiIity to noise is
Logic State
V
CC
e
5V
74HC 74HCT LS TTL 8051 80C51BH
V
IH
35V 20V 20V 20V 19V
V
IL
10V 08V 08V 08V 09V
V
OH
49V 49V 27V 24V 45V
V
OL
01V 01V 05V 045V 045V
Figure 1 Logic Level Comparison (Output voltage levels depend on load current
Data sheets list guaranteed output levels for several load currents The output
levels listed here are for minimum loading)
2
AP-252
paitIy due to supeiioi noise maigins, and paitIy due to
its sIow speed.
Noise maigin is the diffeience between V
OL
and V
IL
,
oi between V
OH
and V
IH
. If V
OH
fiom a diiving cii-
cuit is 2.7V and V
IH
to the diiven ciicuit is 2.0V, then
the diiven ciicuit has 0.7V of noise maigin at the Iogic
high IeveI. These kinds of compaiisons show that an
aII-CMOS system has widei noise maigins than an aII-
TTL system.
Figuie 2 shows noise maigins in CMOS and LS TTL
systems when both have V
CC
e
5V. It can be seen that
CMOS/CMOS and CMOS/CHMOS systems have an
edge ovei LS TTL in this iespect.
Noise maigins can be misIeading, howevei, because
they dont say how much noise eneigy it takes to induce
in the ciicuit a noise voItage of sufficient ampIitude to
cause a Iogic eiioi. This wouId invoIve consideiation of
the width of the noise puIse as compaied with the cii-
cuits iesponse speed, and the impedance to giound
fiom the point of noise intioduction in the ciicuit.
When these consideiations aie incIuded, it is seen that
using the sIowei 74C- and 4000-seiies ciicuits with a 12
oi 15V suppIy voItage does offei a tiuIy impioved IeveI
of noise immunity, but that high-speed CMOS at 5V is
not significantIy bettei than TTL.
One shouId not mistake the widei suppIy voItage toIei-
ance of high-speed CMOS foi V
CC
gIitch immunity.
SuppIy voItage toIeiance is a DC iating, not a gIitch
iating.
Foi any cIocked CMOS, and most especiaIIy foi VLSI
CMOS, V
CC
decoupIing is ciiticaI. CHMOS diaws
Noise Margin for
Interface
V
CC
e
5V
Logic Low Logic High
V
IL
V
OL
V
OH
V
IH
74HC to 74HC 09V 14V
LSTTL to LSTTL 03V 07V
LSTTL to 74HCT 03V 07V
LSTTL to 80C51BH 03V 07V
74HC to 80C51BH 08V 30V
80C51BH to 74HC 08V 10V
Figure 2 Noise Margins for CMOS
and LS TTL Circuits
cuiient in extiemeIy shaip spikes at the cIock edges.
The VHF and UHF components of these spikes aie not
diawn fiom the powei suppIy, but fiom the decoupIing
capacitoi. If the decoupIing ciicuit is not sufficientIy
Iow in inductance, V
CC
wiII gIitch at each cIock edge.
We suggest that a 0.1 mF decoupIei cap be used in a
minimum-inductance configuiation with the miciocon-
tioIIei. A minimum-inductance configuiation is one
that minimizes the aiea of the Ioop foimed by the chip
(V
CC
to V
SS
), the tiaces to the decoupIei cap, and the
decoupIei cap. PCB designeis too often faiI to undei-
stand that if the tiaces that connect the decoupIei cap
to the V
CC
and V
SS
pins aient shoit and diiect, the
decoupIei Ioses much of its effectiveness.
Oveishoot and iinging in signaI Iines aie potentiaI
souices of Iogic upsets. These can IaigeIy be contioIIed
by ciicuit Iayout. Inseiting smaII iesistois (about 100X)
in seiies with signaI Iines that seem to need them wiII
aIso heIp.
The shaip edges pioduced by high-speed CMOS can
cause RFI piobIems. The seveiity of these piobIems is
IaigeIy a function of the PCB Iayout. We dont mean to
impIy that aII RFI piobIems can be soIved by a bettei
PCB Iayout. It may weII be, foi exampIe, that in some
RFI-sensitive designs high-speed CMOS is simpIy not
the answei. But ciicuit Iayout is a ciiticaI factoi in the
noise peifoimance of any eIectionic system, and moie
so in high-speed CMOS systems than otheis.
Ciicuit Iayout techniques foi minimizing noise suscepti-
biIity and geneiation aie discussed in Refeiences 3
thiough 6.
UNUSED PINS
CMOS input pins shouId not be Ieft to fIoat, but shouId
aIways be puIIed to one Iogic IeveI oi the othei. If they
fIoat, they tend to fIoat into the tiansition iegion be-
tween 0 and 1, wheie the puIIup and puIIdown devices
in the input buffei aie both conductive. This causes a
significant inciease in I
CC
. A simiIai effect exists in
HMOS ciicuits, but with Iess noticeabIe iesuIts.
In 80C51BH and 80C31BH designs, unused pins of
Poits 1, 2, and 3 can be ignoied, because they have
inteinaI puIIups that wiII hoId them at a vaIid Logic 1
IeveI. Poit 0 pins aie diffeient, howevei, in not having
inteinaI puIIups (except duiing bus opeiations).
When the 80C51BH is in ieset, the Poit 0 pins aie in a
fIoat state unIess they aie exteinaIIy puIIed up oi down.
If its going to be heId in ieset foi just a shoit time, the
tiansient fIoat state can piobabIy be ignoied. When it
comes out of ieset, the pins stay afIoat unIess
3
AP-252
they aie exteinaIIy puIIed eithei up oi down. AIteina-
tiveIy, the softwaie can inteinaIIy wiite 0s to whatevei
Poit 0 pins may be unused.
The same consideiations aie appIicabIe to the
80C31BH with iegaids to ieset. But when the
80C31BH comes out of ieset, it commences bus opeia-
tions, duiing which the Iogic IeveIs at the pins aie aI-
ways weII defined as high oi Iow.
Considei the 80C31BH in the Powei Down oi IdIe
modes, howevei. In those modes it is not fetching in-
stiuctions, and the Poit 0 pins wiII fIoat if not exteinaI-
Iy puIIed high oi Iow. The choice of whethei to puII
them high oi Iow is the designeis. NoimaIIy it is suffi-
cient to puII them up to V
CC
with 10k iesistois. But if
powei is going to be iemoved fiom ciicuits that aie
connected to the bus, it wiII be advisabIe to puII the bus
pins down (noimaIIy with 10k iesistois). Consideia-
tions invoIved in seIecting puIIup and puIIdown iesistoi
vaIues aie as foIIows.
2700681
Figure 3a Conditions defining the minimum
value for R P0X is emitting a logic low R must
be large enough to not cause IOL to exceed
data sheet specifications
2700682
Figure 3b Conditions defining the maximum
value for R P0X is in a high impedance
state R must be small enough to keep
V
OH
acceptably high
PULLUP RESISTORS
If a puIIup iesistoi is to be used on a Poit 0 pin, its
minimum vaIue is deteimined by I
OL
iequiiements. If
the pin is tiying to emit a 0, then it wiII have to sink the
cuiient fiom the puIIup iesistoi pIus whatevei othei
cuiient may be souiced by othei Ioads connected to the
pin, as shown in Figuie 3a, whiIe maintaining a vaIid
output Iow (V
OL
). To guaiantee that the pin voItage
wiII not exceed 0.45V, the iesistoi shouId be seIected so
that I
OL
doesnt exceed the vaIue specified on the data
sheet. In most CMOS appIications, the minimum vaIue
wouId be about 2k X.
The maximum vaIue you couId use depends on how
fast you want the pin to puII up aftei bus opeiations
have ceased, and how high you want the V
OH
IeveI to
be. The smaIIei the iesistoi the fastei it puIIs up. Its
effect on the V
OH
IeveI is that V
OH
e
V
CC
b
(ILI
a
IIH)
c
R. ILI is the input Ieakage cuiient to the Poit 0
pin, and IIH is the input high cuiient to the exteinaI
Ioads, as shown in Figuie 3b. NoimaIIy V
OH
can be
expected to ieach 0.9 V
CC
if the puIIup iesistance does
not exceed about 50k X.
Pulldown Resistors
If a puIIdown iesistoi is to be used on a Poit 0 pin, its
minimum vaIue is deteimined by V
OH
iequiiements
duiing bus opeiations, and its maximum vaIue is in
most cases deteimined by Ieakage cuiient.
Duiing bus opeiations the poit uses inteinaI puIIups to
emit 1s. The D.C. Chaiacteiistics in the data sheet Iist
guaianteed V
OH
IeveIs foi given I
OH
cuiients. (The -
sign in the I
OH
vaIue means the pin is souicing that
cuiient to the exteinaI Ioad, as shown in Figuie 4.) To
ensuie the V
OH
IeveI Iisted in the data sheet, the iesis-
2700683
Figure 4a Conditions defining the minimum
value for R P0X is emitting a 1 in a bus
operation R must be large enough to not cause
IOH to exceed data sheet specifications
4
AP-252
V
OH
R
a I
IH
s
l
I
OHl
toi has to satisfy wheie I
IH
is the input high cuiient to
the exteinaI Ioads.
When the pin goes into a high impedance state, the
puIIdown iesistoi wiII have to sink Ieakage cuiient
fiom the pin, pIus whatevei othei cuiient may be
souiced by othei Ioads connected to the pin, as shown
in Figuie 4b. The Poit 0 Ieakage cuiient is I
LI
on the
data sheet. The iesistoi shouId be seIected so that the
voItage deveIoped acioss it by these cuiients wiII be
seen as a Iogic Iow by whatevei ciicuits aie connected
to it (incIuding the 80C51BH). In CMOS/CHMOS ap-
pIications, 50k X is noimaIIy a ieasonabIe maximum
vaIue.
2700684
Figure 4b Conditions defining the maximum
value for R P0X is in a high impedance state
R must be small enough to keep VOL
acceptably low
DRIVE CAPABILITY OF THE
INTERNAL PULLUPS
Theies an impoitant diffeience between HMOS and
CHMOS poit diiveis. The pins of Poits 1, 2, and 3 of
the CHMOS paits each have thiee puIIups: stiong, noi-
maI, and weak, as shown in Figuie 5. The stiong puIIup
(p1) is onIy used duiing 0-to-1 tiansitions, to hasten the
tiansition. The weak puIIup (p2) is on whenevei the bit
Iatch contains a 1. The noimaI puIIup (p3) is con-
tioIIed by the pin voItage itseIf.
The ieason that p3 is contioIIed by the pin voItage is
that if the pin is being used as an input, and the exteinaI
souice puIIs it to a Iow, then tuining off p3 makes foi a
Iowei I
IL
. The data sheet shows an I
TL
specification.
This is the cuiient that p3 wiII souice duiing the time
the pin voItage is making its 1-to-0 tiansition. This is
what I
IL
wouId be if an input Iow at the pin didnt tuin
p3 off.
Note, howevei, that this p3 tuin-off mechanism puts a
iestiiction on the diive capacity of the pin if its being
used as an output. If youie tiying to output a Iogic
high, and the exteinaI Ioad puIIs the pin voItage beIow
the pins V
IH
MIN spec, p3 might tuin off, Ieaving onIy
the weak p2 to piovide diive to the Ioad. To pievent
this happening, you need to ensuie that the Ioad doesnt
diaw moie than the I
OH
spec foi a vaIid V
OH
. The idea
is to make suie the pin voItage nevei faIIs beIow its own
V
IH
MIN specification.
2700685
Figure 5 80C51BH Output Drivers for Ports 1 2 and 3
5
AP-252
POWER CONSUMPTION
The main ieason foi going to CMOS, of couise, is to
conseive powei. (Theie aie othei ieasons, but this is the
main one.) Conseiving powei doesnt mean just ieduc-
ing youi eIectiic biII. Noi does it necessaiiIy ieIate to
batteiy opeiation, aIthough batteiy opeiation without
CMOS is pietty unhandy. The main ieason foi conseiv-
ing powei is to be abIe to put moie functionaIity into a
smaIIei space. The ieduced powei consumption aIIows
the use of smaIIei and Iightei powei suppIies, and Iess
heat being geneiated aIIows densei packaging of ciicuit
components. Fxpensive fans and bIoweis can usuaIIy be
eIiminated.
A cooIei iunning chip is aIso moie ieIiabIe, since most
iandom and weaiout faiIuies ieIate to die tempeiatuie.
And finaIIy, the Iowei powei dissipation wiII aIIow
moie functions to be integiated onto the chip.
The ieason CMOS consumes Iess powei than NMOS is
that when its in a stabIe state theie is no path of con-
duction fiom V
CC
to V
SS
except thiough vaiious Ieak-
age paths. CMOS does diaw cuiient when its changing
states. How much cuiient it diaws depends on how
often and how quickIy it changes states.
2700686
Figure 6 80C51BH ICC vs Clock Frequency
CMOS ciicuits diaw cuiient in shaip spikes duiing Iog-
icaI tiansitions. These cuiient spikes aie made up of
two components. One is the cuiient that fIows duiing
the tiansition time when puIIup and puIIdown FFTs aie
both active. The aveiage (DC) vaIue of this component
is Iaigei when the tiansition times of the input signaIs
aie Iongei. Foi this ieason, if the cuiient diaw is a
ciiticaI factoi in the design, sIow iise and faII times
shouId be avoided, even when the system speed doesnt
seem to justify a need foi nanosecond switching speeds.
The othei component is the cuiient that chaiges stiay
and Ioad capacitance at the nodes of a CMOS Iogic
gate. The aveiage vaIue of this cuiient spike is its aiea
(integiaI ovei time) muItipIied by its iep iate. Its aiea is
the amount of chaige it takes to iaise the node capaci-
tance, C, to V
CC
. That amount of chaige is just C x
V
CC
. So the aveiage vaIue of the cuiient spike is C x
V
CC
x f, wheie f is the cIock fiequency.
This component of cuiient incieases IineaiIy with cIock
fiequency. Foi minimaI cuiient diaw, the 80C52BH-2
is specd to iun at fiequencies as Iow as 500 kHz.
Keep in mind, though, that othei component of cuiient
that is due to sIow iise and faII times. A sinusoid is not
the optimaI wavefoim to diive the XTAL1 pin with.
Yet ciystaI osciIIatois, incIuding the one on the
80C51BH, geneiate sinusoidaI wavefoims. Theiefoie, if
the on-chip osciIIatoi is being used, you can expect the
device to diaw moie cuiient at 500 kHz, than it does at
1.5 MHz, as shown in Figuie 6. If you deiive a good
shaip squaie wave fiom an exteinaI osciIIatoi, and use
that to diive XTAL1, then the miciocontioIIei wiII
diaw Iess cuiient. But the exteinaI osciIIatoi wiII piob-
abIy make up the diffeience.
The 80C51BH has two powei-saving featuies not avaiI-
abIe in the HMOS devices. These aie the IdIe and Pow-
ei Down modes of opeiation. The on-chip haidwaie
that impIements these ieduced powei modes is shown
in Figuie 7. Both modes aie invoked by softwaie.
2700687
Figure 7 Oscillator and Clock Circuitry Showing Idle and Power Down Hardware
6
AP-252
Idle In the IdIe Mode (IDL
e
0 in Figuie 7), the CPU
puts itseIf to sIeep by gating off its own cIock. It doesnt
stop the osciIIatoi. It just stops the inteinaI cIock signaI
fiom getting to the CPU. Since the CPU diaws 80 to 90
peicent of the chips powei, shutting it off iepiesents a
faiiIy significant powei savings. The on-chip peiipeiaIs
(timeis, seiiaI poit, inteiiupts, etc.) and RAM continue
to function as noimaI. The CPU status is pieseived in
its entiiety: the Stack Pointei, Piogiam Countei, Pio-
giam Status Woid, AccumuIatoi, and aII othei iegis-
teis maintain theii data duiing IdIe.
The IdIe Mode is invoked by setting bit 0 (IDL) of the
PCON iegistei. PCON is not bit-addiessabIe, so the bit
has to be set by a byte opeiation, such as
0RL F00R,l
The PCON iegistei aIso contains fIag bits OF0 and
OF1, which can be used foi any geneiaI puiposes, oi to
give an indication if an inteiiupt occuiied duiing noi-
maI opeiation oi duiing IdIe. In this appIication, the
instiuction that invokes IdIe aIso sets one oi both of the
fIag bits. Theii status can then be checked in the intei-
iupt ioutines.
WhiIe the device is in the IdIe Mode, ALF and PSFN
emit Iogic high (V
OH
), as shown in Figuie 8. This is so
exteinaI FPROM can be deseIected and have its output
disabIed.
The poit pins hoId the IogicaI states they had at the
time the IdIe was activated. If the device was executing
out of exteinaI piogiam memoiy, Poit 0 is Ieft in a high
impedance state and Poit 2 continues to emit the high
byte of the piogiam countei (using the stiong puIIups
to emit 1s). If the device was executing out of inteinaI
piogiam memoiy, Poits 0 and 2 continue to emit what-
evei is in the P0 and P2 iegisteis.
Theie aie two ways to teiminate IdIe. Activation of any
enabIed inteiiupt wiII cause the haidwaie to cIeai bit 0
of the PCON iegistei, teiminating the IdIe mode. The
inteiiupt wiII be seiviced, and foIIowing RFTI the next
instiuction to be executed wiII be the one foIIowing the
instiuction that invoked IdIe.
The othei way is with a haidwaie ieset. Since the cIock
osciIIatoi is stiII iunning, RST onIy needs to be heId
active foi two machine cycIes (24 osciIIatoi peiiods) to
compIete the ieset. Note that this exit fiom IdIe wiites
1s to aII the poits, initiaIizes aII SFRs to theii ieset
vaIues, and iestaits piogiam execution fiom Iocation 0.
Power Down In the Powei Down Mode (PD
e
0 in
Figuie 7), the CPU puts the whoIe chip to sIeep by
tuining off the osciIIatoi. In case it was iunning fiom
an exteinaI osciIIatoi, it aIso gates off the path to the
inteinaI phase geneiatois, so no inteinaI cIock is genei-
ated even if the exteinaI osciIIatoi is stiII iunning. The
on-chip RAM, howevei, saves its data, as Iong as V
CC
is maintained. In this mode the onIy I
CC
that fIows is
Ieakage, which is noimaIIy in the micio-amp iange.
The Powei Down Mode is invoked by setting bit 1 in
the PCON iegistei, using a byte instiuction such as
0RL F00R,2
WhiIe the device is in Powei Down, ALF and PSFN
emit Iows (V
OL
), as shown in Figuie 8. The ieason they
aie designed to emit Iows is so that powei can be ie-
moved fiom the iest of the ciicuit, if desiied, whiIe the
80CS51BH is in its Powei Down mode.
The poit pins continue to emit whatevei data was wiit-
ten to them. Note that Poit 2 emits its P2 iegistei data
even if execution was fiom exteinaI piogiam memoiy.
Pin
Internal Execution External Execution
Idle Power Down Idle Power Down
ALE 1 0 1 0
PSEN 1 0 1 0
P0 SFR Data SFR Data High-Z High-Z
P1 SFR Data SFR Data SFR Data SFR Data
P2 SFR Data SFR Data PCH SFR Data
P3 SFR Data SFR Data SFR Data SFR Data
Figure 8 Status of Pins in Idle and Power Down Modes SFR data means the port pins emit their
internal register data PCH is the high byte of the Program Counter
7
AP-252
Poit 0 aIso emits its P0 iegistei data, but if execution
was fiom exteinaI piogiam memoiy, the P0 iegistei
data is FF. The osciIIatoi is stopped, and the pait ie-
mains in this state as Iong as V
CC
is heId, and untiI it
ieceives an exteinaI ieset signaI.
The onIy exit fiom Powei Down is a haidwaie ieset.
Since the osciIIatoi was stopped, RST must be heId ac-
tive Iong enough foi the osciIIatoi to ie-stait and stabi-
Iize. Then the ieset function initiaIizes aII the SpeciaI
Function Registeis (poits, timeis, etc.) to theii ieset
vaIues, and ie-staits the piogiam fiom Iocation 0.
Theiefoie, timei ieIoads, inteiiupt enabIes, baud iates,
poit status, etc. need to be ie-estabIished. Reset does
not affect the content of the on-chip data RAM. If V
CC
was heId duiing Powei Down, the RAM data is stiII
good.
USING THE POWER DOWN MODE
The softwaie-invoked Powei Down featuie offeis a
means of ieducing the powei consumption to a meie
tiickIe in systems which aie to iemain doimant foi
some peiiod of time, whiIe ietaining impoitant data.
The usei shouId give some thought to what state the
poit pins shouId be Ieft in duiing the time the cIock is
stopped, and wiite those vaIues to the poit Iatches be-
foie invoking Powei Down.
If V
CC
is going to be heId to the entiie ciicuit, one
wouId want to wiite vaIues to the poit Iatches that
wouId deseIect peiipheiaIs befoie invoking Powei
Down. Foi exampIe, if exteinaI memoiy is being used,
the P2 SFR shouId be Ioaded with a vaIue which wiII
not geneiate an active chip seIect to any memoiy de-
vice.
In some appIications, V
CC
to pait of the system may be
shut off duiing Powei Down, so that even quiescent
and standby cuiients aie eIiminated. SignaI Iines that
connect to those chips must be biought to a Iogic Iow,
whethei the chip in question is CMOS, NMOS, oi
TTL, befoie V
CC
is shut off to them. CMOS pins have
paiasitic pn junctions to V
CC
, which wiII be foiwaid
biased if V
CC
is ieduced to zeio whiIe the pin is heId at
a Iogic high. NMOS pins often have FFTs that Iook
Iike diodes to V
CC
. TTL ciicuits may actuaIIy be dam-
aged by an input high if V
CC
e
0. Thats why the
80C51BH outputs Iows at ALF and PSFN duiing Pow-
ei Down.
Figuie 9 shows a ciicuit that can be used to tuin V
CC
off to pait of the system duiing Powei Down. The cii-
cuit wiII ensuie that the secondaiy ciicuit is not de-en-
eigized untiI aftei the 80C31BH is in Powei Down, and
that the 80C31BH does not ieceive a ieset (teiminating
the Powei Down mode) befoie the secondaiy ciicuit is
ie-eneigized. Theiefoie, the piogiam memoiy itseIf can
be pait of the secondaiy ciicuit.
2700688
Figure 9 The 80C31BH de-energizes part of the circuit (VCC2) when it goes into Power Down
Selections of R and Q2 depend on VCC2 current draw
8
AP-252
In Figuie 9, when V
CC
is switched on to the 80C31BH,
capacitoi C1 piovides a powei-on ieset. The ieset func-
tion wiites 1s to aII the poit pins. The 1 at P2.6 tuins
Q1 on, enabIing V
CC
to the secondaiy ciicuit thiough
tiansistoi Q2. As the 80C31BH comes out of ieset, Poit
2 commences emitting the high byte of the Piogiam
Countei, which iesuIts in the P2.7 and P2.6 pins out-
putting 0s. The 0 at P2.7 ensuies continuation of V
CC
to the secondaiy ciicuit.
The system softwaie must now wiite a 1 to P2.7 and a 0
to P2.6 in the Poit 2 SFR, P2. These vaIues wiII not
appeai at the Poit 2 pins as Iong as the device is fetch-
ing instiuctions fiom exteinaI piogiam memoiy. How-
evei, whenevei the 80C31BH goes into Powei Down,
these vaIues wiII appeai at the poit pins, and wiII shut
off both tiansistois, disabIing V
CC
to the secondaiy cii-
cuit.
CIosing the switch S1 ie-eneigizes the secondaiy cii-
cuit, and at the same time sends a ieset thiough C2 to
the 80C31BH to wake it up. The diode D1 is to pievent
C1 fiom hogging cuiient fiom C2 duiing this second-
aiy ieset. D2 pievents C2 fiom dischaiging thiough the
RST pin when V
CC
to the secondaiy ciicuit goes to
zeio.
2700689
a Using a pFET
27006828
b Using an nFET
Figure 10 Using Power MOSFETs
to Control VCC2
USING POWER MOSFETs to
CONTROL V
CC
Powei MOSFFTs aie gaining in popuIaiity (and avaiI-
abiIity). The easiest way to contioI V
CC
is with a Logic
LeveI pFFT, as shown in Figuie 10a. This ciicuit aI-
Iows the fuII V
CC
to be used to tuin the device on.
UnfoitunateIy, powei pFFTs aie not economicaIIy
competitive with bipoIai tiansistois of compaiabIe iat-
ings.
Powei nFFTs aie both economicaI and avaiIabIe, and
can be used in this appIication if a DC suppIy of highei
voItage is avaiIabIe to diive the gate. Figuie 10b shows
how to impIement a V
CC
switch using a powei nFFT
and a (nominaIIy)
a
12V suppIy. The piobIem heie is
that if the device is on, its souice voItage is
a
5V. To
maintain the on state, the gate has to be anothei 5 oi
10V above that. The 12V suppIy is not paiticuIaiIy
ciiticaI. A minimaIIy fiIteied, unieguIated iectifiei wiII
suffice.
BATTERY BACKUP SYSTEMS
Heie we considei ciicuits that noimaIIy diaw powei
fiom the AC Iine, but switch to batteiy opeiation in the
event of a powei faiIuie. We assume that in batteiy
opeiation high-cuiient Ioads wiII be aIIowed to die
aIong with the AC powei. The system may continue
then with ieduced functionaIity, monitoiing a contioI
tiansducei, peihaps, oi diiving an LCD. Oi it may go
into a baie-bones suivivaI mode, in which ciiticaI data
is saved but nothing eIse happens tiII AC powei is ie-
stoied.
In any case it is necessaiy to have some eaiIy waining
of an impending powei faiIuie so that the system can
aiiange an oideiIy tiansfei to batteiy powei. FaiIy
waining systems can opeiate by monitoiing eithei the
AC Iine voItage oi the unieguIated iectifiei output, oi
even by monitoiing the ieguIated DC voItage.
Monitoiing the AC Iine voItage gives the eaiIiest wain-
ing. That way you can know within one oi two haIf-cy-
cIes of Iine fiequency that AC powei is down. In most
cases you then have at Ieast anothei haIf-cycIe of Iine
fiequency befoie the ieguIated V
CC
staits to faII. In a
haIf-cycIe of Iine fiequency an 80C51BH can execute
about 5,000 instiuctions-pIenty of time to aiiange an
oideiIy tiansfei of powei.
The ciicuit in Figuie 11 uses a Zenei diode to test the
Iine voItage each haIf-cycIe, and a junction tiansistoi to
pass the infoimation on to the 80C51BH. (ObviousIy a
voItage compaiatoi with a suitabIe iefeience souice can
9
AP-252
27006810
Figure 11 Power Failure Detector with Battery Backup When AC power fails
VCC1 goes down and VCC2 is held
peifoim the same function, if one piefeis.) The way it
woiks is if the Iine voItage ieaches an acceptabIy high
IeveI, it bieaks ovei Z1, diives Q1 to satuiation, and
inteiiupts the 80C51BH. The inteiiupt wouId be tian-
sition-activated, in this appIication. The inteiiupt seiv-
ice ioutine ieIoads one of the C51BHs timeis to a vaIue
that wiII make it ioII ovei in something between one
and two haIf-cycIes of Iine fiequency. As Iong as the
Iine voItage is heaIthy, the timei nevei ioIIs ovei, be-
cause it is ieIoaded eveiy haIf-cycIe. If theie is a singIe
haIf-cycIe in which the Iine voItage doesnt ieach a high
enough IeveI to geneiate the inteiiupt, the timei ioIIs
ovei and geneiates a timer inteiiupt.
The timei inteiiupt then commences the tiansition to
batteiy backup. CiiticaI data needs to be copied into
piotected RAM. SignaIs to ciicuits that aie going to
Iose powei must be wiitten to Iogic Iow. Piotected cii-
cuits (those poweied by V
CC
2) that communicate with
unpiotected ciicuits must be deseIected. The miciocon-
tioIIei itseIf may be put into IdIe, so that it can contin-
ue some IeveI of inteiiupt-diiven functionaIity, oi it
may be put into Powei Down.
Note that if the CPU is going to invoke Powei Down,
the SpeciaI Function Registeis may aIso need to be cop-
ied into piotected RAM, since the ieset that teiminates
the Powei Down mode wiII aIso intiaIize aII the SFRs
to theii ieset vaIues.
The ciicuit in Figuie 11 does not show a wake-up
mechanism. A numbei of choices aie avaiIabIe, howev-
ei. A pushbutton couId be used to geneiate an intei-
iupt, if the CPU is in IdIe, oi to activate ieset, if the
CPU is in Powei Down.
Automatic wake-up on powei iestoiation is aIso possi-
bIe. If the CPU is in IdIe, it can continue to iespond to
any inteiiupts that might be geneiated by Q1. The in-
teiiupt seivice ioutine deteimines fiom the status of
fIag bits OF0 and OF1 in PCON that it is in IdIe be-
cause theie was a powei outage. It can then sampIe
V
CC
1 thiough a voItage compaiatoi simiIai to Z1, Q1
in Figuie 11. A satisfactoiy IeveI of V
CC
1 wouId be
indicated by the tiansistoi being in satuiation.
But peihaps you cant spaie the timei that is the key to
the opeiation of the ciicuit in Figuie 11. In that case a
ietiiggeiabIe one-shot, tiiggeied by the AC Iine voItage,
can peifoim essentiaIIy the same function. Figuie 12
shows an exampIe of this type of powei faiIuie detectoi.
A ietiiggeiabIe one-shot (one haIf of a 74HC123) moni-
tois the AC Iine voItage thiough tiansistoi Q1. Q1 ie-
tiiggeis the one-shot eveiy haIf-cycIe of Iine fiequency.
If the output puIse width is between one and two haIf-
cycIes of Iine fiequency, then a singIe missing oi Iow
haIf-cycIe wiII geneiate an active Iow waining fIag,
which can be used to inteiiupt the miciocontioIIei.
The inteiiupt ioutine takes caie of the tiansition to
batteiy backup. Fiom this point V
CC
1 may oi may not
actuaIIy diop out. The missing haIf-cycIe of Iine voItage
that caused the powei down sequence may have been
nothing moie than a shoit gIitch. If the AC Iine comes
back stiong enough to tiiggei the one-shot whiIe V
CC
1
is stiII up (as indicated by the state of tiansistoi Q2),
then the othei haIf of the 74HC123 wiII geneiate a
wake-up signaI.
10
AP-252
27006811
Figure 12 Power Failure Detector uses retriggerable one-shots to flag impending power outage and
generate automatic wake-up when power returns
Having been awakened, the 80C51BH wiII stay awake
foi at Ieast anothei haIf-cycIe of Iine fiequency (anothei
5,000 oi so instiuctions) befoie possibIy being toId to
aiiange anothei tiansfei of powei. ConsequentIy, if the
Iine voItage is jitteiing eiiaticaIIy aiound the switch-
ovei point (deteimined by diode Z1), the system wiII
Iimp aIong executing in haIf-cycIe units of Iine fiequen-
cy.
On the othei hand, if the powei outage is ieaI and
Iengthy, V
CC
1 wiII eventuaIIy faII beIow the IeveI at
which the backup batteiy takes ovei. The backup bat-
teiy maintains powei to the 80C51BH, and to the
74HC123, and to whatevei othei ciicuits aie being pio-
tected duiing this outage. The batteiy voItage must be
high enough to maintain V
CC
MIN specs to the
80C51BH.
If the miciocontioIIei is an 80C31BH, executing out of
exteinaI ROM, and if the C31BH is put into IdIe dui-
ing the powei outage, then the exteinaI ROM must aIso
be suppIied by the batteiy. On the othei hand, if the
C31BH is put into Powei Down duiing the outage,
then the ROM can be aIIowed to die with the AC pow-
ei. The consideiations heie aie the same as in Figuie 9:
V
CC
to the ROM is stiII up at the time Powei Down is
invoked, and we must ensuie (thiough seIection of di-
ode Z2 in Figuie 12) that the 80C31BH is not awak-
ened tiII ROM powei is back in spec.
POWER SWITCHOVER CIRCUITS
Batteiy backup systems need to have a way foi the
piotected ciicuits to diaw powei fiom the Iine-opeiated
powei suppIy when that souice is avaiIabIe, and to
switch ovei to batteiy powei when iequiied. The
switchovei ciicuit is simpIe if the entiie system is to be
batteiy poweied in the event of a Iine powei outage. In
that case a paii of diodes suffice, as shown in Figuie 12,
piovided V
CC
MIN specs aie stiII met aftei the diode
diop has been subtiacted fiom its iespective powei
souice.
The situation becomes moie compIicated when pait of
the ciicuit is going to be aIIowed to die when the AC
powei goes out. In that case it is difficuIt to maintain
equaI V
CC
s to piotected and unpiotected ciicuits (and
possibIy dangeious not to).
The piobIem can be aIIeviated by using a Schottky di-
ode instead of a 1N4001, foi its Iowei foiwaid voItage
diop. The 1N5820, foi exampIe, has a fowaid diop of
about 0.35V at 1A.
Othei soIutions aie to use a tiansistoi oi powei MOS-
FFT switch, as shown in Figuie 13. With minoi modifi-
cations this switch can be contioIIed by poit pins.
11
AP-252
27006827
a Using a pnp Transistor
27006812
b Using a Power MOSFET
Figure 13 Power Switchover Ckts
80C31BH
a
CHMOS EPROM
The 27C64 and 87C64 aie InteIs 8K byte CHMOS
FPROMs. The 27C64 iequiies an exteinaI addiess
Iatch, and can be used with the 80C31BH as shown in
Figuie 14a. In most 8031
a
2764 (HMOS) appIi-
cations, the 2764s Chip FnabIe (CF) pin is haidwiied
to giound (since its noimaIIy the onIy piogiam memo-
iy on the bus). This can be done with the CHMOS
veisions as weII, but theie is some advantage in con-
necting CF to ALF, as shown in Figuie 14a. The ad-
vantage is that if the 80C31BH is put into IdIe mode,
since ALF goes to a 1 in that mode, the 27C64 wiII be
deseIected and go into a Iow cuiient standby mode.
The timing wavefoims foi this configuiation aie shown
in Figuie 14b. In Figuie 14b the signaIs and timing
paiameteis in paienthesis aie those of the 27C64, and
the otheis aie of the 80C31BH, except Tpiop is a pa-
iametei of the addiess Iatch. The iequiiements foi tim-
ing compatibiIity aie
TAVIV b Tprop
l
tACC
TLLIV
l
tCE
TPLIV
l
tOE
TPXIZ
l
tDF
If the appIication is going to use the Powei Down mode
then we have anothei consideiation: In IdIe, ALF
e
PSFN
e
1, and in Powei Down, ALF
e
PSFN
e
0.
In a ieaIistic appIication theie aie IikeIy to be moie
chips in the ciicuit than aie shown in Figuie 14, and it
is IikeIy that the nonessentiaI ones wiII have theii V
CC
iemoved whiIe the CPU is in Powei Down. In that case
the FPROM and the addiess Iatch shouId be among
the chips that have V
CC
iemoved, and Iogic Iows aie
exactIy what aie iequiied at ALF and PSFN.
But if V
CC
is going to be maintained to the FPROM
duiing Powei Down, then it wiII be necessaiy to de-
27006826
Figure 14a 80C31BH
a
27C64
12
AP-252
27006813
Figure 14b Timing Waveforms for 80C31BH
a
27C64
seIect the FPROM when the CPU is in Powei Down. If
IdIe is nevei invoked, CF of the FPROM can be con-
nected to P2.7 of the 80C31BH, as shown in Figuie
15a. In noimaI opeiation, P2.7 wiII be emitting the
MSB of the Piogiam Countei, which is 0 if the pio-
giam contains Iess than 32K of code. Then when the
CPU goes into Powei Down, the Poit 2 pins emit P2
SFR data, which puts a 1 at P2.7, thus deseIecting the
FPROM.
If IdIe and Powei Down aie both going to be used, CF
of the FPROM can be diiven by the IogicaI OR of ALF
and P2.7, as shown in Figuie 15b. In IdIe, ALF
e
1
wiII deseIect the FPROM, and in Powei Down, P2.7
e
1 wiII deseIect it.
27006814
a Power Down is used but not idle
27006815
b Idle and Power Down both used
Figure 15 Modifications to 80C31BH27C64
Interface
PuIIdown iesistois aie shown in Figuie 14a undei the
assumption that something on the bus is going to have
its V
CC
iemoved duiing Powei Down. If this is not the
case, puIIups can be used as weII as puIIdowns.
The 87C64 is Iike the 27C64 except that it has an on-
chip addiess Iatch. The Poit 0 pins aie tied to both
addiess and data pins of the 87C64, as shown in Figuie
16a. ALF diives the FPROMs ALF/CS input. Duiing
ALF high, the addiess infoimation is aIIowed to fIow
into the FPROM and begin accessing the code byte. On
the faIIing edge of ALF the addiess byte is inteinaIIy
Iatched. The A0A7 inputs aie then ignoied and the
same bus Iines aie used to tiansmit the fetched code
byte fiom the O0O7 pins back to the 80C31BH.
The timing wavefoims foi this configuiation aie shown
in Figuie 16b. In Figuie 16b the signaIs and timing
paiameteis in paientheses aie those of the 87C64, and
the otheis aie of the 80C31BH. The iequiiements foi
timing compatibiIity aie
TLHLL
l
tLL
TAVLL
l
tAL
TLLAX
l
tLA
TLLIV
l
tACL
TPLIV
l
tOE
TLLPL
l
tCOE
TPXIZ
l
tOHZ
The same consideiations appIy to the 87C64 as to the
27C64 with iegaids to the IdIe and Powei Down
modes. BasicaIIy you want CS
e
1 if V
CC
is main-
tained to the FPROM, and CS
e
OF
e
0 if V
CC
is
iemoved.
SCANNING A KEYBOARD
Theie aie many diffeient kinds of keyboaids, but aIpha-
numeiic keyboaids geneiaIIy consist of a matiix of 8
scan Iines and 8 ieceive Iines as shown in Figuie 17.
Fach set of Iines connects to one poit of the miciocon-
tioIIei. The softwaie has wiitten 0s to the scan Iines,
and 1s to the ieceive Iines. Piessing a key connects a
scan Iine to a ieceive Iine, thus puIIing the ieceive Iine
to a Iogic Iow.
The 8 ieceive Iines aie ANDed to one of the exteinaI
inteiiupt pins, so that puIIing any of the ieceive Iines
Iow geneiates an inteiiupt. The inteiiupt seivice iou-
tine has to identify the piessed key, if onIy one key is
down, and conveit that infoimation to some usefuI out-
put. If moie than one key in the Iine matiix is found to
be piessed, no action is taken. (This is a two key Iock-
out scheme.)
13
AP-252
On some keyboaids, ceitain keys (Shift, ContioI, Fs-
cape, etc.) aie not a pait of the Iine matiix. These keys
wouId connect diiectIy to a poit pin on the miciocon-
tioIIei, and wouId not cause Iock-out if piessed simuIta-
neousIy with a matiix key, noi geneiate an inteiiupt if
piessed singIy.
NoimaIIy the miciocontioIIei wouId be in idIe mode
when a key has not been piessed, and anothei task is
not in piogiess. Piessing a matiix key geneiates an in-
teiiupt, which teiminates the IdIe. The inteiiupt seiv-
ice ioutine wouId fiist caII a 30 ms (oi so) deIay to
debounce the key, and then set about the task of identi-
fying which key is down.
Fiist, the cuiient state of the ieceive Iines is Iatched
into an inteinaI iegistei. If a singIe key is down, aII but
one of the Iines wouId be iead as 1s. Then 0s aie wiitten
to the ieceive Iines and 1s to the scan Iines, and the scan
Iines aie iead. If a singIe key is down, aII but one of
27006816
Figure 16a 80C31BH
a
87C64
27006817
Figure 16b Timing Waveforms for 80C31BH
a
87C64
14
AP-252
these Iines wouId be iead as 1s. By Iocating the singIe 0
in each set of Iines, the piessed key can be identified. If
moie than one matiix key is down, one oi both sets of
Iines wiII contain muItipIe 0s.
A subioutine is used to deteimine which of 8 bits in
eithei set of Iines is 0, and whethei moie than one bit is
0. Figuie 18 shows a subioutine (SCAN) which does
that using the 8051s bit-addiessing capabiIity. To use
the subioutine, move the Iine data into a bit-addiess-
abIe RAM Iocation named LINF, and caII the SCAN
ioutine. The numbei of LINF bits which aie zeio is
ietuined in ZFRO
-
COUNTFR. If onIy one bit is
zeio, its numbei (1 thiough 8) is ietuined in ZFRO
-
BIT.
The inteiiupt seivice ioutine that is executed in ie-
sponse to a key cIosuie might then be as foIIows:
RE$F0R$E 10 KEY 0L0$URE:
0ALL IEB0UR0E IELAY
N07 LlRE,Fl_ _$ee Fiure l7.
0ALL $0AR
I5R7 7ER0 00UR1ER,RE5E01
N07 AIIRE$$,7ER0 Bl1
N07 F2,0FFH_ _$ee Fiure l7.
N07 Fl,0
N07 LlRE,F2
0ALL $0AR
I5R7 7ER0 00UR1ER,RE5E01
X0H A,7ER0 Bl1
$AF A
0RL AIIRE$$,A
X0H A,7ER0 Bl1
N07 Fl,0FFH
N07 F2,0
RE5E01: 0LR EX0
RE1l
27006818
Figure 17 Scanning a Keyboard
15
AP-252
27006819
Figure 18 Subroutine SCAN Determines Which of 8 Bits in LINE is Zero
Notice that RFSPONSF
-
TO
-
KFY
-
CLOSURF
does not change the AccumuIatoi, the PSW, noi any of
the iegisteis R0 thiough R7. Neithei do SCAN oi DF-
BOUNCF
-
DFLAY.
What we come out with then is a one-byte key addiess
(ADDRFSS) which identifies the piessed key. The
keys scan Iine numbei is in the uppei nibbIe of AD-
DRFSS, and its ieceive Iine numbei is in the Iowei
nibbIe. ADDRFSS can be used in a Iook-up tabIe to
geneiate a key code to tiansmit to a host computei,
and/oi to a dispIay device.
The keyboaid inteiiupt itseIf must be edge-tiiggeied,
iathei than IeveI-activated, so that the inteiiupt ioutine
is invoked when a key is piessed, and is not constantIy
being iepeated as Iong as the key is heId down. In edge-
tiiggeied mode, the on-chip haidwaie cIeais the intei-
iupt fIag (FX0, in this case) as the seivice ioutine is
being vectoied to. In this appIication, howevei, contact
bounce wiII cause seveiaI moie edges to occui aftei the
seivice ioutine has been vectoied to, duiing the DF-
BOUNCF
-
DFLAY ioutine. ConsequentIy it is neces-
saiy to cIeai FX0 again in softwaie befoie executing
RFTI.
The debounce deIay ioutine aIso takes advantage of the
IdIe mode. In this ioutine a timei must be pieIoaded
with a vaIue appiopiiate to the desiied Iength of deIay.
This wouId be
timer preload e
(osc kHz) c (delay time ms)
12
Foi exampIe, with a 3.58 MHz osciIIatoi fiequency, a
30 ms deIay couId be obtained using a pieIoad vaIue of
b
8950, oi DD0A, in hex digits.
In the debounce deIay ioutine (Figuie 19), the timei
inteiiupt is enabIed and set to a highei piioiity than the
keyboaid inteiiupt, because as we invoke IdIe, the key-
boaid inteiiupt is stiII in piogiess. An inteiiupt of
the same piioiity wiII not be acknowIedged, and wiII
not teiminate the IdIe mode. With the timei inteiiupt
set to piioiity 1, whiIe the keyboaid inteiiupt is a piioi-
ity 0, the timei inteiiupt, when it occuis, wiII be ac-
knowIedged and wiII wake up the CPU. The timei in-
teiiupt seivice ioutine does not itseIf have to do any-
thing. The seivice ioutine might be nothing moie than
a singIe RFTI instiuction. RFTI fiom the timei intei-
iupt seivice ioutine then ietuins execution to the de-
bounce deIay ioutine, which shuts down the timei and
ietuins execution to the keyboaid seivice ioutine.
DRIVING AN LCD
An LCD (Liquid CiystaI DispIay) consists of a back-
pIane and any numbei of segments oi dots which wiII
be used to foim the image being dispIayed. AppIying a
voItage (nominaIIy 4 oi 5V) between any segment and
the backpIane causes the segment to daiken. The onIy
catch is that the poIaiity of the appIied voItage has to
be peiiodicaIIy ieveised, oi eIse a chemicaI ieac-
16
AP-252
27006820
Figure 19 Subroutine DEBOUNCE

DELAY Puts the 80C51BH into Idle During the Delay Time
tion takes pIace in the LCD which causes deteiioiation
and eventuaI faiIuie of the Iiquid ciystaI.
To pievent this happening, the backpIane and aII the
segments aie diiven with an AC signaI, which is de-
iived fiom a iectanguIai voItage wavefoim. If a seg-
ment is to be off it is diiven by the same wavefoim as
the backpIane. Thus it is aIways at backpIane potentiaI.
If the segment is to be on it is diiven with a wave-
foim that is the inveise of the backpIane wavefoim.
Thus it has about 5V of peiiodicaIIy changing poIaiity
between it and the backpIane.
With a IittIe softwaie oveihead, the 80C51BH can pei-
foim this task without the need foi additionaI LCD
diiveis. The onIy diawback is that each LCD segment
uses up one poit pin, and the backpIane uses one moie.
If moie than, say, two 7-segment digits aie being diiv-
en, theie aient many poit pins Ieft foi othei tasks.
NeveitheIess, assuming a given appIication Ieaves
enough poit pins avaiIabIe to suppoit this task, the con-
sideiations foi diiving the LCD aie as foIIows.
Suppose, foi exampIe, it is a 2-digit dispIay with a deci-
maI point. One poit (TFNS
-
DIOIT) connects to the 7
segments of the tens digit pIus the backpIane. Anothei
poit (ONFS
-
DIOIT) connects to a decimaI point pIus
the 7 segments of the ones digit.
One of the 80C51BHs timeis is used to maik off haIf-
peiiods of the diive voItage wavefoim. The LCD diive
wavefoim shouId have a iep iate between 30 and 100
Hz, but its not veiy ciiticaI. A haIf-peiiod of 12 ms wiII
set the iep iate to about 42 Hz. The pieIoad/ieIoad
vaIue to get 12 ms to ioIIovei is the 2s compIement
negative of the osciIIatoi fiequency in kHz: if the osciI-
Iatoi fiequency is 3.58 MHz, the ieIoad vaIue is
b
3580, oi F204 in hex digits.
Now, the 80C51BH wouId noimaIIy be in IdIe, to con-
seive powei, duiing the time that the LCD and othei
tasks aie not iequiiing seivicing. When the timei ioIIs
ovei it geneiates an inteiiupt, which biings the
80C51BH out of IdIe. The seivice ioutine ieIoads the
timei (foi the next ioIIovei), and inveits the Iogic IeveIs
of aII the pins that aie connected to the LCD. It might
Iook Iike this:
L0I IRl7E lR1ERRUF1:
N07 1Ll,L0| 1 X1AL FRE@,
N07 1Hl,Hl0H| 1 X1AL FRE@,
XRL 1ER$ Il0l1,0FFH
XRL 0RE$ Il0l1,0FFH
RE1l
To update the dispIay, one wouId use a Iook-up tabIe to
geneiate the chaiacteis. In the tabIe, on segments aie
iepiesented as 1s, and off segments as 0s. The back-
pIane bit is iepiesented as a 0. The quantity to be dis-
pIayed is stoied in RAM as a BCD vaIue. The Iook-up
tabIe opeiates on the Iow nibbIe of the BCD vaIue, and
pioduces the bit pattein that is to be wiitten to eithei
the ones digit oi the tens digit. Befoie the new patteins
can be wiitten to the LCD, the LCD diive inteiiupt has
to be disabIed. That is to pievent a poIaiity ieveisaI
fiom taking pIace between the times the two digits aie
wiitten. An update subioutine is shown in Figuie 20.
USING AN LCD DRIVER
As was noted, diiving an LCD diiectIy with an
80C51BH uses a Iot of poit pins. LCD diiveis aie avaiI-
abIe in CMOS to inteiface an 80C51BH to a 4-digit
dispIay using onIy 7 of the C51BHs I/O pins. BasicaI-
Iy, the C51BH teIIs the LCD diivei what digit is to be
dispIayed (4 bits) and what position it is to be dispIayed
in (2 bits), and toggIes a Chip SeIect pin to teII the
diivei to Iatch this infoimation. The LCD diivei genei-
ates the dispIay chaiacteis (hex digits), and takes caie
of the poIaiity ieveisaIs using its own RC osciIIatoi to
geneiate the timing.
17
AP-252
Figuie 21a shows an 80C51BH woiking with an
ICM7211M to diive a 4-digit LCD, and the softwaie
that updates the dispIay.
One couId equaIIy weII send infoimation to the LCD
diivei ovei the bus. In that case, one wouId set up the
AccumuIatoi with the digit seIect and data input bits,
and execute a MOVX

R0,A instiuction. The LCD

diiveis chip seIect wouId be diiven by the CPUs WR
signaI. This is a IittIe easiei in softwaie than the diiect
bit manipuIation shown in Figuie 21a. Howevei, it uses
moie I/O pins, unIess theie is aIieady some exteinaI
memoiy invoIved. In that case, no extra pins aie used
up by adding the LCD diivei to the bus.
RESONANT TRANSDUCERS
AnaIog tiansduceis aie often used to conveit the vaIue
of a physicaI piopeity, such as tempeiatuie, piessuie,
etc., to an anaIog voItage. These kinds of tiansduceis
then iequiie an anaIog-to-digitaI conveitei to put the
measuiement into a foim that is compatibIe with a digi-
taI contioI system. Anothei kind of tiansducei is now
becoming avaiIabIe that encodes the vaIue of the physi-
caI piopeity into a signaI that can be diiectIy iead by a
digitaI contioI system. These devices aie caIIed ieso-
nant tiansduceis.
Resonant tiansduceis aie osciIIatois whose fiequency
depends in a known way on the physicaI piopeity being
measuied. These devices output a tiain of iectanguIai
puIses whose iepetition iate encodes the vaIue of the
quantity being measuied. The puIses can in most cases
be fed diiectIy into the 80C51BH, which then measuies
eithei the fiequency oi peiiod of the incoming signaI,
basing the measuiement on the accuiacy of its own
cIock osciIIatoi. The 80C51BH can even do this in its
sIeep, that is, in IdIe.
When the fiequency oi peiiod measuiement is compIet-
ed, the C51BH wakes itseIf up foi a veiy shoit time to
peifoim a sanity check on the measuiement and con-
veit it in softwaie to any scaIing of the measuied quan-
tity that may be desiied. The softwaie conveision can
incIude coiiections foi nonIineaiities in the tiansduc-
eis tiansfei function.
ResoIution is aIso contioIIed by softwaie, and can even
be dynamicaIIy vaiied to meet changing needs as a situ-
ation becomes moie ciiticaI. Foi exampIe, in a piocess
contioIIei you can inciease youi iesoIution (fine tune
the contioI, as it weie) as the piocess appioaches its
taiget.
The nominaI iefeience fiequency of the output signaI
fiom these devices is in the iange of 20 Hz to 500 kHz,
depending on the design. Tiansduceis aie avaiIabIe that
have a fuII scaIe fiequency shift 2 to 1. The tiansducei
opeiates fiom a suppIy voItage iange of 3V to 20V,
which means it can opeiate fiom the same suppIy voIt-
age as the 80C51BH. At 5V, the tiansducei diaws Iess
than 5 mA (Refeience 7). It can noimaIIy be connected
diiectIy to one of the C51BHs poit pins, as shown in
Figuie 22.
FREQUENCY MEASUREMENTS
Measuiing a fiequency means counting puIses foi a
known sampIe time. Two timei/counteis can be used,
one to maik off the sampIe time and one to count puIs-
es. If the fiequency being counted doesnt exceed 50
kHz oi so, one may equaIIy weII connect the tiansducei
signaI to one of the exteinaI inteiiupt pins, and count
puIses in softwaie. That fiees up one timei, with veiy
IittIe cost in CPU time.
The count that is diiectIy obtained is TxF, wheie T is
the sampIe time and F is the fiequency. The fuII scaIe
27006821
Figure 20 UPDATE

LCD Routine Writes Two Digits to an LCD

18
AP-252
iange is Tx(Fmax-Fmin). Foi n-bit iesoIution
1 LSB e
Tx(Fmax-Fmin)
2
n
Theiefoie the sampIe time iequiied foi n-bit iesoIution
is
T e
2
n
Fmax-Fmin
Foi exampIe, 8-bit iesoIution in the measuiement of a
fiequency that vaiies between 7 kHz and 9 kHz wouId
iequiie, accoiding to this foimuIa, a sampIe time of 128
ms. The maximum acceptabIe fiequency count wouId
be 128 ms
c
9 kHz
e
1152 counts. The minimum
wouId be 896 counts. Subtiacting 896 fiom each fie-
quency count (oi piesetting the fiequency countei to
b
896
e
0FC80H) wouId aIIow the fiequency to be
iepoited on a scaIe of 0 to FF in hex digits.
27006822
Figure 21a Using an LCD Driver
27006823
Figure 21b UPDATE

LCD Routine Writes 4 Digits to an LCD Driver

19
AP-252
27006824
Figure 22 Resonant Transducer Does Not
Require an AD Converter
To impIement the measuiement, one timei is used to
estabIish the sampIe time. The timei is pieset to a vaIue
that causes it to ioII ovei at the end of the sampIe time,
geneiating an inteiiupt and waking the CPU fiom its
IdIe mode. The iequiied pieset vaIue is the 2s compIe-
ment negative of the sampIe time measuied in machine
cycIes. The conveision fiom sampIe time to machine
cycIes is to muItipIy it by 1/12 the cIock fiequency. Foi
exampIe, if the cIock fiequency is 12 MHz, then a sam-
pIe time of 128 ms is
(128 ms) c (12000 kHz)12 e 128000 machine cycles
Then the iequiied pieset vaIue to cause the timei to ioII
ovei in 128 ms is
b128000 e FE0C00 in hex digits
Note that the pieset vaIue is 3 bytes wide wheieas the
timei is onIy 2 bytes wide. This means the timei must
be augmented in softwaie in the timei inteiiupt ioutine
to thiee bytes. The 80C51BH has a DJNZ instiuction
(deciement and jump if not zeio) that makes it easiei to
code the thiid timei byte to count down instead of up.
If the thiid timei byte counts down, its ieIoad vaIue is
the 2s compIement of what it wouId be foi an up-coun-
tei. Foi exampIe, if the 2s compIement of the sampIe
time is FF0C00, then the ieIoad vaIue foi the thiid
timei byte wouId be 02, instead of FF. The timei intei-
iupt ioutine might then be:
1lNER lR1ERRUF1 R0U1lRE:
IR57 1HlRI 1lNER BY1E,0U1
N07 1L0,0
N07 1H0,00H
N07 1HlRI 1lNERBY1E,2
N07 FRE@UER0Y,00UR1ER L0
_Freset 00UR1ER to 1398:
N07 00UR1ER L0,30H
N07 00UR1ER Hl,0F0H
0U1: RE1l
At this point the vaIue of the fiequency of the tiansduc-
ei signaI, measuied to 8 bit iesoIution, is contained in
FRFQUFNCY. Note that the timei can be ieIoaded on
the fIy. Note too that the timei can be ieIoaded on the
fIy. Note too that foi 8-bit iesoIution onIy the Iow byte
of the fiequency countei needs to be iead, since the
high byte is necessaiiIy 0. Howevei, one may want to
test the high byte to ensuie that it is zeio, as a sanity
check on the data. Both bytes, of couise must be ie-
Ioaded.
PERIOD MEASUREMENTS
Measuiing the peiiod of the tiansducei signaI means
measuiing the totaI eIapsed time ovei a known numbei,
N, of tiansducei puIses. The quantity that is diiectIy
measuied is NT, wheie T is the peiiod of the tiansduc-
ei signaI in machine cycles. The ieIationship between T
in machine cycIes and the tiansducei fiequency F in
aibitiaiy fiequency units is
T e
Fxtal
F
c (112)
wheie FxtaI is the 80C51BH cIock fiequency, in the
same units as F.
The fuII scaIe iange then is Nx (Tmax
b
Tmin). Foi
n-bit iesoIution.
1 LSB e
Ns(Tmax-Tmin)
2
n

Theiefoie the numbei of peiiods ovei which the eIapsed
time shouId be measuied is
N e
2
n
Tmax-Tmin
Howevei, N must aIso be an integei. It is IogicaI to
evaIuate the above foimuIa (dont foiget Tmax and
Tmin have to be in machine cycIes) and seIect foi N the
next highei integei. This seIection gives a peiiod mea-
suiement that has somewhat moie than n-bit iesoIu-
tion, but it can be scaIed back if desiied.
Foi exampIe, suppose we want 8-bit iesoIution in the
measuiement of the peiiod of a signaI whose fiequency
vaiies fiom 7.1 kHz to 9 kHz. If the cIock fiequency is
12 MHz, then Tmax is (12000 kHz/7.1 kHz) x (1/12)
e
141 machine cycIes. Tmin is 111 machine cycIes.
The iequiied vaIue foi N, then, is 256/(141-111)
e
8.53 peiiods, accoiding to the foimuIa. Using N
e
9
peiiods wiII give a maximum NT vaIue of 141 x 9
e
1269 machine cycIes. The minimum NT wiII be 111
c
9
e
999 machine cycIes. A Iookup tabIe can be used to
20
AP-252
scaIe these vaIues back to a iange of 0 to 255, giving
pieciseIy the 8-bit iesoIution desiied.
To impIement the measuiement, one timei is used to
measuie the eIapsed time, NT. The tiansducei is con-
nected to one of the exteinaI inteiiupt pins, and this
inteiiupt is configuied to the tiansition-activated mode.
In the tiansition-activated mode eveiy 1-to-0 tiansition
in the tiansducei output wiII geneiate an inteiiupt. The
inteiiupt ioutine counts tiansducei puIses, and when it
gets to the piedeteimined N, it ieads and cIeais the
timei. Foi the specific exampIe cited above, the intei-
iupt ioutine might be:
lR1ERRUF1 RE$F0R$E:
I5R7 R,0U1
N07 R,9
0LR EA
0LR 1Rl
N07 R1 L0,1Ll
N07 R1 Hl,1Hl
N07 1Ll,9
N07 1Hl,0
$E1B 1Rl
$E1B EA
0ALL L00KUF 1ABLE
0U1: RE1l
In this ioutine a puIse countei N is deciemented fiom
its pieset vaIue, 9, to zeio. When the countei gets to
zeio it is ieIoaded to 9. Then aII inteiiupts aie bIocked
foi a shoit time whiIe the timei is iead and cIeaied. The
timei is stopped duiing the iead and cIeai opeiations,
so cIeaiing it actuaIIy means piesetting it to 9, to
make up foi the 9 machine cycIes that aie missed whiIe
the timei is stopped.
The subioutine LOOKUP
-
TABLF is used to scaIe
the measuiement back to the desiied 8-bit iesoIution. It
can aIso incIude buiIt-in coiiections foi eiiois oi non-
Iineaiities in the tiansduceis tiansfei function.
The subioutine uses the MOVC A,

A
a
DPTR
instiuction to access the tabIe, which contains 270 en-
tiies commencing at the 16-bit addiess iefeiied to as
TABLF. The subioutine must compute the addiess of
the tabIe entiy that coiiesponds to the measuied vaIue
of NT. This addiess is
DPTR e TABL a NT b NTMIN
wheie NTMIN
e
999, in this specific exampIe.
L00KUF 1ABLE:
FU$H A00
FU$H F$
N07 A,L0|1ABLE-R1NlR,
AII A,R1 L0
N07 IFL,A
N07 A,Hl0H|1ABLE-RN1lR,
AII0 A,R1 Hl
N07 IFH,A
0LR A
N070 A,A0I1FR
N07 FERl0I,A
F0F F$
F0F A00
RE1
At this point the vaIue of the peiiod of the tiansducei
signaI, measuied to 8 bit iesoIution, is contained in PF-
RIOD.
PULSE WIDTH MEASUREMENTS
The 80C51BH timeis have an opeiating mode which is
paiticuIaiIy suited to puIse width measuiements, and
wiII be usefuI in these appIications if the tiansducei
signaI has a fixed duty cycIe.
In this mode the timei is tuined on by the on-chip
ciicuitiy in iesponse to an input high at the exteinaI
inteiiupt pin, and off by an input Iow, and it can do this
whiIe the 80C51BH is in IdIe. (The OATF mode of
timei opeiation is desciibed in the InteI MiciocontioI-
Iei Handbook.) The exteinaI inteiiupt itseIf can be en-
abIed, so the same 1-to-0 tiansition fiom the tiansducei
that tuins off the timei aIso geneiates an inteiiupt. The
inteiiupt ioutine then ieads and iesets the timei.
The advantage of this method is that the tiansducei
signaI has diiect access to the timei gate, with the iesuIt
that vaiiations in inteiiupt iesponse time have no effect
on the measuiement.
Resonant tiansduceis that aie designed to fuIIy expIoit
the OATF mode have an inteinaI divide-by-N ciicuit
that fixes the duty cycIe at 50% and Ioweis the output
fiequency to the iange of 250 to 500 Hz (to contioI
RFI). The tiansfei function between tiansducei peiiod
and measuiand is appioximateIy Iineai, with known
and iepeatabIe eiioi functions.
HMOSCHMOS Interchangeability
The CHMOS veision of the 8051 is aichitectuiaIIy
identicaI with the HMOS veision, but theie aie nevei-
theIess some impoitant diffeiences between them which
the designei shouId be awaie of. In addition, some ap-
pIications iequiie inteichangeabiIity between HMOS
and CHMOS paits. The diffeiences that need to be con-
sideied aie as foIIows:
External Clock Drive To diive the HMOS 8051 with
an exteinaI cIock signaI, one noimaIIy giounds the
XTAL1 pin and diives the XTAL2 pin. To diive the
CHMOS 8051 with an exteinaI cIock signaI, one must
diive the XTAL1 pin and Ieave the XTAL2 pin uncon-
nected. The ieason foi the diffeience is that in the
21
AP-252
HMOS 8051, it is the XTAL2 pin that diives the intei-
naI cIocking ciicuits, wheieas in the CHMOS veision it
is the XTAL1 pin that diives the inteinaI cIocking cii-
cuits.
Theie aie seveiaI ways to design an exteinaI cIock diive
to woik with both types. Foi Iow cIock fiequencies (be-
Iow 6 MHz), the HMOS 8051 can be diiven in the same
way as the CHMOS veision, nameIy, thiough XTAL1
with XTAL2 unconnected. Anothei way is to diive
both XTAL1 and XTAL2, that is, diive XTAL1 and
use and exteinaI inveitei to deiive fiom XTAL1 a sig-
naI with which to diive XTAL2.
In eithei case, a 74HC oi 74HCT ciicuit makes an ex-
ceIIent diivei foi XTAL1 and/oi XTAL2, because nei-
thei the HMOS noi the CHMOS XTAL pins have
TTL-Iike input Iogic IeveIs.
Unused Pins Unused pins of Poits 1, 2 and 3 can be
ignoied in both HMOS and CHMOS designs. The in-
teinaI puIIups wiII put them into a defined state. Un-
used Poit 0 pins in 8051 appIications can be ignoied,
even if theyie fIoating. But in 80C51BH appIications,
these pins shouId not be Ieft afIoat. They can be extei-
naIIy puIIed up oi down, oi they can be inteinaIIy
puIIed down by wiiting 0s to them.
8031/80C31BH designs may oi may not need puIIups
on Poit 0. PuIIups aient needed foi piogiam fetches,
because in bus opeiations the pins aie activeIy puIIed
high oi Iow by eithei the 8031 oi the exteinaI piogiam
memoiy. But they aie needed foi the CHMOS pait if
the IdIe oi Powei Down mode is invoked, because in
these modes Poit 0 fIoats.
Logic Levels If V
CC
is between 4.5V and 5.5V, an
input signaI that meets the HMOS 8051s input Iogic
IeveIs wiII aIso meet the CHMOS 80C51BHs input Iog-
ic IeveIs (except foi XTAL1/XTAL2 and RST). Foi
the same V
CC
condition, the CHMOS device wiII ieach
oi suipass the output Iogic IeveIs of the HMOS device.
The HMOS device wiII not necessaiiIy ieach the output
Iogic IeveIs of the CHMOS device. This is an impoitant
consideiation if HMOS/CHMOS inteichangeabiIity
must be maintained in an otheiwise CMOS system.
HMOS 8051 outputs that have inteinaI puIIups (Poits
1, 2, and 3) typicaIIy ieach 4V oi moie if I
OH
is zeio,
but not fast enough to meet timing specs. Adding an
exteinaI puIIup iesistoi wiII ensuie the Iogic IeveI, but
stiII not the timing, as shown in Figuie 23. If timing is
an issue, the best way to inteiface HMOS to CMOS is
thiough a 74HCT ciicuit.
Idle and Power Down The IdIe and Powei Down
modes exist onIy on the CHMOS devices, but if one
27006825
Figure 23 0-to-1 Transition Shows Unspecd
Delay (Dt) in HMOS to 74HC Logic
wishes to pieseive the capabiIity of inteichanging
HMOS and CHMOS 8051s the softwaie has to be de-
signed so that the HMOS paits wiII iespond in an ac-
ceptabIe mannei when a CHMOS ieduced powei mode
is invoked.
Foi exampIe, an instiuction that invokes Powei Down
can be foIIowed by a JMP $:
0LR EA
0RL F00R,2
5NF |
The CHMOS and HMOS paits wiII iespond to this
sequence of code diffeientIy. The CHMOS pait, going
into a noimaI CHMOS Powei Down Mode, wiII stop
fetching instiuctions untiI it gets a haidwaie ieset. The
HMOS pait wiII go thiough the motions of executing
the ORL instiuction, and then fetch the JMP instiuc-
tion. It wiII continue fetching and executing JMP $ un-
tiI haidwaie ieset.
Maintaining HMOS/CHMOS 8051 inteichangeabiIity
in iesponse to IdIe iequiies moie pIanning. The HMOS
pait wiII not iespond to the instiuction that puts the
CHMOS pait into IdIe, so that instiuction needs to be
foIIowed by a softwaie idIe. This wouId be an idIing
Ioop which wouId be teiminated by the same conditions
that wouId teiminate the CHMOSs haidwaie IdIe.
Then when the CHMOS device goes into IdIe, the
HMOS veision executes the idIing Ioop, untiI eithei a
haidwaie ieset oi an enabIed inteiiupt is ieceived. Now
if IdIe is teiminated by an inteiiupt, execution foi the
CHMOS device wiII pioceed aftei RFTI fiom the in-
stiuction foIIowing the one that invoked IdIe. The in-
stiuction foIIowing the one that invoked IdIe is the
idIing Ioop that was inseited foi the HMOS device. At
this point, both the HMOS and CHMOS devices must
be abIe to faII thiough the Ioop to continue execution.
22
AP-252
One way to achieve the desiied effect is to define a
fake IdIe fIag, and set it just befoie going into IdIe.
The instiuction that invoked IdIe is foIIowed by a soft-
waie idIe:
$E1B lILE
0RL F00R,l
5B lILE,|
Now the inteiiupt that teiminates the CHMOSs IdIe
must aIso bieak the softwaie idIe. It does so by cIeaiing
the IdIe bit:
...
0LR lILE
RE1l
Note too that the PCON iegistei in the HMOS 8051
contains onIy one bit, SMOD, wheieas the PCON ieg-
istei in CHMOS contains SMOD pIus foui othei bits.
Two of those othei bits aie geneiaI puipose fIags. Main-
taining HMOS/CHMOS inteichangeabiIity iequiies
that these fIags not be used.
REFERENCES
1. PawIowski, Moioyan, AInethei, Inside CMOS
TechnoIogy, BYTE magazine Sept., 1983. AvaiI-
abIe as AiticIe Repiint AR-302.
2. Kokkonen, PashIey, ModuIai Appioach to C-MOS
TechnoIogy TaiIois Piocess to AppIication, Elec-
tronics, May, 1984. AvaiIabIe as AiticIe Repiint
AR-332.
3. WiIIiamson, T., Designing Microcontroller Systems
for Electrically Noisy Environments InteI AppIica-
tion Note AP-125, Feb. 1982.
4. WiIIiamson, T., PC Layout Techniques foi Mini-
mizing Noise, Mini-Micro Southeast Session 9,
Jan., 1984.
5. AInethei, J., High Speed Memory System Design Us-
ing 2147H Intel Application Note AP-74 March
1980
6. Ott, H., DigitaI Ciicuit Oiounding and Inteicon-
nection, Proceedings of the IEEE Symposium on
Electromagnetic Compatibility pp. 292297, Aug.
1981.
7. Digital Sensors by Technar Technai Inc., 205 Noith
2nd Ave., Aicadia, CA 91006.
23
INTEL CORPORATION 2200 Mission College Blvd Santa Clara CA 95052 Tel (408) 765-8080
INTEL CORPORATION (UK) Ltd Swindon United Kingdom Tel (0793) 696 000
INTEL JAPAN kk Ibaraki-ken Tel 029747-8511
Printed in USAxxxx0296B10Mxx xx