74HC245 Octal 3State Noninverting Bus Transceiver

HighPerformance SiliconGate CMOS

The 74HC245 is identical in pinout to the LS245. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC245 is a 3state noninverting transceiver that is used for 2way asynchronous communication between data buses. The device has an activelow Output Enable pin, which is used to place the I/O ports into highimpedance states. The Direction control determines whether data flows from A to B or from B to A.
Features http://onsemi.com MARKING DIAGRAMS
20 20 1 TSSOP20 DT SUFFIX CASE 948E 1 HC 245 ALYW G G

Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 308 FETs or 77 Equivalent Gates This is a PbFree Device

HC245 A L Y W G

= Device Code = Assembly Location = Wafer Lot = Year = Work Week = PbFree Package

(Note: Microdot may be in either location)

ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

Semiconductor Components Industries, LLC, 2007

March, 2007 Rev. 1

Publication Order Number: 74HC245/D

74HC245
DIRECTION A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OUTPUT ENABLE B1 B2 B3 B4 B5 B6 B7 B8 DIRECTION OUTPUT ENABLE A DATA PORT A1 A2 A3 A4 A5 A6 A7 A8 2 3 4 5 6 7 8 9 1 19 PIN 10 = GND PIN 20 = VCC 18 17 16 15 14 13 12 11 B1 B2 B3 B4 B5 B6 B7 B8 B DATA PORT

Figure 1. Pin Assignment

Figure 2. Logic Diagram

FUNCTION TABLE
Control Inputs Output Enable L L H X = dont care Direction L H X Operation Data Transmitted from Bus B to Bus A Data Transmitted from Bus A to Bus B Buses Isolated (HighImpedance State)

ORDERING INFORMATION
Device 74HC245DTR2G Package TSSOP20* Shipping 2500 / Tape & Reel

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently PbFree.

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74HC245
MAXIMUM RATINGS (Note 1)
Symbol VCC VIN VOUT IIK IOK IOUT ICC IGND TSTG TL TJ qJA PD MSL FR VESD ILATCHUP DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance Power Dissipation in Still Air at 85_C Moisture Sensitivity Flammability Rating ESD Withstand Voltage Latchup Performance Oxygen Index: 30% to 35% Human Body Model (Note 3) Machine Model (Note 4) Above VCC and Below GND at 85_C (Note 5) TSSOP TSSOP (Note 2) Parameter Value *0.5 to )7.0 *0.5 to VCC )0.5 *0.5 to VCC )0.5 $20 $35 $35 $75 $75 *65 to )150 260 )150 128 450 Level 1 UL 94 V0 @ 0.125 in u2000 u200 $300 V mA Unit V V V mA mA mA mA mA _C _C _C _C/W mW

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Measured with minimum pad spacing on an FR4 board, using 10 mmby1 inch, 20 ounce copper trace with no air flow. 2. IO absolute maximum rating must observed. 3. Tested to EIA/JESD22A114A. 4. Tested to EIA/JESD22A115A. 5. Tested to EIA/JESD78.

RECOMMENDED OPERATING CONDITIONS

Symbol VCC Vin, Vout TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 3) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min 2.0 0 55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V _C ns

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74HC245
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit Symbol VIH Parameter Minimum HighLevel Input Voltage Test Conditions Vout = VCC 0.1 V |Iout| v 20 mA Vout = 0.1 V |Iout| v 20 mA Vin = VIH |Iout| v 20 mA Vin = VIH |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA VOL Maximum LowLevel Output Voltage Vin = VIL |Iout| v 20 mA Vin = VIL |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA Iin IOZ ICC Maximum Input Leakage Current Maximum ThreeState Leakage Current Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Output in HighImpedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 mA VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 6.0 6.0 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.48 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.26 0.1 0.5 v 85_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.34 3.84 5.34 0.1 0.1 0.1 0.33 0.33 0.33 1.0 5.0 v 125_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.2 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.4 1.0 10 mA mA V Unit V

VIL

Maximum LowLevel Input Voltage

VOH

Minimum HighLevel Output Voltage

6.0

4.0

40

40

mA

6. Information on typical parametric values and high frequency or heavy load considerations can be found in the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit Symbol tPLH, tPHL tPLZ, tPHZ tPZL, tPZH tTLH, tTHL Cin Cout Maximum Propagation Delay, A to B, B to A (Figures 1 and 3) Maximum Propagation Delay, Direction or Output Enable to A or B (Figures 2 and 4) Maximum Propagation Delay, Output Enable to A or B (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 3) Maximum Input Capacitance (Pin 1 or Pin 19) Maximum ThreeState I/O Capacitance (I/O in HighImpedance State) Parameter VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 55 to 25_C 75 55 15 13 110 90 22 19 110 90 22 19 60 23 12 10 10 15 v 85_C 95 70 19 16 140 110 28 24 140 110 28 24 75 27 15 13 10 15 v 125_C 110 80 22 19 165 130 33 28 165 130 33 28 90 32 18 15 10 15 Unit ns

ns

ns

ns

pF pF

7. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor HighSpeed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 40 CPD Power Dissipation Capacitance (Per Transceiver Channel) (Note 8) pF 8. Used to determine the noload dynamic power consumption: P D = CPD VCC2 f + ICC VCC . For load considerations, see the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).

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74HC245

DIRECTION tr INPUT A OR B tPLH OUTPUT B OR A 90% 50% 10% 90% 50% 10% tTLH tPHL tf VCC GND

50%

VCC GND VCC

OUTPUT ENABLE

50% tPZL 50% tPZH tPHZ tPLZ 10% 90%

GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE

A OR B tTHL

A OR B

50%

Figure 3. Switching Waveform

Figure 4. Switching Waveform

TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST

TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.

CL*

*Includes all probe and jig capacitance

*Includes all probe and jig capacitance

Figure 5. Test Circuit

Figure 6. Test Circuit

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74HC245

A1

2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 B8 B7 B6 B5 B4 B DATA PORT B3 B2 B1

A2

A3

A4 A DATA PORT

A5

A6

A7

A8

DIRECTION

OUTPUT ENABLE

19

Figure 7. Expanded Logic Diagram

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74HC245
PACKAGE DIMENSIONS
TSSOP20 CASE 948E02 ISSUE C

20X

K REF
M

2X

L/2

20

11

J J1 B U N

PIN 1 IDENT 1 10

0.15 (0.006) T U

A V

N F DETAIL E W
DIM A B C D F G H J J1 K K1 L M

C D 0.100 (0.004) T SEATING

PLANE

DETAIL E

SOLDERING FOOTPRINT*
7.06 1

0.36

16X

16X

1.26

*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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SECTION NN 0.25 (0.010) M

0.15 (0.006) T U

0.10 (0.004)

T U

K K1

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_

0.65 PITCH

DIMENSIONS: MILLIMETERS

74HC245

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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74HC245/D