SRI BALAJI DURAI

2200 Waterview Pkwy, #1923 Richardson, TX - 75080 USA (214) 326-1771 sribalajid@live.com

SUMMARY
Seeking entry-level position as an electrical engineer. Proven skills in Digital Design, RTL coding, Simulation, Functional Verification, Synthesis, Pre-silicon & Post Silicon Validation, Static timing analysis for System On chip Designs. Worked on Schematic, Layout, DRC, LVS, Routing, Placement and Timing analysis. Strong knowledge of High Speed and Low power ASIC design, CMOS Circuit Design, Computer Architecture. Hands on Experience with DFT methodologies which include BIST, Scan Logic, ATPG and JTAG. Hands on experience in using Design/simulation tools like Cadence, Synopsys, Xilinx ISE, Spice, Modelsim. Good command over programming/HDL/HVL/Scripting languages such as C, C++/Verilog/System Verilog/PERL, TCL.

EDUCATION
Master of Science in Electrical Engineering University of Texas at Dallas, Richardson, Texas, USA Bachelor of Engineering in Electronics and Communication Engineering Anna University, Chennai, INDIA GPA: 3.29/4.0 Dec. 2012 GPA: 3.55/4.0 Apr. 2010

SKILLS
Hardware Description/Verification Languages : Verilog/System Verilog Programming/Scripting Languages : C, C++, Perl, TCL, 8085/8086 Assembly Language Cadence Tools : ICFB Virtuoso, Schematic, Layout Editor, SOC Encounter Synopsys Tools : PrimeTime, Design Compiler, TetraMAX Simulation Tools : ModelSim, XilinX ISE Design suite, HSPICE, MATLAB Operating System : Unix/Linux, Windows, Solaris, Mac

ACADEMIC PROJECTS
AVLSI design - Design of 512-bit SRAM IBM 90nm [Cadence, HSPICE, Primetime, Cosmoscope] Designed a memory cell, row decoder, column decoder, sense amplifier, write driver using 90nm. Optimized the design for Area, Aspect Ratio, Write Time, read time and timing reports were generated. ASIC design - Mini Stereo Digital Audio Processor IBM 130nm [Verilog, Cadence, Encounter] Designed FSM for a low power Digital Signal Processing audio application used in hearing aid. Computed simulation, FSM synthesis, timing analysis and placement & routing. Computer Architecture - Cache Design and Optimization of an Alpha Microprocessor [Simplescalar, Perl] Designed a cache hierarchy and compared the CPI and cost function for different benchmarks. Optimized Cache size, Block size, Split/Unified Cache, Associativity and Block Replacement policy. Computer Architecture - Performance of Several Branch Predictors [Simplescalar, Python] Explored branch predictors, RAS Configurations and compared the CPI and cost function. Compared the performance of the branch target buffer to the overall performance. Testing of Digital circuits [Verilog, Synopsys Design Vision, Tetramax] Tested various combinational and sequential logic circuits and synthesized those using Synopsys. ATPG was implemented on these circuits to generate test patterns and to detect various faults.

SRI BALAJI DURAI

VLSI design - Design of BCD Carry Look-ahead Adder IBM 130nm [Verilog, Cadence, HSPICE] Designed a High Speed BCD Adder Circuit with lowest EDP. Evaluated Area, power, energy, delay, EDP and timing reports were generated. Design of a 32-bit word Error Correction Code (ECC) [Cadence, HSPICE, Cosmoscope] Designed a 32-bit word ECC which will enable the correction of any single-bit error automatically. Detection and correction of any single bit error were done using Hamming Codes algorithm. Buffering a 20mm Long Wire [Cadence, HSPICE, Primetime, Cosmoscope] Buffered a 20mm long wire and calculated delay between input and output buffer. Equally spaced buffers and inverters were added separately and calculated their delay. Noise Margin of a Dynamic Inverter [Cadence, HSPICE, Primetime, Cosmoscope] Designed a dynamic inverter in schematic level with and without half-keeper circuit. Compared the Noise Margin between both the circuits. Vth Range of a Static CMOS Inverter [Cadence, HSPICE, Primetime, Cosmoscope] Designed a static CMOS Inverter in schematic level and netlist was extracted. Vth values were swept by changing the ratio of Wp/Wn in Hspice code. UWB Radar for detection of humans trapped under building debris [AWR, Virtual systems simulator] Designed a system to detect and locate human beings trapped in building debris like earthquake. Ultra Wide Band RF Transceiver was utilized in this project which provided best results. Vehicle Information and monitoring system Using GSM Modem [VB, Microcontroller simulator] Designed a working model which can collect data of a speeding vehicle and send it to a base station. The vehicle can be controlled from base stations in emergency situations. Wireless Sensor Networks - Design of a Sensor Mote Designed various components used in sensor node. Presented a sensor node used in biomedical application. Advanced applications of wireless sensor networks E39 Technology Presented the design of a biomedical strap used in a soccer ball game. Zigbee protocol was used as it supports large number of nodes considering players as nodes.

COURSE WORK
VLSI Design Advanced VLSI Design Advanced Computer Architecture Advanced Digital Logic ASIC Design Testing and Testable Design Analog IC Design Microprocessor Systems Low Power VLSI Circuits Design Automation of VLSI System Digital Integrated Circuits Digital Circuits and Systems

ACTIVITIES
Attended seminar on Open Verification Methodology conducted by Mentor graphics.