| Embedded |VLSI |DIP |Power Electronics | |Power Systems |JAVA | Dot Net |

VLSI
Front End Digital Design
Code DRZV 001 DRZV 002 DRZV 003 DRZV 004 DRZV 005 Title High Speed Modified Booth Encoder Multiplier for Signed and Unsigned Numbers Low-Power and Area-Efficient Carry Select Adder
IEEE 2012 Digital Design/ASIC

Domain

High speed and area efficient vedic multiplier On Modulo 2^n+1 Adder Design Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits VLSI Based Robust Router Architecture Addition of BCD digits using non-standard codes Design and implementation of low power FFT/IFFT processor for wireless communication An Asynchronous Floating-Point Multiplier Design of Modified Low Power Booth Multiplier FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial Using VHDL Low Complexity Design of Ripple Carry and BrentKung Adders in QCA High-Speed Low-Power Viterbi Decoder Design for TCM decoders Design of 32-Point FFT Using Radix-2 Algorithm for FPGA Synthesis and Implementation of UART Using VHDL Codes Low Power Efficient Built in Self Test Hardware Efficiency Comparison of AES Implementations Design of Low Power TPG Using LP-LFSR

DRZV 006 DRZV 007 DRZV 008 DRZV 009 DRZV 010 DRZV 011 DRZV 012 DRZV 013 DRZV 014 DRZV 015 DRZV 016 DRZV 017 DRZV 018 DRZV 019

IEEE 2012 Processers /ASIC/DFT/Communications

Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers - architecture description

IEEE 2012 Protocols/Co mmunication s

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| Embedded |VLSI |DIP |Power Electronics | |Power Systems |JAVA | Dot Net | DRZV 020 DRZV 021 DRZV 022 DRZV 023 DRZV 024 DRZV 025 A Novel Architecture for VLSI Implementation of RSA CORDIC Designs for Fixed Angle of Rotation Highly secured high throughput VLSI architecture for AES algorithm
IEEE 2011-2012 Protocols/Communications /Digital Design IEEE 2012

Towards to SHA-3 Hashing Standard for Secure Communications: On the Hardware Evaluation Development High Speed Parallel Decimal Multiplication with Redundant Internal Encodings System on Chip Design Using ISCAS Benchmark Circuits-An approach to Fault Injection and Simulation Based On Verilog HDL Implementation of Power Efficient Vedic Multiplier Implementation of Convolution Encoder and Viterbi Decoder using Verilog Design and Characterization of Parallel Prefix Adders using FPGAs A Review on Power optimization of Linear Feedback Shift Register (LFSR) for Low Power Built In Self Test (BIST) VHDL Implementation Of BIST Controller Design and Implementation of area-optimized AES based on FPGA Design Of Low Power And High Speed Configurable Booth Multiplier High Speed ASIC Design Of Complex Multiplier Using Vedic Mathematics Design and Verification of Four Port Router for NoC A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes An Efficient Implementation Of Floating Point Multiplier A New Reversible Design of BCD Adder

DRZV 026 DRZV 027 DRZV 028 DRZV 029 DRZV 030 DRZV 031 DRZV 032 DRZV 033 DRZV 034 DRZV 035 DRZV 036 DRZV 037 DRZV 038 DRZV 039 DRZV 040 DRZV 041

IEEE 2011- 2012 Processers /ASIC/DFT/Communications IEEE 2011-12 Protocols/Digital Design

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient Systemon-Chip Communications Image Encryption Based On AES Key Expansion AMBA-AXI Protocol Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance

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| Embedded |VLSI |DIP |Power Electronics | |Power Systems |JAVA | Dot Net | DRZV 042 DRZV 043 DRZV 044 DRZV 045 DRZV 046 DRZV 047 DRZV 048 DRZV 049 DRZV 050 DRZV 051 DRZV 052 DRZV 053 DRZV 054 New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter Power Estimation of Embedded Multiplier Blocks in FPGAs Design of Pipelined FFT Processor Based on FPGA Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing A New VLSI Architecture of Parallel MultiplierAccumulator Based on Radix-2 Modified Booth Algorithm Implementation of an On-chip Interconnect Using the i-SLIP Scheduling Algorithm A High Performance Binary To BCD Converter For Decimal Multiplication FPGA Implementations of the Hummingbird Cryptographic Algorithm Design and Implement of the Embedded Elevator Monitor System based on Wireless Communication Performance Evaluation of DES and Blowfish Algorithms A High-Speed 32-Bit Signed/Unsigned Pipelined Multiplier Improvisation Of Gabor Filter Design Using Verilog HDL Multiplexer based bit parallel Systolic Multiplier over GF (2m)
IEEE 2011 Digital Design /Cryptography IEEE 2011 Digital Design /Communications/ASIC/Proc essers Architectures

VLSI Image Processing /FPGA

DRZV 055 DRZV 056 DRZV 057 DRZV 058 DRZV 059 DRZV 060 A Novel Architecture for an Efficient Implementation of Image Compression Using 2D-DWT Median filter on FPGAs Background subtraction algorithm for moving object detection Implementation of moving object tracking using EDK Real time hardware co-simulation of Edge Detection for video processing system A Co-Design Methodology for Processor-centric embedded systems with Hardware Acceleration using FPGA
IEEE 2012 Image Processing(SOC)

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| Embedded |VLSI |DIP |Power Electronics | |Power Systems |JAVA | Dot Net | DRZV 061 DRZV 062 DRZV 063 DRZV 064 DRZV 065 DRZV 066 DRZV 067 DRZV 068 DRZV 069 DRZV 070 DRZV 071 DRZV 072 DRZV 073 DRZV 074 DRZV 075 DRZV 076 DRZV 077 DRZV 078 DRZV 079 A Level Set Based Deformable Model for Segmenting Tumors in Medical Images Adaptive Steg analysis of Least Significant Bit Replacement in Grayscale Natural Images A Simultaneous Implementation of Message Encoding using LSB Stenography & Image Compression using Lifting Scheme on FPGA Hardware Architecture for a Message Hiding Algorithm with Novel Randomizers A New Adaptive Weight Algorithm for Salt and Pepper Noise Removal Design and FPGA Implementation of Modified Distributive Arithmetic Based DWT IDWT Processor for Image Compression Pipelined Architecture for FPGA Implementation of Lifting-Based DWT An FPGA-based Architecture for Linear and Morphological Image Filtering Removal of High Density Salt and Pepper Noise Through Modified Decision Based Un symmetric Trimmed Median Filter Motion human detection based on background subtraction Parameterized FPGA-Based Architecture For Parallel 1-D Filtering Algorithms Hardware Implementation of DWT for Image Compression Using SPIHT Algorithm VLSI Implementation of Image Segmentation with Resource Optimized Adaptive Median Filter Motion human detection based on background subtraction Flexible Hardware Architecture of Hierarchical K-Means Clustering for Large Cluster Number Image Edge Detection Based on FPGA Optimization of Processor Architecture for Image Edge Detection Filter Efficient Hardware Architecture for Multimedia Encryption High-Speed FPGA Implementation for DWT of Lifting Scheme
IEEE 2011-2012 Image Processing(SOC)/FPGA Applications IEEE 2011-2012 /FPGA Applications IEEE 2012 Image Processing(SOC)

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| Embedded |VLSI |DIP |Power Electronics | |Power Systems |JAVA | Dot Net | DRZV 080 Hardware Description of Multi-Directional Fast Sobel Processor by VHDL for Implementing on FPGA Edge Detection
IEEE 2011

DRZV 081

Hardware Software Co-Simulation Of Motion Estimation In H.264 Encoder

Communications-SoC Architectures
DRZV 082 DRZV 083 BPSK system on Spartan 3E FPGA. Simulink Modeling and Design of an Efficient Hardware-constrained FPGAbased PMSM Speed Controller A highly secure cryptosystem for image encryption Gesture recognition using field programmable gate arrays. Intelligent human-machine interface using hand gestures recognition Real time hardware co-simulation of Edge Detection for video processing system Hardware Software co-simulation for Image Processing Applications Simulation of Switched Reluctance Motor for Performance Analysis Using MATLAB/SIMULINK Environment and use of FPGA for its control Comparison of different realization techniques of IIR filters using system generator FPGA Implementation of Low Complexity VLSI CDMA Communication System Architecture for DSIEEE 2012 DSP Architectures /FPGA Applications

DRZV 084 DRZV 085 DRZV 086 DRZV 087

DRZV 088 DRZV 089 DRZV 090 DRZV 091 DRZV 092 DRZV 093 DRZV 094 DRZV 095 DRZV 096 DRZV 097

IEEE 2012 /FPGA Applications/System Generator IEEE 2011-2012 DSP Architectures /FPGA Applications/System Generator

Real-time implementation of UWB-OFDM synthetic aperture radar imaging. MATLAB/simulink applications for SAR system design with FPGA. Modeling and simulation of a DC motor control system with digital PID controller and encoder in FPGA using Xilinx system generator System on chip implementation of 1-D wavelet transform based de noising of fiber optic gyroscope signal on FPGA Simulation and implementation of a BPSK modulator on FPGA QPSK Modulator on FPGA

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| Embedded |VLSI |DIP |Power Electronics | |Power Systems |JAVA | Dot Net | DRZV 098 DRZV 099 DRZV 100 DRZV 101 DRZV 102 DRZV 103 Model-based software-defined radio(SDR) design using FPGA A new method for FPGA development Design of Pipelined FFT Processor Based on FPGA FPGA Based Non Uniform Illumination Correction in Image Processing Applications SysGen Architecture for Visual Information Hiding Framework Performance efficient FPGA implementation of parallel 2-D MRI image filtering algorithms using Xilinx system generator Simulation and Analysis of Passive Wireless TPMS Digital Down Converter Based on System Generator. QMF implementation using Xilinx SysGen (XSG) An FPGA Implementation of the Time Domain Deadbeat Algorithm for Control Applications Efficient Design and FPGA Implementation of Digital Controller Using Xilinx SysGen Automatic Detection of Diabetic Retinopathy in Non dilated RGB Retinal Fundus Images
IEEE 2011-2012 PGA /System Generator IEEE 2011 DSP Architectures /FPGA Applications/System Generator

DRZV 104

DRZV 105 DRZV 106

DRZV 107

DRZV 108

Low Power Design

DRZV 109 DRZV 110 DRZV 111 DRZV 112 DRZV 113 DRZV 114 DRZV 115 Enhanced power gating schemes for low leakage low ground bounce noise in deep submicron circuits Single phase clocked quasi static adiabatic tree adder Interconnect Design for Sub threshold Circuits Implementation Of Low Power High Performance Combinational Circuits Using Output Prediction Logic Design of Low Voltage Low Power Operational Amplifier Reactivation Noise Suppression with Sleep Signal Slew Rate Modulation in MTCMOS Circuits Low-Power Pulse-Triggered Flip-Flop Design With Conditional PulseEnhancement Scheme
IEEE 2012 LOWPOWER /CMOS Design Analysis

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| Embedded |VLSI |DIP |Power Electronics | |Power Systems |JAVA | Dot Net | DRZV 116 DRZV 117 DRZV 118 DRZV 119 DRZV 120 DRZV 121 DRZV 122 DRZV 123 DRZV 124 DRZV 125 DRZV 126 DRZV 127 DRZV 128 DRZV 129 DRZV 130 DRZV 131 DRZV 132 DRZV 133 DRZV 134 DRZV 135 Implementation of full adder cells using NP-CMOS and Multi-Output logic styles in 90nm technology Design and Analysis of Low Power Full Adder Using Adiabatic Technique Four Bit CMOS Full adder in Submicron Technology with Low leakage and Ground bounce Noise Reduction Adiabatic Technique for Energy Efficient Logic Circuits Design
IEEE 2011 -12 LOWPOWER/Ultra Low Power/Layouts IEEE 2012 /CMOS Digital Design

Design of Sequential Elements for Low Power Clocking System Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design A 11-Transistor Nano scale CMOS Memory Cell for Hardening to Soft Errors Low Power Sub threshold D Flip Flop Analysis of Power Gating designs in Low Power VLSI Circuits Area Optimized Low Power Arithmetic And Logic Unit Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting Design of new full adder cell using hybrid-CMOS logic style A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design Design analysis of XOR (4T) based low voltage CMOS full adder circuit A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip Flops With Embedded Logic Ground Bounce Noise Reduction of Low leakage 1-bit Nano-CMOS based Full Adder Cells for Mobile Applications Design of A Low Power Flip-Flop Using CMOS Deep Submicron Technology Dual Stack Method: A Novel Approach to Low Leakage and Speed Power Product VLSI Design A Wide-Range All-Digital Delay-Locked Loop in 65nm CMOS Technology

IEEE 2011 -12 Ultra Low Power/Memories/Digital Design IEEE 2011 CMOS Design /Processer Applications

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| Embedded |VLSI |DIP |Power Electronics | |Power Systems |JAVA | Dot Net | DRZV 136 DRZV 137 DRZV 138 DRZV 139 A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nano scale VLSI Systems Optimal Design For Ground Bounce Noise Reduction Using Sleep Transistor CMOS Full-Adders for Energy-Efficient Arithmetic Applications 6 BIT Flash ADC
IEEE 2011 Ultra Low Power Digital Design

Embedded Applications/Analog VLSI

DRZV 140 DRZV 141 DRZV 142 DRZV 143 DRZV 144 Operation Improvement of Indoor Robot by Gesture Recognition Improving ATM Security Via Face Recognition Real Time Smart Car Lock Security System Using Face Detection and Recognition Driving Analog Mixed Signal Verification through Verilog-AMS Generate sine and Ramp waves by using Verilog AMS
IEEE 2012 Security/3AN FPGA IEEE 2012 Analog VLSI

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