A Low-Power Scan-Path Architecture

S. Hatami1, M. Alisafaee2, E. Atoofian2, Z. Navabi2 and A. Afzali-Kusha1 1 Low-Power High-Performance Nanosystems Laboratory 2 Computer Aided Design Laboratory ECE Department, University of Tehran Tehran, Iran alisafaee@cad.ece.ut.ac.ir, {s.hatami, e.atoofian}@ece.ut.ac.ir, navabi@ece.neu.edu, afzali@ut.ac.ir
Abstract In this paper, we propose a scan cell architecture that decreases power consumption and the total consumed energy. In the method which is based on the data compression, the test vector set is divided into two repeated and unrepeated partitions. The repeated part, which is common among some of the vectors, is not changed during the new scan path where new test vector will be filled. This way, every time that a new test vector is applied to the circuit, only the cells of the scan-path which are not repeated are altered and other cells retain their values. As a result, the test vector is applied to the circuit under test in a fewer number of clock cycles. In addition, the values of some scan cells remain unchanged leading to a lower switching activity in the scan-path during test mode. Besides, by latching the inputs of circuit under test, the proposed scan chain architecture avoids transitioning of test vectors into the circuit inputs at the time of shifting. This also saves power of the system during the test mode. Our architecture has been applied to ISCAS89 circuits. Simulation results reveal up to 66% reduction in the test power consumption when compared to the conventional scan-path architecture. I. INTRODUCTION reliability of the circuit under test (CUT) due to an excessive current density during the test. In addition, this amount of current may not be tolerated by low power circuits [2]. Secondly, the high switching activities during test increases the current flowing between the power and ground lines giving rise to a large resistive voltage drop. The voltage drop changes the voltage level of the circuits causing a good circuit to fails during the test [3]. Recently, a number of solutions have been proposed to deal with the power and energy problems during test of circuits (see e.g., [4]-[11]). These approaches, which mainly target combinational circuits, can be classified as follows [10]: Distributed BIST Control Scheme [2],[5], Vector Filtering Architectures [6], Low power Test Pattern Generators [7], Modified Scan-Cells [11], Circuit Partitioning for Low Power BIST [8], Modified Clock feed Tree [10]. In our work, a data compression based scan cell architecture that reduces the number of transitions in the scan-path during the test phase is presented. This paper is organized as follows. Section II describes the low power scan path architecture while the results are presented in Section III. Finally, Section IV contains the summary and the conclusion of the paper. II. PROPOSED LOW POWER SCAN PATH STRUCTURE

There are a tremendous number of devices on a single chip fabricated using the state of the art CMOS technology. This high integration has made the power consumption as one of the main concerns of integrated circuit designs. Additionally, the ever increasing utilization of portable computing devices and battery operated systems, such as laptops and cellular phones needs a low power dissipation in VLSI circuits. This is due to the fact that in such devices the energy consumption determines the lifetime of the batteries. Different techniques have been given in [1] for low power VLSI circuits. While these techniques lower the power consumption in normal operation mode, the test power consumption of these circuits has only recently has attracted attention which is mainly due to two reasons. Firstly, in [2] it was reported that the test power consumption increases considerably compared to the normal power consumption. This increase can be as high as 200% compared with that of the normal mode which stems from the higher switching activities during the test mode. Such high power consumption can degrade the

In this section, at first the data compression concept is reviewed and then we explain the low power scan cell structure which was utilized in this work. A. Data Compression In the general serial test method, all test vectors are applied to the Circuit Under Test (CUT) respectively but, in the data compression based test methods, the correlation of test vectors are decreased as much as possible. In the compression method that we are using for our architecture (test reuse [9]) the test set is partitioned and the repeated segments of test set are removed. To reduce the amount of test data, this technique removes the data that is left unchanged from one test to another. Fig. 1 shows an example for

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redundant test data that may be eliminated to reduce test time. In the upper part of this figure a pattern of six vectors, V1, V2, V3, V4, V5 and V6, with length M are shown. Each line represents a test vector that is serially shifted into part of a scan chain.
V1 V2 V3 V4 V5 V6 10100010101010001010101001010110001000 00101010100101001010101001010011110000 11111010000100001010101001010111001111 11010001001001001010101001010111100100 01010000001001001010101001010110101010 10101000010100001010101001010101011010 10100010101010001010101001010110001000 00101010100101.011110000 11111010000100.111001111 Repeated 11010001001001.111100100 segments are 01010000001001.110101010 removed 10101000010100.101011010

idea is to reduce the number of shift cycles with the help of test compression, in order to reduce the power consumption of the scan chain and the CUT. For example, suppose that for a test vector only the value of the i-th cell in the scan path should be changed and the values of other cells remain unchanged; in our architecture, all scan cells

Figure 1. Removing repetitive data patterns, test reuse.

Data shown in the shaded box remains unchanged for all six test vectors hence these bits are the candidates for the compression. The reuse compression consists of partitioning data by considering non-overlapping blocks of vectors. Binary compression of each block is then achieved by removing the segments (fixed and shared data) and shifting the remaining bits into the CUT. In the lower part of this figure the first test vector is the same as the original (uncompressed) vector in the upper part. However, the shaded part is only shown once and is eliminated from the other 5 vectors. The part that is eliminated from each vector is shown by dots. Test compression in test reuse relies on the fact that not all bits in test vectors that are applied to a CUT are different in every test. The methodology that is used in test reuse is preprocessing test data and generating compressed data for off-chip test application. Compressed test data shifted into the chip will be uncompressed by scan cells and distributed through CUT. B. Data Compression Based Low Power Scan-Cell Architecture In conventional scan-based test method, each test vector is shifted into the M-length scan-path separately in M clock cycles. Each shift operation in scan-path may change the values of CUTs inputs and these new values are propagated through the CUT which leads to many switching activity in CUT nodes every clock cycle. This high number of switching activities results in a high power consumption during the shift phase. In our data compression based test method, we change the scan-cell architecture to reduce power consumption by both decreasing the number of CUTs switching activities and reducing the scan chain power consumption. The main

Figure 2. Scan cell architecture

before and after the i-th cell can preserve their values and only the value of the i-th cell will be changed, in one clock cycle. Conventional scan chain architecture requires M shift cycles to do the same work. Fig. 2 shows our proposed scan-cell architecture. Like a conventional scan-cell, it has two operating modes: normal mode or test mode. In normal mode, the cell acts as a flip-flop. In test mode, it operates as a part of scan-chain to shift-in test data. To support test compression, during the test phase every cell could operate in two modes: transparent mode and shift mode. Those cells which must retain their previous data are set in transparent mode. In this mode, the Scan In input of the cell is connected to its Scan Out output and transitions in the input of the cell are propagated directly into the input of the neighboring cell. In shift mode, the cell acts as a flip-flop and every value in the input of the cell, will be captured in clock edge and will overwrite the data of the cell. The operating modes of the proposed architecture are controlled by Normal/nTest and Shift/nTransparent signals. When both signals are 1 the circuit is in normal mode and otherwise it is in the test mode. However, in test time another normal mode of operation exists for Normal/nTest and Shift/nTransparent equal to 1 and 0 respectively. This operating mode is also considered as a normal mode but it is only valid during the test time. When the test finished, all Shift/nTransparent must be reset to 1 to avoid the latter form of normal mode. Totally, the scancell has three different operating modes, shown in Table I. During the test mode, scan data are fed to cell via the Scan In input, and in normal operating mode Data In input feeds the cell.

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TABLE I. Mode Transparent Shift Normal

OPERATING MODES Shift/nTransparent 0 1 X

Normal/nTest 0 0 1

Figure 3. A typical scan path

results are checked by the MISRs. The BIST controller shifts the compressed test data into the scan chain and generates control signals for each of scan-cells. It controls the transparent or shift mode of cells by generating Shift/nTransparent signal for each of them. Suppose that we wish to apply six compressed test vector of Fig. 1 to a CUT. First, the BIST controller puts all scan cells in the shift mode and then shifts the first test vector, V1. After switching to the normal mode, test data pass through the CUT and the MISR will check the results. For shifting the next vector, V2, the controller puts all cells that their data must be changed in the shift mode and the other cells (those that correspond to the shaded areas of Fig. 1) in the transparent mode. When circuit return to the normal mode, those cells which were in the transparent mode have old values and other cell have new values generating the new test vector. The same process is repeated for vector V3 to V6. When the test session is completed, BIST controller puts all scan cells in the shift mode and the circuit continues its normal operation. To control the mode of each cell, it is necessary to control Shift/nTransparent signal of every cell. This means that each cell should be addressed individually increasing the hardware overhead notably. To deal with this problem, some of scan cells can be grouped and controlled by the same Shift/nTransparent signal. The groups can have unequal sizes.

Every cell has two outputs: one to fill the scan-path which gives the test data to and, the other one is the input for the CUT which gives the cells data to the CUT. In the normal mode Latch 0 and Latch 2 make a flipflop when Shift/nTransparent signal is 1. If Shift/ nTransparent is zero, the input is always disconnected from output. During the test and in the shift mode Latch 0 and Latch 1 will make a flip-flop which is used for shifting test data. In the transparent mode both these latches are enabled and the scan data transparently reaches the output of the cell. Latch 2 is controlled by Normal/nTest signal and either in shift or in transparent mode this latch is disabled, preventing changes in circuit input. C. Scan-Cell Utilization In this subsection a typical test session of a scanpath that utilizes the proposed scan-cell proposed in this work is presented. This session shows how a compressed test set can be applied to a circuit under test. Such a scan-path can be a test-per-scan BIST scheme similar to that shown in Fig. 3. In this scheme, test data are shifted in the scan-chain in the test mode (the test mode is the transparent mode for some cells, and shift mode for others). After that, the CUT returns to the normal mode and test data are applied to it and the

III.

EXPERIMENTAL RESULTS

To evaluate the architecture proposed in this work, we utilize some of the ISCAS 89 benchmark circuits. In these circuits, we make a scan chain of all flip-flops where every eight scan cells are placed in one group. To estimate the power consumption, synthesis, layout extractor, and circuit simulator CAD tools are used. The VHDL codes of the circuits are synthesized, using a 0.25 micron library. The synthesis results are utilized for extracting the layout of the circuits where the output of the layout extractor tool is fed to the circuit simulator CAD tool. The power consumption of the circuits is calculated using SPICE. Similar steps are followed for calculating the power consumption of a conventional scan path. Table II shows a comparison between the power consumption of our method and that of the conventional one which uses flip-flops as the scan-cell. It also compares the power consumption improvement of our proposed structure with that of the low power structure proposed in [10]. As shown, our method has less power consumption in all cases compared to that of the conventional method. When compared to the power reduction of [10], in most cases our method is superior. In addition, Table II shows the increase in the number of transistors compared to that of the conventional method.

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The increase includes the number of transistors for proposed scan-path and its controller in each circuit. IV. SUMMARY AND CONCLUSION

[4]

In this paper, a new structure for scan-cell was proposed. This architecture uses test compression methodology to reduce power consumption. Compressed data is shifted into the scan by putting those scan cells that have a new value in the shift mode, and the rest in transparent mode. This scheme reduces the power consumption during test. Because of the usage of the compressed test vectors, another benefit of proposed architecture is the reduction in test time and memory usage for the test vectors. REFERENCES
[1] M. Pedram, "Power Minimization in IC Design: Principles and Applications," in ACM Transactions on Design Automation of Electronic Systems, vol. 1, no. 1, pp.1-54, Jan. 1996. Y. Zorian, "A distributed BIST control scheme for complex VLSI devices," IEEE VLSI Test Symposium, pp. 4-9, Apr. 1993. N. Nicolici, Bashir M. Al-Hashimi, "Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation," IEEE International Test Conference, pp. 72-81, Oct.-Nov. 2001. TABLE II. Circuit S1423 S1488 S1238 S1196 S5378 S9234 S13207 S15850 S38417 # of Transistors 6363 3037 2722 2220 15856 18899 51389 32071 37806

[2] [3]

H. Cheung and S. Gupta, A BIST Methodology for ComprehensiveTesting of RAM with Reduced Heat Dissipation, Proc. IEEE Intl Test Conf., Nov. 1996, pp. 386-395. [5] R.M. Chou, K.K. Saluja, and V. D. Agrawal, Power Constraint Scheduling of Tests, Proc. IEEE Intl Conf. on VLSI Design, Jan. 1994, pp. 271-274. [6] S. Manich, A. Gabarro, M. Lopez, J. Figueras, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, P. Teixeira, M. Santos, "Low power BIST by filtering non-detecting vectors". Journal of Electronic Testing: Theory and Applications, vol. 16, no. 3, pp.193-202, June 2000. [7] S. Wang and S.K. Gupta, DS-LFSR: A New BIST TPG for Low Heat Dissipation, Proc. IEEE Intl Test Conf. 1997, pp. 48-857. [8] P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch," Circuit partitioning for low power BIST design with minimized peak power consumption," IEEE Test Symposium, pp. 16-18, Nov. 1999. [9] F. Karimi, W. Meleis, Z. Navabi, and F. Lombardi, "Data Compression for System-on-Chip Testing using ATE," IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 166-174, 6-8 Nov. 2002. [10] P. Girard, L. Guiller,C. Landrault,S. Pravossoudovitch, H.J. Wunderlich," A modified clock scheme for a low power BIST test pattern generator," IEEE VLSI Test Symposium, 306 -311, 29 April-3 May, 2001. [11] A. Hertwing and H. J. Wunderlich, Low Power Serial Built-In Self Test, Proc. IEEE European Test Workshop, 1998, pp. 49-53.

COMPARISON BETWEEN THE PROPOSED TECHNIQUE AND CT (CONVENTIONAL TECHNIQUE). Increase in # of Transistors Compared to CT 34% 23% 28% 31% 33% 28% 32% 30% 25% Power Consumption (mw) 6.3 3.3 2.1 1.9 17.4 35.9 40.3 56.8 50.1 Improvement Compared to CT 42% 51% 61% 60% 58% 61% 72% 66% 71% Improvement of [10] Compared to CT 55% 49.5% 64.7% 40% 44% 38% -

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