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Circuit Analysis for Hi3560Q

2011-05-21

` Main Board Power Supply

W 9 8 7 6 5 4 3 2 1

100N

4 A

7 U

/ 5 2 4 V

0 V 1 _ I N

0 0

L W 7 B 1 2 0 R

L W L W L W 100N 100N C W 21 C W 22

F4 B F1 B F2 B

1 1 1

2 0 2

3 A 3 R A C W 0 0 2 8 N 0 1 3 A 3 V 4 V 3

0 R 2 0

( 2

. 5

4 m

Power Supply Interface

C W 25

C N

W C

E 1 5 / 1 0 U

/ 1

6 V

1 2

V 5 V 9

W F

1 / 1 6

0 U

Definition for JPW1 Power Supply Interface1 GND 2 3.3V 3 3V3 4 GND 5 5V8 6 5V8 7 GND 8 15V 9 30V

5V For Dac and video buffer


5 V 9 1 U C M C U _ P R W W R 1 7 C T L 3 V C 2 E 5 6 IV N O G N D E N 5 2 1 U C 5 4 8 E T C 1 0 R N W C 1 2 8 C W +9 0 N1 0 W E 0 U 1 3 F / 1 6 V 5 0 M V 0

+
2

C U

W F

EC 6 W

2C 3 W

6 0 N

2 0

/ 1 1 0 6 0 V N1 0

0 R

5V for USB

5 V 9 1

U C

2 4 E 6 2 1 5 A 5 0 G L D V I N G N V O U T D 3

5 V 0 _ U

S B

G N

1 3 2

1 1

E 8 / 1 6 V

1 0 0 N

1 0 0 N

2 2 0 U

R W 2 1 3 0 0 R

1v25 for demo

3 V

3 _ M

O U

S W I N A 1 D 4A V V Z O O 1 1 1 7 - A U 2 T 1 U 4 T 2 D J

1 V

2 5 _ L

3 C W

V E* 1 F

C W E16

C W 3

R 1 0 0 U / 1 6 V R W 0 R N

W C 8

1 0

1 0 0 N

1 0 0 U F /1 6 V

100N

1V2 for Hi3560Q Core


3 V 3 U 3 V W I N A D 3 A V V J Z O O 1 1 1 7 - A U U T 21 T 42 C W E 1 10 0 0 U F / 1 6 V C W 8 D J 1 V 2

C 1

S 0 0

5 N

R 2 5 1 2 0 R

1 0 0 N

9V for audio amp

1 2 V
1 2 V 0 C A 5 N U A 1 7 8 L 0 9 V I NV O G N 2

T o
L A 3 N C / 5 R 1

9 V
9 V

U D

C A4

A +E 4 7 U F /1 6 V

1 0 0

100N

2v5/1v25 for SDRAM

3 V

3 A

2 2 0 U

/ 1 6 V

U
1 2 3 4 R B V V V

0
2 V 5 1 V 2 5

1 0 0 U F / 11 06 0V 1N 0 0 N 1 0 0 N C / 1 0 U F / 6 . 3 V

8+

CE W5

C1

2 W

8 P V O U T 7 1 I N 1 G N D 6 I N 2 V O U T 5 2 C N VT R E F E 9N L S I N K T 9 0 0 5 A P S P

L W 5 F B 1 2 0 R

1 0 0 N

R
1 0 K

3
_ 1 %

1 C0 W

1 C7 +
/ 6 . 3 V

E
F

4
/ 1 6 V

1 0 0 N 1 0 U F

2 2 0 U

C 0

/ 1 0 U

F 1/ 60 . 0 3 N V

1 0 K

_ 1 %

13V/18V for LNB

0 _ 3 V R

3 T 3 2 3 R

R T 4 1 4 K 7 L N 1 C T 4 6 4 2 A T A B V O U T D V J I N 3 2 4 V C T B _ E N R T 4 0 4 K 7 2 3 1 Q T 1 2 S C

1 8 1 5

i s e q c _ O R U T T3 9 1 0 0 R C T 4 5 R 1 K 1 0 N

T 3 7

1 0 0 N T 3 8 2

1 0 K

U T 1 L M 3 1 7 C T 1N C 1 1 2

T 1 0

T 2 2 3 0 0 R R T 7

T 4 1

C+

E F

T 6 / 5 0 V

1 2 K V _ S E LR T 1 9 3

1 0 0 4N 7 U

. 3

1 2

1 0 K

Q 2 S

1 0 K T 2 R T 2 1 C 1 8 1 5 9 K 1 R T 1 8 C T 4 4 C T 4 3 8 K 2 3 3 0 P F 1 0 0 N

3V3 for tuner

R W 1 1 2 0 0 R R W 1 3

1 2 0 R 4 2 E +2 1 F C 2 5 F A 1 3 V 3 _ T U N C E R W V V U O O Z W U U A D J T 2 T 1 V

I N

3 C D J 2 4 F C W 1 0 U

5 V 4 F

1 0 U

/ 1 0 V1 0 0 N

5 1 1 1 7 - A

1 0 0 N

/ 6 . 3 V

P O W E R

F O R

A U D I O

1 2 V L B 1 6 N C / F B 1 2 0 R 3 A

1 2 V 0

Q 2 N

7 2 9 0 7

R W 2 1 0 K

2 3 1 0 0 N

+
F

E 1 2 F

2 1 F

1 0 U

/ 2 5 V 1 0 0 N

R 3 V 3

W 1 5 1 0 K

R W 5 4 K 7 1 , 7 M C U _ P W R C T L M C U _ P W R C T L R W 2 K 2 1 4 1 B

Q W 6 2 S C 1 8 1 5 2

2 4 V

_ I N L B 2 0 N C / F B 1 2 0 R 3 A

2 4 V

Q W 7 A O 3 4 0 1 A

2 C R W 1 9 2 4 K 3 7 F

1 0 0 N

1 R 2 4 3 1 0 0 K 3 B Q 2 S 2 C W 2 C 1 8 1 5 E

8 1 2 4 V _ C O N T R

m A O

( N

M A X T R O

) L R 2 K W 2 1 2 1

2 4 V _ C O L

W 2 0 4 K 7

3 V 3 _ M O 3 V 3 N L B 1 8 C / F B 1 2 0 R 3 A C 6

Q W 4 U T 2 3 0 1

1 0 0 N 2 S D 3

W 1 K

1 6

2 2 0 N

1 R

3 5

G 1 4 7 5 R R 2 4 2 1 K R 2 4 1 1 5 0 K

C Q W 1 2 S C 1 8 1 5

1 , 7

M C

_ P W

T L

M C

_ P W

T L

2 K 2

Main Point: Test whether the voltage for power supply interface is established after opening STB.
Exclude the power board failure and then test the board to see if the voltage is normally established. Notice that just as standby control pin is high level , the voltage can be established.

Tuner and Demodulator

RF-OUT

RF-IN

C T 4 7 3 V 3 _ T U N E R 1 0 0 P F 2 L T 4 F B 1 2 0 R 3 A L T 5 F B 1 2 0 R 3 A D 2 1 N 4 0 0 7 1

C T 3 2 1 0 0 P F 500mA L N B B L N B A 40mA 145mA C + E T 7 0 U 4 5 F / 1 0 V C C T 1 0 N 3 3 C 1 2 3 4 5 6 7 8 9 1 0

N G

B 1 B B 1 A B 4 (3 V 3 ) B 2 (3 V 3 ) Q O U T I O U T A G C S D A S C L C L K -O U T D D D G G G

T 1 T U N - S H

1 1

1 2

1 3

1 4

E T 7 0 U 4 1 F / 1 0 V

T 1 0 N 3 4

A R P - 7 3 0 6

I P Q P

R T 4 R T 5

0 R 0 R C T 3 5 N C C T 3 6 N C R T 2 4 R T 2 3 C T 3 7 1 0 N C T 3 9 2 0 P F C T 4 0 2 0 P F

V D D 0 _ 3 V 3

R T 3 3 3 9 0 R R T 1 1 2 K C T 4 2 1 0 N V D D 0 _ 3 V 3 R T 3 6 1 N C R T 3 0 R R T 1 2 2 K 2 A A G C R T 8 1 K R T 9 1 K

3 3 R 3 3 R

S C L T S D A T

Q T 3 2 N 5 5 5 1 3

C T 3 8 N C R T 3 1 4 7 R

V D D A _ 3 V 3 V D D 1 _ 1 V 2 5 V D D 0 _ 3 V 3

M L N

O B

_ L O _ E

T 2 F

T 3 F

D N

_ L O 1C

3 0 P

3 0 P

5 5 C K X T A L _ 1 3 5 O L F 4 G N D 6 G N D

1 M C C 2 P T 8 T 5 C T 4 1 2 3 4 5 6 7 8 9

L N B _ E N

Y T 1 2 7 M H T 2 7

6 4

6 3

5 8 5 7

5 6

5 5

2 1

0 9

6 2

6 1

6 0

5 9

5 4

T 2

5 3

V D D D

L O C K

G P O

V C C

V C C

N C

N C

N C

N C N C

N C

N C

C 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 R N1 T 3 2 3 4 N 1T 2 2 3 4 1 2 3 4 R N 4 7 R V D D 0 _ 3 V 4 7 R 8 7 6 5 X 4 N

T 1 3 C T S I _ C T S I T T S I _ _ _ _ _ _ _ _ D D D D D D D D A A A A A A A A L _ S _ T T T T T T T T K S Y I _ V E R 7 6 5 4 3 2 1 0 I _ D A T [ 0 . . 7 ] T S I _ D A T [ 01 . . 7 ] T S I N C T S I A L T S I T S I _ _ _ _ C L K S Y N V A L E R 1 C1 1 1

F 1 0 0 N

I P

1 0 0 N Q P C T 9 1 1 1 1 1 1 1

V D D D A D D R _ S E L 1

C 2 P

T 6 F

T 7

D S D A T

D IS E Q C

1 0 0 N

C K X T A L _ 2 7 R E S E T

D IS E Q C _ IN

1 0 0 N

A D D R _ S E L 0

A A G C

S C L T

V S E L

0 1 2 3 4 5 6

V C C

V C C

V C C

S D A

G N D X T A L X T A L V D D G N D I P I N V D D G N D Q N Q P N C V D D V C C V C C N C

A _ I N _ O U A A A A

8 8 D

3 0 0 2

4 M _ C L K4 _ S Y N 4C V C C 4 M _ V A L4 M _ E R R4 M _ D 74 M _ D 64 V D D D 4 M _ D 53 M _ D 43 V C C 3 M _ D 33 M _ D 23 M _ D 13 M _ D 03 V C C

84 7 R 7 6 5 8 7 6 5 T 1 X 4 3

XT T T T T T T T

4S S S S S S S S

I I I I I I I I

T S

1 7

1 8

2 3 2 4

S C L

2 5

2 6

2 9 3 0

3 1 3 2

1 9

2 0

2 1

2 2

2 7

2 8

R T 2 0 1 0 K R C V D D 0 _ 3 V 3 A C T 1 51 0 0 N C T 1 61 0 0 N C T 1 41 0 0 N C T 1 71 0 0 N C T 4 91 0 0 N A V G D C D 0 _ 3 V 3 D is e q c _ O V _ S E L 3 U T V D D 0 _ 3 V 3 V D D 1 _ 1 V 2 5 T 1 2 T 1 0 R 3 V 3 _ M O S 1 0 0 N T U N E R _ R S T U T N E R _ R 1 S T

L T 1 F B 1 2 0 R 3 A + C E T 2 1 0 0 U F /1 6 V

3 V R T 1 7 4 K 7 V D D 0 _ 3 V 3 S S C D C L T A T T 1 8C T 4 8 F C T 1 0 F C R T 1 6 4 K 7 I 2 C I 2 C _ A _ A D D R R T 2 5 2 3 3 R D D R 0 R 1 T 1 4 K 2

T 1 3 2 K 2 S S D C A L _ T U N E R S C _ T U N E SR D L _ T U N 1 , R8 E A _ T U N 1E , 8 R

R T 2 6 T 1 13 3 R F

N 3 V 3 _ M O S V D D A _ 3 V 3

T 3 5 C / 0 R

T 3 4 C / 0 R _ A D _ A D D D R R 0 1

4 7 P

F 4 7 P

2 0 P

2 0 P

I 2 C I 2 C

L T 2 F B 1 2 0 R 3 A + R T 2 0 R R T 6 0 R C T 1 91 0 0 N C E T 3 2 2 0 U F /1 6 V C T 2 01 0 0 N C T 2 11 0 0 N
R 5N T3 = C R =R T2 0 R 5N T3 = C R =R T2 0 R 50 T3 = R R = C T2 N R 50 T3 = R R = C T2 N

C ip a d ss o M 8D 3002 h d re f 8 S
V e o RT 5 RT alu f 3, 2 an RT 4, RT d 3 6
R 4N T3 = C R = T6 0R R 40 T3 = R R = C T6 N R 4N T3 = C R = T6 0R R T34 0R = R T6= C N

O ratio a ress pe n dd Rea d D D D D 1 H 3 H 5 H 7 H W rite D D D D 0 H 2 H 4 H 6 H

1 V

2 5 _ L N

B V

1 _ 1 V

2 5

L T 3

The above is schematic diagram for tuner, T1 for SHARP-7306, and with the CPU function through the IIC busmastering UT2-M88DS3002, then through the UT2-M88DS3002 IIC control satellite signals change into the input IF signal output. After demodulating by UT2-M88DS3002, digital TS stream signal would be output finally. No matter CPUs control or Tuners feedback are all come true by IICSCLSDA. However, the data which CPU decode picture & voice is controlled by TSTSIN_DATA07. So, if TS stream is abnormal, which would not affect the testing for signal quality and strength of channel searching. But if IIC cable is abnormal, signal quality and strength cant be tested and even not decode for corrected TS stream.

Main Point: Judge if Tuner and demodulated IC work normal:


1) 2)

Whether there is 4M CLK signal output from10th pin of T1? Whether there is normal signal output from 5th and 6th pin of T1?

3) Whether there is waveform with 27M from YT1 crystal oscillation?


4) 5)

Whether there is normal AGC signal output from 17th pin of UT2-M88DS3002? Whether there is low PWL 3V3 from 32th pin of UT2-M88DS3002?

6)

Whether there is normal output from TS streamTSIN_DATA07,CLK, SYNC,VALof UT2-M88DS3002?

Memory

E E E E E E E E E E E E E E E E E E E E E E / W / O / C

B B B B B B B B B B B B B B B B B B B B B B E E

I I I I I I I I I I I I I I I I I I I I I I E

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

A A A A A A A A A A A A A A A A A A A A A A

B1 B1 B B1 B1 B4 B B B B B B B B B1 B1 B2 B2 B2 B2 B2 B2

1 2 3 4 5 6 7 8

2 3 2 0 1 1 6 1 7 1 8 1 1 1 1 1 1 9 8 7 8 6 9 5 0 4 1 3 2 2 3 1 4 0 5

U S

1 0A 9A 8A 7A 6A 5A 4A 3A 2A 1A 0A A A A A A A A A A A A

F 2 2 9 G 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 1 0 9 8 7 6 5 4 3 2 1 0

L 0 6 4 N D

9 0 T F 4 Q 1 4 / A 4 D Q 1 44 D Q 1 33 D Q 1 32 D Q 1 31 D Q 1 30 D Q 93 D Q 84 D Q 74 D Q 64 D Q 53 D Q 43 D Q 33 D Q 23 D Q 12 D Q 0 P

I 0 4 0 E 5 - 1 E 3 E 1 E 9 E 6 E 4 E 2 E 0 E 4 E 2 E 0 E 8 E 5 E 3 E 1 E 9

B B B B B B B B B B B B B B B B

I I I I I I I I I I I I I I I I

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

D D D D D D D D D D D D D D D D

B B B B B B B B B B B B B B B B

1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0

5 4 3 2 1 0

1 4 # / A 4C 7 C B Y T E 1 #2 R E S E 1T 5# R Y / B Y # V G G N N C C 3 7

W P B Y T E / R S T _ S 3 V 3

/ R

T _ S

Y 1 S, 8

_ E 1B 1 I E # _ E B 8I W 2 O HE # _ F L A S 2 6 C E #

2 7 D 41 6 D 2

1 0 0 P F

2 V

C D 1 +

1 V

2 5

1 V

2 5

1 0 U F /6 .3 V

C D 2

C D 16

C D 17

C D 11

100N

100N

100N

100N

100N

C D 13

R D 19 R D 7 R D 8 R D 9 R D 10 R D 11 R D 12 R D 13 R D 14 R D 15 R D 21 R D 20 R D 22

100R 100R 100R 100R 100R 100R 100R 100R 100R 100R 100R 100R 100R

5 D

_ A

DDR_ADDR[0:12]
R [ 0 : 1 2 ]

U
2 3 3 3 3 3 3 3 3 4 2 4 4 1 5 5 1 4 4 4 4 4 2 2 2 2 2 9 0 1 2 5 6 7 8 9 0 8 1 2 A A A A A A A A A A A A A

1
D D D D D D D D D D D D D D D D V V V N N N N N V V V V V V V V S S S S S S S S D D D C C C C C S S S S S S S S Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q D D D _ _ _ _ _ Q Q Q Q Q 1 1 1 1 1 1 6 6 6 6 5 5 5 59 18 17 16 85 74 53 42 21 0 5 53 42 30 29 17 06 4 3 1 0

100R 100R 100R 100R 100R 100R 100R 100R 100R 100R 100R 100R 100R 100R 100R 100R

R R R R R R R R R R R R R R R R

D D D D D D D D D D D D D D D D

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

100N

C D 3

2 V

1 V

2 5

DDR_ADDR0 DDR_ADDR1 DDR_ADDR2 DDR_ADDR3 DDR_ADDR4 DDR_ADDR5 DDR_ADDR6 DDR_ADDR7 DDR_ADDR8 DDR_ADDR9 DDR_ADDR10 DDR_ADDR11 DDR_ADDR12 1 1 5 1
Q S 0

R R

D D

0 0 R 0 0 R
R R D D 6 6 22 12

0 1 2 3 4 5 6 7 8 9 1 0 / A 1 1 1 2

1 K

_ 51 % D
5 D

D D

R R

_ D _ D

DDR_DQS1 Q S 1 DDR_DQS0 D D D D D D D D D D D 6 2 3 1 4 3 4 4 4

2 R 2 R

9 0 D N U _ 0 1 D N U _ 1 6 U D Q S L D Q S 9 7 6 5 4 0 1 2 3 4 V U ^ C C L ^ ^ ^ ^ R D K K W C R C D A A S A A D D D D D 0 1 D D D D D Q Q Q Q Q _ _ _ _ _ 1 2 3 4 5 E F M E M E S S

R R R R R R R R R R R R R R R R
2 V 5

D D D D D D D D D D D D D D D D

6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4

20 29 28 27 26 25 24 23 22 21 20 29 28 27 26 25

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

R DDR_DQ15 R DDR_DQ14 R DDR_DQ13 R DDR_DQ12 R DDR_DQ11 R DDR_DQ10 R DDR_DQ9 R DDR_DQ8 R DDR_DQ7 R DDR_DQ6 R DDR_DQ5 R DDR_DQ4 R DDR_DQ3 R DDR_DQ2 R DDR_DQ1 R DDR_DQ0

DDR_DQ[0:15]

100N

C D 15

_ D

5Q

[ 0

: 1 5

100N

100N - E

100N

1 0 u F / 6 . 31 VK

_ 1 %

R R

4 13 0 4 14 0

0 R 0 R

DDR_BA0 DDR_BA1

2 6 2 7 B B 3 V 9 1 5 V 5 5 V 6 1 V V

6 5 5 1 6 6 _ 4 _ 3 _

4 _8 _2 _2 _ _ 6 2 8 1 4 0

5 4 3 2 1

100N

C D 12

100N

100N

100N

C D 6

C D 8

C D 9

E D

5 1 1 6 A

T A

- 5 B

C D 4

D D R _D M 1

D D R _C KN 0

D D R _C KP0

D D R _C KE D D R _D M 0 D D R _W E D D R _C AS D D R _R AS 5 D D R _C S D D R _BA0 D D R _BA1 5 5 5 5 5 5 5 5

100N

6 3 / 3 0 0 R

100N

8 R

R R R R R R R R R

1 1 1 16 1 19 10 11 12

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

R R R R R R R R R

DDR_DM1 DDR_CKN0 DDR_CKP0 DDR_CKE DDR_DM0 DDR_WE DDR_CAS DDR_RAS DDR_CS

DDR0

C D 7

C D 5

C D 10

5 4 2 1 1

3 43 35 27 14 0

C D 14

1 1_ 8 0 3_ 3 1 _ 2

Above refer to partial circuit for FLASH [UF2] and DDR [UD1]. The main function of Flash is stock software code which storage system needed and conserve all code after power-down. Therefore, it requests flash could complete restoration before CPU reset and then waiting for CPU reading. In fact, STB upgrading process is also updating the FLASH program code, which need to make sure do not power-off during upgrading to avoid system halted when code updating. The main function of DDR is stock procedure and program temporarily in system operation. When power-off, all data will be disappeared. Their work are two differential clock signal CLK, currently used in the 133MHz frequency, a single peak is about 700mV around the clock, the oscilloscope measurement of peak value is about 3.3V. If the rate is too low, it would cause the system run unstable, causing crashes, mosaic, and slow response to the problem. LMI_VREF is the reference voltage of DDR, the design voltage is 1.25V. If the voltage ripple is too large, it will cause the system run unstable.

Reset Circuit and Surge

3 V

3 R 5 S 1 R 3 C R ESET S 6 1 4

3 V

VC C

U C Y

G N D

S 1 T 8 0 9 - TCM809 V 2 . 6 3

1 0 0 N

R N U
/RST_SYS
/ R S T _ S Y , S5 1

S C

5 / 4

S
A A A G 0 1 2 N

2
8 C 7 P 6 S C L 5 D S D A V W C S C S D L _ T U A _ T U N N E E R R

1 2 3 4

C B 5

R S 2 5 1 0 0 K

Addr:0x1010000 2 4 C 6 4

R 1

S K

100N

I _

T SI_DAT[0..7]
T [ 0 . . 7

MISC(2) Interface 3 of 3

3 V

1 0 0 U F /1 6 V

9 9 9

T S T S T S

I _ I _ I _

S C V

Y L A

N K L

10N

T SI_DAT0 T SI_DAT1 T SI_DAT2 T SI_DAT3 T SI_DAT4 T SI_DAT5 T SI_DAT6 T SI_DAT7 TSI_SYNC C TSI_CLK TSI_VAL

U
2 3 5 6 7 8 9 T T T T T T T T T T T U U T T T T ^ F S S 2 4M 5M 6T 7T 8T 9T 1T 3T 5R 6R 7R 8R 9R 1R 2R 3C C

2
S S S S S S S S S S S I I I I I I I I I I I

B
D D D D D D D D S C V A T A T A T A T A T A T A T A T Y N K L D 0 1 2 3 4 5 6 7 2 I M _ 2D I M _ P2 I M _ R S S D A I M I M

^ U U

S S U U

DAT _SIM 0 E N 1 A T AP W W2 R /RST _SIM E N E S E T


L K DEC_SIM E T

3 V D A T _ S I1 _ S I M P W E N _1 / R S T _ S 1 C D C V V V

3 _ D M0 S0 I M I 0M

1 1 1 1 1 1 4 5 5 5 5 5 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 5 5 6

0 1 3 4 7 8 9 0 1 3 4 6 6 7

2 4 _2 C6 _ D

Mode Selection: 0:Normal Mode 1:Test Mode

1 0

/ T R D C M M T T T T T T R R R R R R R C C

T N

R 11

8 , 9 S 8 , 9S

A _ T U L _ T U D D

SDA_T UNER N SCL_T UNER E R


E R

3 V

X X X X X X

4k7

X 2 C 3 2 7
5

1 7 M F
/ R

I R

I N

IR_IN 0 R

P
, 8

1M

2 9 5 I 7 ^ 9 ^ 0 X X

T _

/RST _SYS
Y S

2 1

R C 1 5 0 0 P F

I 3

N C /4 K 7

4 2

F R2

X X X X X X X R O

D D D D E C

MDC_MII C _ MMDIO_MII I I I O _ M I T XD0_MII I


0 1 2 3 N K _ _ _ _ M M M M _ M _ M _ M _ M _ M _ M _ M _ M _ M M I M I I I I I

R3 3 .4 8 K _ 1 %

D D D D D E C

0 1 2 3 V R K S _ L _

IT X D 1 _ I T XD2_MII I T XD3_MII I T XEN_MII I IT XCK_MII I IRXD0_MII I RXD1_MII I I RXD2_MII I I RXD3_MII I I RXDV_MII I I RXER_MII I I RXCK_MII I I CRS_MII I I COL_MII

N C /1 K

I I

0 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 2

10N

URXD0 8 U R X D 0 UT XD0 8 U T X D 0 TDO_CPU 1 0 T D O _ C P U TDI_CPU 1 0 T D I _ C P U TCK_CPU 1 0 T C K _ C P U TMS_CPU 1 0 T M S _ C P U /T RST N_CPU

R X D 0 / G P I O 2 0 T X D 0 / G P I O 2 1 D O D I T C K LRCK_IIS 9 4 M S S I O X 9F 6 S L R C K _ 3I I S DAT A_IIS T R S T N S I O D9 O D A T A _ I3 I S BCLK_IIS 7 U N S E L S I O X 9C 9 K B C L K _ I3 I S MCLK_DAC D A S I O M C L K 1 / 0G 1 P I SPDIF 7 O 2 M C L K _ 3D A C C L S P D I F O U 9T 0/ G P I O 2 8 S P D I F 3 USB 2.0 Host Only S I O B D O / P W M 1 D C K ID_USB R 8 0 R 3 1 D I O O T G 3 I D2 VBUS_USB X D 0 O T G V 3B 6 U S V B U S _ 1U 0 S B DP_USB X D 1 O T G 3 8P D D P _ U S 1B 0 DM_USB X D 2 O T G D 0M D M _ U S 1B0 4 X D 3 O T G R 4 E3 X T VBUS_EN X E N / G P I O 3 0 O T G D R V V B U S V B U S _ 1E 0 N X C K / G P I O 3 1 G P I O _ L O C K 2 7 X D 0 / G P I O 3 2 G P I O2 80 CLK_LED C L K _ L E8 D X D 1 / G P I O 3 3 G P I O2 91 DAT A_LED D A T A _ L8 E D X D 2 / G P I O 3 4 G P I O1 22 4 C V B S / R G B X D 3 / G P I O 3 5 G P I O 1 12 47 S D A _ R F S D A _ R 1F 1 X D V / G P I O 3 6 G P I O 1 16 51 MCU_PWRCTL M C U _ P 6W , 7 R C X E R R / G P I O 3 7 G P I O 1 16 8 T SI_ER T S I _ E R 9 X C K / G P I O 3 8 T S I E R R / 8 G 9 P I O FP-STB 1 9 R S / G P I O 3 9 S I O B D I / 9G 2 P I O T2 U N E R _ R FS PT - S T B 8 2 O L / G P I O 4 0 S I O B R F S 9 / 1G P I O 2 3 24V_CONTROL T U N E R 9 _ R S T S I O B X F S 8 / G8 P I O / R 4 S T _ E T H 2 / R S T _ E T H R I N / G P I O 4 4 S I O B X C K 9 / G P I O 4/32OR 16/9 5 5 W D G R S T S I O D I / G 1 P0 0I O 4 M2 U T E M U T E 3 R S T N S I O R F S / 1 G 2 P6 I O 2S 6 C L _ R F S C L _ R 1F 1 I N T S I P W M / G P I O 4 3 O U T

C D A D A D A D A R D A C D A V R D A V R

6 7 S 7 V0 M C 7 B3 C 7 G6 C 7 R9 E8 0X T O8 M P 1 E 2F I N 8 E F O U

CVBS VDAC_B VDAC_G VDAC_R

L K _ S I1 M 0 E C _ +S 1 I M0 V D D D B A A A S C C C 1 1 _ 1B 1 _ 1G 1 _ 1R 1

CE1

CLK_SIM

C 2

R5

R R

7 1

4 2

K 7

7 0

_ R

4K7

C 1

I O

R6

R4

T L

The above picture shows the EEPROM, reset circuit, HyperTerminal, and part of the schematic system clock. Reset is precondition for the entire start system. Normally, when power supply is in 200-300mS, 2nd foot of Us1 / RST_SYS signal would go from low to high, which began CPU reset. US2's EEPROM chip is a IIC bus devices, controlled by the CPU, when saving some systems need to power down some small amount of information, such as channel information, system settings, and a small amount of data. X1 is the system clock signal . Through this pin in C3 and the voltage 2.5V to produce oscillations, which make 27M sine wave signals in the C4 pin.

Video and Audio


U V V V D D D A A A C C C _ R _ G _ B 1 2 3 4 5 V _ A 3 A 2 3 5 V 2 1 F M I N 1 O I N 2 O I N 3 O V C C G 6 1 4 3 8 U T 71 U T 62 U T 53 N D S R G R R R 2 2 5 7 5 R 2 2 6 7 5 R 2 5 1 7 5 R _ 1C % 2 3 1 2 2 0 u F _ 1C % 2 3 2 2 2 0 u F _ 1C % 2 3 4 2 2 0 u F /R 1 _ O 6 V / G 6 _ VO 1 / B1 6_ V O U U U T T T

5 V

L V F B

1 2 0 R C

2 N

1 0 0 u F

/ 1 1 06 V0

+ ++

U 1 2 3

2 6 5 4

5 V

_ A

I N O U T G N D V C G N D C N C / S G M

9 1 1 3

R N U C V B S 1 2 3 4 2 0 I N 1 I N 2 I N 3 V C C F M 6 1 4 3 8 O U T 1 7 O U T 2 6 O U T 3 5 G N D S C R / 1 6 V C 2 3 3

2 2 8 / 7 5 R 2 2 7 _ 1 % _ 1 % C

_ T V

_ O

_ O

T 1

2 2 0 u F

7 5 R

5 V

_ A

C 1

V 0 0

2 N

E 9 E S D

C N

V C

3 / 1

0 N F

E 5 E S D

C N

V C
C

2 / 1
N

3 N
1

L _ C

8 7

L 1 G R R G R 1 1 1 2 2

3 R _ O U T

_ C

5 9 4

C N

V C

3 / 1

1 0 0 P

F E S D
E 1 2 E S D

E 1 0

B _ O

T C V B S _ O U T 1

6 2

C N

V C

3 / 1

2 0

V 1 G 3

E 1 5 E S D

C N

V C

3 / 1

3 0 0 P F

1 3

V 2

R G _ O U T

A 6 _ 0

E 1 6 E S D

C N

V C

3 / 1

4 0 0 P F

5 V

_ A

R 1

A 1 7 C 0 0 R 3

A 0 P

1 F

C A2

1 1 1 1

D A T A _ I I S B C L K _ I I S L R C K _ I I SM C M C L K _ D A C

DAT A_IIS BCLK_IIS LRCK_IIS


_ D A

U
1 2 3 4

2
8 7T L 6 C 5 D T R

S D A TAA O U S C L K A V C L R C L AK G N M C L KA O U

AOUT L AOUT R +
1

L 0

A U

2 H

C 1

A 0 0

E U

1 F

1 / 1 6 V

+ 1

C 0

A 0 U

E F

2 / 1 6 V

100N

R A 1 4 7 K C A O 4 U 7 A E T R + U F 9 / 1 V R 2 A 4 K G N D C R 2 4 A K 3 1 0 G C 7 A E F G 4 N R D A 9 2 A 6 0 N N D G N + C A E 5 4 7 U F / 1 6 V C A 2 . 7 G N D 8 N G 6 6 V C R A 8 2 K 2 C A 2 . 7 9 N 3 9 A 0 7 P F 1 2 3 4 U F 8 O U T+ 1V C 7 C 1 I N -O U T 6 2 1 I N + 2 I N 5- V C C2 I N + C 4 5 5 8 _ S O A 3 9 V C A 1 11 0 0 G P 8 N N D R A 1 1 5 K C A E 46 7 + U F / 1 8 R 3 K A 9 1 2 R A 1 1 5 K 1 C A E 47 7 + U F / 1

6 RV A 1 0 2 2 0 R

H L

6 RV A 7 2 2 0 R

H R

C A 1 0 3 9 0 P F R A 4 2 K 2

R A 5 4 7 K

F N D

O 4

T L + U

/ 1

3 K 6 V

Above is schematic diagram for audio & video Audio: CPU directly output IIS digital audio signals, and UA2-CS4334 change IIS signals into analog signals then which be amplified by 4558. Circuit resistance on the RA11 and RA1 are the feedback impedance, which together with input impedance ratio determines the size of magnification, and also determines the size of set-top box output volume. Video: R7-4K7 & R1-270R resistors are configured video DAC reference current on CPU configuration. With 4 video DAC, HI3560Q could be respectively configured in different combinations. DAC output converted analog video signals. CVBS and YPBPR signals will be amplified and output by FM6143 .

Spare Parts reference data

From left to right: operational amplifier LM833/4558 , voltage stablizing unit LM/AZ1117-ADJ, EEPROM AT24C64

From left to right: replacement chipset IMP809

ESD diode BAV99