Introduction to VLSI

The Manufacturing Process

Integrated Circuits

What will we learn today?

Basic

Process Concepts

Basic Concepts Detailed Flow Layout & DRC

Detailed

Process Flow

Layout

and Design Rules

CMOS Process Outline

Basic Process Flow

Lightly Doped Wafer Grow Field Oxide Define Wells Grow Gate Oxide Deposit Poly Gate Etch Gates Implant Source/Drain Deposit Isolation Oxide and Contacts Deposit Metal 1 Deposit Isolation Oxide and Via 1 Deposit Metal 2 5

What will we learn today?

Basic

Process Concepts

Basic Concepts Detailed Flow Layout & DRC

Detailed

Process Flow

Layout

and Design Rules

Detailed Process Flow

The Silicon Wafer

Lightly Doped Wafer

Smithsonian (2000)
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Field Oxide The LOCOS Process

Lightly Doped Wafer Grow Field Oxide

Photoresist
Nitride (Si3N4) SiO2 Oxide (FOX) Field

Active Area

Field Oxide The STI Process

Lightly Doped Wafer

The LOCOS Process has two problems:

Birds Beak makes it hard to make transistors close to each other. A parasitic MOSFET can turn on underneath the FOX.

Grow Field Oxide

Solution: Shallow Trench Isolation (STI) and Field Implants

Nitride (Si3N4) SiO2

Active Area

Active Area

Active Area

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Well Implantation
Lightly Doped Wafer

Grow Field Oxide

Well Implants

Cover wafer with thin layer of oxide. Implant wells through photolithographic Process. After implant we must Anneal to fix the covalent bonds, and Diffuse to get the wells to the depth we want.

Annealing: Heating up the wafer to fix covalent bonds. Done after every ion implantation or similar damaging step. Diffusion: Movement of dopants due to heating of the wafer. Usually this is unwanted, as it changes the implanted doping depth.

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Well Implantation Deep N-Wells

Lightly Doped Wafer

Grow Field Oxide

Well Implants

Can we change the body voltage of an nMOS transistor? Yes, but it costs a lot of area:

p (field implant)

N-well (n-)
P-sub (p-)

Isolated P-well (p) Deep N-well (n-)

p (field implant) P-well (p)

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Transistor Fabrication: VT Implant

Lightly Doped Wafer

Grow Field Oxide

The threshold voltage of a transistor is approximately: 2 qN 2

VTH VFB 2 f
s A

Well Implants

Cox

qQI Cox

Transistor Fabrication

So the first step is to implant QI. Random Dopant Fluctuations (RDF) cause a problematic distribution in VT between devices. Native Transistors are transistors that didnt go through this step (i.e. VT0 Depletion)
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Transistor Fabrication: Gate Oxide

Lightly Doped Wafer

Grow Field Oxide

Gate Oxide thickness (tox) is one of the most important device parameters. 45 nm technology has a 1.2 nm thick layer (about 5 atoms!). Gate oxide growth has to be done in super-clean conditions to eliminate traps and defects. New high-K materials extremely complicate this process.
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Well Implants

Transistor Fabrication

Transistor Fabrication: Gate Etch

Lightly Doped Wafer

Grow Field Oxide

Well Implants

Transistor Fabrication

Originally Aluminum was used as the gate material, then polysilicon, now metal again. The gate is the smallest dimension that is fabricated through photolithography. The oxide is self-aligned to the gate through the etching process.

p (field implant)
P-well (p) P-sub (p-)

p (field implant)

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Photolithography
Lightly Doped Wafer

Grow Field Oxide

Photolithographic resolution is set by D k1 n sin Therefore, to get better resolution, we could:

Use a smaller wavelength (today 193 nm). Possibilities are e-beam, extreme UV (13 nm). Use wet lithography (nwater=1.43) Use mask and layout techniques. Use nanoimprinting.

Well Implants

Transistor Fabrication

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Photolithography
Lightly Doped Wafer

Step and Scan

Grow Field Oxide

Well Implants

Transistor Fabrication

OPC

Phase Shift Masks

Kahng et. al., 1999 DAC 17

Transistor Fabrication: Tip Extension

Lightly Doped Wafer

Grow Field Oxide

Well Implants

Transistor Fabrication

For various reasons, we need a Lightly Doped Drain (LDD). But for source/drain resistance, we need a heavily doped area away from the channel. Therefore, a Tip or Spacer is formed:

p (field implant)

n implant n+

n implant n+ implant

p (field implant)

P-well (p) P-sub (p-)

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Contacts
Lightly Doped Wafer

Grow Field Oxide

Well Implants

Transistor Fabrication

A Silicide layer reduces contact resistance. A thick isolation oxide is grown. The bumpy oxide is planarized through CMP. Contacts are etched, lined and plugged. This is known as the Damascene Process.

Contacts

FOX
p (field implant)

n implant n+

n implant n+ implant

p (field implant)

P-well (p) P-sub (p-)

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Planarization

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Contacts

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Metal Layers

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Advanced Metallization

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Hillocking and Electromigration

Hillocking:
The development of small hills in the interconnect due to stress on the Aluminum. Can short between metal layers, crack SiO2, cause bumpiness. Adding Cu to Al helps reduce hillocking.

Electromigration:
Movement of Aluminum atoms due to high current densities that can eventually cause hillocks (shorts) or voids (opens). Proper design helps prevent electromigration. Cu interconnect is very efficient against electromigration.

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Antenna Effect

Charge is built up on interconnect layers during deposition. If enough charge is created, this can cause a high voltage to breakdown the thin gates.

m4 m3

100

2000

m2
m1 gate diff gate Dangerous: lots of m3; will probably accumulate lots of charge and then blow oxide
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diff

Safe: m3 is too short to accumulate very much charge; wont kill gate

Antenna Effect

Bridging or Antenna Diodes are used to eliminate the Antenna Effect.

m4 m3 m2 m1 gate

2000

diff psub Bridging keeps gate away from long metals until they drain through the diffusion

gate

ndiff

Node diodes are inactive during chip operation (reverse-biased p/n); let charge leak away harmlessly

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Layer Density
This etching step takes a lot longer (microloading)

resist metal ILD

High density Low density

Solution: Add dummy metal structures here to maintain minimum metal density

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What will we learn today?

Basic

Process Concepts

Basic Concepts Detailed Flow Layout & DRC

Detailed

Process Flow

Layout

and Design Rules

28

Layout and Design Rules

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Transistor Layout

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Design Rules

Interface between designer and process engineer

Guidelines for constructing process masks Unit dimension: Minimum line width
scalable design rules: lambda parameter absolute dimensions (micron rules)

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Layers in our Slides

Layer Color Yellow Green Green Red Representation

Well (p,n)
Active Area (n+,p+)

Select (p+,n+)
Polysilicon

Metal1
Metal2 Contact To Poly

Blue
Magenta Black

Contact To Diffusion
Via

Black
Black
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Transistor Layout

Transistor

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Design Rules

Intra-layer
Widths, spacing, area

Inter-layer
Enclosures, distances, extensions, overlaps

Special rules (sub-0.25m)

Antenna rules, density rules, (area)

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Intra-Layer Design Rules

Same Potential Well 10 Active 3 2 Select 3 Contact or Via Hole 2
Metal2 3

Different Potential 9 Polysilicon 2 Metal1 2 3

4

0 or 6

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Vias and Contacts

2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4

2 2

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Select Layer
2 3 1 3 3 2 Select

Substrate

Well

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CMOS Inverter Layout

GND In VD D

Out (a) Layout

A p-substrate n+ (b) Cross-Section along A-A n p+ Field Oxide

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Inverter Layout

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Actual Layout in Cadence

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Latchup

Thyristors created by parasitic BJT transistors can turn on and short VDD and GND. This requires power down at the least, and sometimes causes chip destruction. To eliminate some latchup, use lots of well/substrate contacts.

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Bulk Contacts

To ensure a constant body voltage across large areas, Bulk Contacts or Taps have to be added frequently.
N-well
P-select VDD
N-select

P-sub
VSS

N-select

pMOS

P-select

nMOS

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Basic Layout Planning

Choose global directions for routing layers

Adjacent levels should route perpendicular Example: m2 horizontal, m1 vertical

Position power lines first in top layer of metal Cluster together NMOS with NMOS and PMOS with PMOS Generally keep gate orientation the same Arrange transistors so that common sources/drains can be shared Arrange transistors so that common gates line up Limit lengths of diffusion and poly routing use metal Try to design/layout as little stuff as possible (use repetition/tools)

An Example Step 1

Choose global directions for routing layers Position power lines in top layer of metal

An Example Step 2

Cluster together NMOS with NMOS and PMOS with PMOS Generally keep gate orientation the same

An Example Step 3

Arrange transistors so that common sources/drains can be shared Give precedence to shared signals over shared vdd/ground Arrange transistors so that common gates line up

An Example Step 4

Connect everything up and convert to layout

Further Reading

J. Plummer Silicon VLSI Technology, 2000 especially Chapter 2 J. Rabaey, Digital Integrated Circuits 2003, Chapters 2.2-2.3 C. Hu, Modern Semiconductor Devices for Integrated Circuits, 2010, Chapter 3 http://www.eecs.berkeley.edu/~hu/Book-Chapters-and-Lecture-Slides-download.html E. Alon, Berkeley EE-141, Lectures 2,4 (Fall 2009)
http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_f09/

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