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Universal Asynchronous Receiver/Transmitter

Universal Asynchronous Receiver/Transmitter UART ECEn 224 20 UART © 2003-2008 Page 1 BYU

UART

ECEn 224

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© 2003-2008

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Why use a UART?

• A UART may be used when:

– High speed is not required

– An inexpensive communication link between two devices is required

• UART communication is very cheap

– Single wire for each direction (plus ground wire) • Asynchronous because no clock signal is transmitted

– Relatively simple hardware

• PC devices such as mice and modems used to often use UARTs for communication to the PC

as mice and modems used to often use UARTs for communication to the PC ECEn 224

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UART Uses

• PC serial port is a UART!

– Serializes data to be sent over serial cable

– De-serializes received data

Serial

Serial Serial Cable Port Port
Serial
Serial
Cable
Port
Port
Serial Cable Device
Serial
Cable
Device
data Serial Serial Serial Cable Port Port Serial Cable Device ECEn 224 20 UART © 2003-2008

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UART Uses

• Communication between distant computers

– Serializes data to be sent to modem

– De-serializes data received from modem

Serial Cable Phone Line Phone Modem Serial Line Cable Modem ECEn 224 20 UART ©
Serial
Cable
Phone
Line
Phone
Modem
Serial
Line
Cable
Modem
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UART Uses

• Used to be commonly used for internet access

Phone Line Internet Internet Phone Line Server
Phone
Line
Internet Internet
Phone
Line
Server
Serial Cable
Serial
Cable

Modem

Phone Line Internet Internet Phone Line Server Serial Cable Modem ECEn 224 20 UART © 2003-2008

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UART Uses

• Used to be used for mainframe access

– A mainframe could have dozens of serial ports

Mainframe Serial Cables Terminal Terminal Terminal Terminal
Mainframe
Serial
Cables
Terminal
Terminal
Terminal
Terminal
ports Mainframe Serial Cables Terminal Terminal Terminal Terminal ECEn 224 20 UART © 2003-2008 Page 6

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UART Uses

• Becoming much less common

• Largely been replaced by faster, more sophisticated interfaces

– PCs: USB (peripherals), Ethernet (networking)

– Chip to chip: I 2 C, SPI

• Still used today when simple low speed communication is needed

SPI • Still used today when simple low speed communication is needed ECEn 224 20 UART

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UART Functions

• Transmitter

– Convert from parallel to serial

– Add start and stop delineators (bits)

– Add parity bit

• Receiver

– Convert from serial to parallel

– Remove start and stop delineators (bits)

– Check and remove parity bit

start and stop delineators (bits) – Check and remove parity bit ECEn 224 20 UART ©

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UART Character Transmission

• Below is a timing diagram for the transmission of a single byte

• Uses a single wire for transmission

• Each block represents a bit that can be a mark (logic ‘1) or space (logic ‘0’)

1 bit time

mark space Time
mark
space
Time
(logic ‘1) or space (logic ‘0’) 1 bit time mark space Time ECEn 224 20 UART

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UART Character Transmission

• Each bit has a fixed time duration determined by the transmission rate

• Example: a 1200 bps (bits per second) UART will have a 1/1200 s or about 833.3 µs bit duration

1 bit time

) UART will have a 1/1200 s or about 833.3 µs bit duration 1 bit time
) UART will have a 1/1200 s or about 833.3 µs bit duration 1 bit time

ECEn 224

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UART Character Transmission

• The start bit marks the beginning of a new word

• When detected, the receiver synchronizes with the new data stream

Start Bit

detected, the receiver synchronizes with the new data stream Start Bit ECEn 224 20 UART ©
detected, the receiver synchronizes with the new data stream Start Bit ECEn 224 20 UART ©

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UART Character Transmission

• Next follows the data bits (7 or 8)

• The least significant bit is sent first

7 Data Bits

bits (7 or 8) • The least significant bit is sent first 7 Data Bits ECEn
bits (7 or 8) • The least significant bit is sent first 7 Data Bits ECEn
bits (7 or 8) • The least significant bit is sent first 7 Data Bits ECEn

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UART Character Transmission

• The parity bit is added to make the number of 1’s even (even parity) or odd (odd parity)

• This bit can be used by the receiver to check for transmission errors

• Use of parity bits is optional

Parity Bit

for transmission errors • Use of parity bits is optional Parity Bit ECEn 224 20 UART
for transmission errors • Use of parity bits is optional Parity Bit ECEn 224 20 UART

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UART Character Transmission

• The stop bit marks the end of transmission

• Receiver checks to make sure it is ‘1’

• Separates one word from the start bit of the next word

Stop Bit

• Separates one word from the start bit of the next word Stop Bit ECEn 224
• Separates one word from the start bit of the next word Stop Bit ECEn 224

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UART Character Transmission

• In the configuration shown, it takes 10 bits to send 7 bits of data

• Transmission efficiency is 7/10, or 70%

Start bit

7 data bits

Parity bit

Stop bit

or 70% Start bit 7 data bits P a r i t y b i t
or 70% Start bit 7 data bits P a r i t y b i t

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UART Transmission Example

• Send the ASCII letter ‘W’ (1010111)

Parity bit

(odd parity)

Line idling

Start bit

Stop bit

   
   
   

1

1

1

0

1

0

1

0

 

Mark

Space

1 1 1 0 1 0 1 0   Mark Space Line idling again 7 data

Line idling again

7 data bits – Least significant bit first

Space Line idling again 7 data bits – Least significant bit first ECEn 224 20 UART

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UART Character Reception

Start bit says a character is coming, receiver resets its timers

Receiver should sample in middle of bits Mark Space
Receiver should sample in middle of bits
Mark
Space

Receiver uses a timer (counter) to time when it samples. Transmission rate (i.e., bit duration) must be known!

when it samples. Transmission rate (i.e., bit duration) must be known! ECEn 224 20 UART ©

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UART Character Reception

If receiver samples too quickly, see what happens…

If receiver samples too quickly, see what happens…   Mark            
 

Mark

 
               

Space

                  Space ECEn 224 20 UART © 2003-2008

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UART Character Reception

If receiver samples too slowly, see what happens…

If receiver samples too slowly, see what happens…   Mark            
 

Mark

 
                   

Space

Receiver resynchronizes on every start bit. Only has to be accurate enough to read 9 bits.

on every start bit. Only has to be accurate enough to read 9 bits. ECEn 224

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UART Character Reception

• Receiver also verifies that stop bit is ‘1’

– If not, reports “framing error” to host system

• New start bit can appear immediately after stop bit

– Receiver will resynchronize on each start bit

after stop bit – Receiver will resynchronize on each start bit ECEn 224 20 UART ©

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UART Options

• UARTs usually have programmable options:

Data: 7 or 8 bits

Parity: even, odd, none, mark, space

Stop bits: 1, 1.5, 2

Baud rate: 300, 1200, 2400, 4800, 9600, 19.2k, 38.4k, 57.6k, 115.2k…

rate: 300, 1200, 2400, 4800, 9600, 19.2k, 38.4k, 57.6k, 115.2k… ECEn 224 20 UART © 2003-2008

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UART Options

• Baud Rate

– The “symbol rate” of the transmission system

– For a UART, same as the number of bits per second (bps)

– Each bit is 1/(rate) seconds wide

• Example:

Not the data throughput rate!

seconds wide • Example: Not the data throughput rate! – 9600 baud 9600 Hz – 9600

– 9600 baud 9600 Hz

– 9600 bits per second (bps)

– Each bit is 1/(9600 Hz) 104.17 µs long

per second (bps) – Each bit is 1/(9600 Hz) ≈ 104.17 µs long ECEn 224 20

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UART Throughput

• Data Throughput Example

– Assume 19200 baud, 8 data bits, no parity, 1 stop bit

• 19200 baud 19.2 kbps

• 1 start bit + 8 data bits + 1 stop bit 10 bits

– It takes 10 bits to send 8 bits (1 byte) of data

– 19.2 kbps • 8/10 = 15.36 kbps

• How many KB (kilobytes) per second is this?

– 1 byte = 8 bits

– 1 KB = 1,024 bytes

– So, 1 KB = 1,024 bytes • 8 bits/byte = 8,192 bits

– Finally, 15,360 bps • 1 KB / 8,192 bits = 1.875 KB/s

8,192 bits – Finally, 15,360 bps • 1 KB / 8,192 bits = 1.875 KB/s ECEn

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A Note on Signaling

• RS232 is the most common UART standard

– Used by PC serial ports

• RS232 does NOT use positive logic

– Logic 1 is any signal from -25V to -3V

– Logic 0 is any signal from +3V to 25V

– The range -3V to +3V is a transition region that is not assigned to a logic level

• On an oscilloscope, an RS232 waveform looks inverted from the actual data values transmitted

RS232 waveform looks inverted from the actual data values transmitted ECEn 224 20 UART © 2003-2008

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Let’s Design a UART Transmitter!

Specifications

• Parameters: 300 baud, 7 data bits, 1 stop bit, even or odd parity

• Inputs:

Din[6:0]: 7-bit parallel data input

Send: Instructs transmitter to initiate a transmission

ParitySelect: Selects even parity (ParitySelect=0) or odd parity

(ParitySelect=1)

• Outputs:

Dout: Serial data output

Busy: Tells the host it’s busy sending a character

data output – Busy : Tells the host it’s busy sending a character ECEn 224 20

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System Diagram

To host

system

System Diagram To host system UART Transmitter Dout Send Busy ParitySelect Din 7 To serial cable

UART

Transmitter

Dout

UART Transmitter Dout

Send

Diagram To host system UART Transmitter Dout Send Busy ParitySelect Din 7 To serial cable ECEn

Busy

To host system UART Transmitter Dout Send Busy ParitySelect Din 7 To serial cable ECEn 224

ParitySelect

Din 7

Din

7

UART Transmitter Dout Send Busy ParitySelect Din 7 To serial cable ECEn 224 20 UART ©

To serial

cable

Transmitter Dout Send Busy ParitySelect Din 7 To serial cable ECEn 224 20 UART © 2003-2008

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Transmitter/System Handshaking

• System asserts Send and holds it high when it wants to send a byte

• UART asserts Busy signal in response

• When UART has finished transfer, UART de-asserts Busy signal

• System de-asserts Send signal

Send Busy ECEn 224 20 UART © 2003-2008 Page 27 BYU
Send
Busy
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Transmitter Block Diagram

NextBit 300 HZ ResetTimer Timer Count10 Transmitter Mod10 Increment State Counter ResetCounter Machine Shift
NextBit
300 HZ
ResetTimer
Timer
Count10
Transmitter
Mod10
Increment
State
Counter
ResetCounter
Machine
Shift
Load
Parity
Generator
Shift
ParityBit
Register

To host

system

Generator Shift ParityBit Register To host system Send Busy ParitySelect Dout To serial cable Din 7

Send

Generator Shift ParityBit Register To host system Send Busy ParitySelect Dout To serial cable Din 7

Busy

Shift ParityBit Register To host system Send Busy ParitySelect Dout To serial cable Din 7 ECEn

ParitySelect

ParityBit Register To host system Send Busy ParitySelect Dout To serial cable Din 7 ECEn 224

Dout

Register To host system Send Busy ParitySelect Dout To serial cable Din 7 ECEn 224 20

To serial

cable

Din 7
Din
7
To host system Send Busy ParitySelect Dout To serial cable Din 7 ECEn 224 20 UART

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The Timing Generator

300 Hz

Timer

NextBit

SystemClock

The Timing Generator 300 Hz Timer NextBit SystemClock ResetTimer • Divides system clock down to 300

ResetTimer

Generator 300 Hz Timer NextBit SystemClock ResetTimer • Divides system clock down to 300 Hz •
Generator 300 Hz Timer NextBit SystemClock ResetTimer • Divides system clock down to 300 Hz •

• Divides system clock down to 300 Hz

• Output is NextBit signal to state machine

– Goes high for one system clock cycle 300 times a second

• Simply a Mod f clk /300 resetable counter where NextBit is the rollover signal

• More sophisticated UARTs have programmable timing generators for different baud rates

UARTs have programmable timing generators for different baud rates ECEn 224 20 UART © 2003-2008 Page

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The Mod10 Counter

Count10

Mod10

Counter

The Mod10 Counter Count10 Mod10 Counter Increment SystemClock ResetCounter • Resets to 0 on command from

Increment

SystemClock

The Mod10 Counter Count10 Mod10 Counter Increment SystemClock ResetCounter • Resets to 0 on command from
The Mod10 Counter Count10 Mod10 Counter Increment SystemClock ResetCounter • Resets to 0 on command from

ResetCounter

Count10 Mod10 Counter Increment SystemClock ResetCounter • Resets to 0 on command from state machine •

• Resets to 0 on command from state machine

• Increments on command from state machine

• Counts from 0 to 9, then rolls over to 0

• Tells state machine when it’s going to roll over from 9 back to 0 (signal Count10)

when it’s going to roll over from 9 back to 0 (signal Count10 ) ECEn 224

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Mod10 Counter in Verilog

module mod10 (clk, reset, increment, count10); input clk, reset, increment; output reg count10;

wire [3:0] ns, q, qPlus1;

assign qPlus1 = (q == 9) ? 0 : q+1;

assign ns = (reset)

(increment) ? qPlus1 :

?

0

:

q;

regn #(4) R0(clk, ns, q);

// Input forming logic // “” // “” // “”

// 4-bit register

assign count10 = increment & (q == 9); // Rollover logic

endmodule

This could also be written using behavior Verilog (an always block)

This could also be written using behavior Verilog (an always block) ECEn 224 20 UART ©

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The Parity Generator

ParitySelect

Parity

Generator

The Parity Generator ParitySelect Parity Generator Din 7 ParityBit • Combinational circuit • Generates ParityBit

Din

7

The Parity Generator ParitySelect Parity Generator Din 7 ParityBit • Combinational circuit • Generates ParityBit
The Parity Generator ParitySelect Parity Generator Din 7 ParityBit • Combinational circuit • Generates ParityBit

ParityBit

Generator ParitySelect Parity Generator Din 7 ParityBit • Combinational circuit • Generates ParityBit

• Combinational circuit

• Generates ParityBit according to value of Din[6:0] and ParitySelect input

ParityBit according to value of Din[6:0] and ParitySelect input ECEn 224 20 UART © 2003-2008 Page

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The Parity Generator

• The value of ParityBit is the bit needed to make the number of 1’s even (if even parity) or odd (if odd parity)

 

Even Parity (ParitySelect = 0)

Odd Parity (ParitySelect = 1)

Even number of ‘1’s

ParityBit = 0

ParityBit = 1

Odd number of ‘1’s

ParityBit = 1

ParityBit = 0

= 1 Odd number of ‘1’s ParityBit = 1 ParityBit = 0 ECEn 224 20 UART

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An 8-Bit Parity Generator

Din[0]

Din[1]

Din[2]

Din[3]

Din[4]

Din[5]

Din[6]

Din[7]

Din[0] Din[1] Din[2] Din[3] Din[4] Din[5] Din[6] Din[7] Odd/Even# ParityBit Will be ‘0’ if Din has
Din[0] Din[1] Din[2] Din[3] Din[4] Din[5] Din[6] Din[7] Odd/Even# ParityBit Will be ‘0’ if Din has

Odd/Even#

Din[1] Din[2] Din[3] Din[4] Din[5] Din[6] Din[7] Odd/Even# ParityBit Will be ‘0’ if Din has even

ParityBit

Will be ‘0’ if Din has even number of 1’s, ‘1’ if odd number.

For 7-bit parity, tie Din[7] to a ‘0’

‘1’ if odd number. For 7-bit parity, tie Din[7] to a ‘0’ ECEn 224 20 UART

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7-bit Parity Generator in Verilog

module parity_gen (data, oddeven, parity); input [6:0] data; input oddeven; output parity;

assign parity = (^data) ^ oddeven; endmodule

Reduction XOR operator

assign parity = (^data) ^ oddeven; endmodule Reduction XOR operator ECEn 224 20 UART © 2003-2008

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The Shift Register

• Standard Parallel-In/Serial-Out (PISO) shift register

• Has 4 operations:

– Do nothing

– Load parallel data from Din

– Shift right

– Reset

Do nothing – Load parallel data from Din – Shift right – Reset ECEn 224 20

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The Shift Register

• Make it a 9-bit register

• When it loads:

– Have it load ‘0’ for the start bit on the right (LSB)

– Have it load 7 data bits in the middle

– Have it load the parity bit on the left (MSB)

• When it shifts:

– Have it shift ‘1’ into the left so a stop bit is sent at the end

• When it resets:

– Have it load all 1’s so that its default output is a ‘1’ (line idle value)

‘1’

its default output is a ‘1’ (line idle value) ‘1’ ‘0’ P D 6 D 5
its default output is a ‘1’ (line idle value) ‘1’ ‘0’ P D 6 D 5
its default output is a ‘1’ (line idle value) ‘1’ ‘0’ P D 6 D 5
its default output is a ‘1’ (line idle value) ‘1’ ‘0’ P D 6 D 5
its default output is a ‘1’ (line idle value) ‘1’ ‘0’ P D 6 D 5
its default output is a ‘1’ (line idle value) ‘1’ ‘0’ P D 6 D 5
its default output is a ‘1’ (line idle value) ‘1’ ‘0’ P D 6 D 5
its default output is a ‘1’ (line idle value) ‘1’ ‘0’ P D 6 D 5
its default output is a ‘1’ (line idle value) ‘1’ ‘0’ P D 6 D 5

‘0’

output is a ‘1’ (line idle value) ‘1’ ‘0’ P D 6 D 5 D 4

P

D

6

D

5

D

4

D

3

D

2

D

1

D

0

‘0’

D 3 D 2 D 1 D 0 ‘0’ Shift Register ECEn 224 Dout 20 UART
D 3 D 2 D 1 D 0 ‘0’ Shift Register ECEn 224 Dout 20 UART

Shift Register

ECEn 224

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9-bit Shift Register Module

module ShiftReg (clk, rst, din, parity, load, shift, dout); input clk, rst, parity, load, shift; input [6:0] din; output dout; wire [8:0] ns, q;

assign ns =

rst

? 9'b111111111 :

load

? {parity, din, 1'b0} :

shift ? {1'b1, q[8:1]} :

q; reg #(9) R0(clk, ns, q); assign dout = q[0]; endmodule

q[8:1]} : q; reg #(9) R0(clk, ns, q); assign dout = q[0]; endmodule ECEn 224 20

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Transmitter FSM

Send’

Reset

Send Idle Send’ Load Wait Busy Count NextBit Count10 Shift
Send
Idle
Send’
Load
Wait
Busy
Count
NextBit
Count10
Shift

Load

Busy

ResetCounter

ResetTimer

Send

NextBit’

Count10’

Shift

Increment

Busy

ResetTimer Send NextBit’ Count10’ Shift Increment Busy ECEn 224 Be sure to choose state encodings and

ECEn 224

Be sure to choose state encodings and use logic minimization that ensures Busy signal will have no hazards!

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The Receiver

• Left for you as a homework problem!

• Receiver Issues:

1. How to sample the middle of bit periods?

2. How do you check if parity is correct?

3. What do you do on a framing error?

4. What do you do on a parity error?

5. Handshaking with rest of system?

What do you do on a parity error? 5. Handshaking with rest of system? ECEn 224

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