MOS TRANSISTOR 1. What is meant Photolithography? 2. What is photoresist? 3. Describe the process of ion implantation. 4. What is defect density?

5. What is annealing? 6. What are the different integration levels? The different integration levels are i. SSI(Small-Scale Integration) ii. MSI(Medium-Scale Integration) iii. LSI(Large- Scale Integration) iv. VLSI(Very Large-Scale Integration) v. ULSI(Ultra Large-scale Integration) vi. GSI(Giga-Scale Integration) 7. Define yield? (Xc nh sn lng) 8. What is SSI and MSI? 9. What is LSI and GSI? 10. What is VLSI and ULSI? 11. What are the pattern layers needed for nFET masking sequence? 12. What are the pattern layers needed for pFET masking sequence? 13. Where we introduce length metric lambda? 14. Define design rule check (DRC). 15. What are the sequences we used to create the pattern? 16. Describe the term reticle. 17. What is the use of passivation mask? 18. State Moores law. 19. What are the classification of design rules? 20.What is minimum feature and minimum spacing? 21.What is surround rule and exact size? 22.What is process specific rules ? 23. Define design rules(DRs). 24. What is meant by Reactive Ion Etching? 25. Give the advantages of IC? 26. Give the variety of Integrated Circuits? 27. Give the basic process for IC fabrication. i. Silicon wafer Preparation ii. Epitaxial Growth iii.Oxidation iv.Photolithography v.Diffusion vi.Ion Implantation vii.Isolation technique viii.Metallization ix.Assembly processing & Packaging

MOSFET TRANSISTOR 1. What are the materials we use to built the MOSFET? 2. Define surface charge, Qs. 3. Define body bias voltage. The body bias voltage is expressed as: VSB=VS-VB 4. How to express the device transconductance and process transconductance. The device transconductance is expressed as: K= k(W/L) [units of A/V2] The process transconductance is expressed as: K= Cox [units of A/V2] 5. Define mobility ratio.
k n n .Cox n = = =r k p p .Cox p

6.How to measure the effective channel length? 7. Write the current equation for cut off, triode and saturation region. For cut off region, ID=0 For triode region ID= Kn[2(VGS-VTn)VDS-V2DS]2 For saturation region, ID = Kn(VGS-VTn)2[1+O(VDS-Vsat)]2 8. How to express the MOS capacitors in terms of gate capacitance? The MOS capacitors can be expressed in terms of gate capacitance is CG=Cox WL Where area has been taken to be A=WL 9. Write the capacitance equation for three regions? For cut off region, CGB=CG, CGS,CGD=0. For triode region, CGS= (2/3) CG , CGD=0, CGB=0 For saturation region, CGS , CGD= (1/2) CG, CGB=0 10. How we find the threshold voltage variation in transistor? The threshold voltage of transistor varies according to Where VT0n is the zero body bias threshold voltage and is called the body bias coefficient. 11.What is the possible modification to change the saturation current? The possible modification to change the saturation current is I D,sat = Kn (VGS-VTN)T 12. What is the total capacitance for n-type source /drain? For n-type source or drain the total capacitance is sum of bottom and sidewall contributions in the form of Cn = Cbot + Csw 13. What are the different regions we can define in MOSFET depend upon voltages? Cutoff , Vds=0 For triode region, Vds<Vgs-Vt For saturation region, Vds>Vgs-Vt and Vgd<Vt 14. Define threshold voltage V(t).

Threshold voltage can be defined as voltage Vgs(gate to source voltage) applied below which Ids drop to zero. Vt=V t-mos + Vf band 15. What is body effect? Threshold voltage Vt is not constant with respect to voltage difference between substrate and source of MOS transistor. This is known as body effect and it is otherwise known as substrate bias effect. 16. What are the parameters in threshold voltage? The parameters are: i. Gate conductor material. ii. Gate insulation material. iii. Gate insulator thickness-Channel doping. iv. Impurities at the silicon- Insulator surface. v. Voltage between source and substrate. 17. What is Enhancement mode transistor and Depletion mode transistor? Enhancement mode transistor is the device that is normally cut-off with zero gate bias. Depletion mode Device is the device that conduct with zero gate bias. 28. When the channel is said to be pinched off? If a large Vds is applied this voltage with deplete the Inversion layer .This Voltage effectively pinches off the channel near the drain.