Capacitances

Alpana Agarwal
Assistant Professor
Email: alpana@thapar.edu, alpana.tiet@gmail.com

Electronics & Communication Engineering Department

Thapar University, Patiala

Capacitance
Any two conductors separated by an insulator have capacitance Essential for transient and ac responses Most of them are distributed & not lumped On-chip capacitances, used for hand estimation Gate to channel capacitor is very important
Creates channel charge necessary for operation

Source and drain have capacitance to body

Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion

More parasitic capacitances

10/13/2007

Alpana Agarwal, Thapar University

CMOS Inverter: Dynamic

Transient, or dynamic, response determines the maximum speed at which a device can be operated. VDD

Todays focus

Vout = 0 Rn CL

tpHL = f(Rn, CL)

Vin = V DD
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Covered earlier
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Sources of Capacitance
Vin Vout CL Vout2

M2

CG4 CDB2 Vout Cw CDB1 CG3

M3 M4

Vin

Vout2

CGD12
M1

intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance
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Alpana Agarwal, Thapar University

MOS Intrinsic Capacitances

Structure capacitances Channel capacitances Depletion regions of the reversebiased pn-junctions of the drain and source

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MOS Structure Capacitances

lateral diffusion Source n+ Poly Gate LD Ldrawn tox n+ Leff n+ LD Drain W n+

Top view

Overlap capacitance (linear) CGSO = CGDO = Cox LD W = Co W

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MOS Channel Capacitances

The gate-to-bulk capacitance depends upon the operating region and the terminal voltages

CGS = CGCS + CGSO

VGS

G
+

CGD = CGCD + CGDO

D

S
-

n+

n+

n channel

CGB = CGCB
p substrate

depletion region

B
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Alpana Agarwal, Thapar University

Average Distribution of Channel Capacitance

Operation Region Cutoff Resistive Saturation CGCB CoxWL 0 0 CGCS 0 CoxWL/2 (2/3)CoxWL CGCD 0 CoxWL/2 0 CGC CoxWL CoxWL (2/3)CoxWL CG CoxWL + 2CoW CoxWL + 2CoW (2/3)CoxWL + 2CoW

Channel capacitance components are nonlinear and vary with operating voltage Most important regions are cutoff and saturation since that is where the device spends most of its time
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Alpana Agarwal, Thapar University

MOS Diffusion Capacitances

The junction (or diffusion) capacitance is from the reversebiased source-body and drain-body pn-junctions. G
VGS +

S
-

n+

n+

n channel

p substrate

depletion region

CSB = CSdiff
B
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CDB = CDdiff

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Source Junction View

channel-stop implant (NA+) W

source bottom plate (ND) channel side walls substrate (NA)

junction depth

xj

LSource Cdiff = Cbp + Csw = Cj AREA + Cjsw PERIMETER = Cj LSource W + Cjsw (2LSource + W)
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Review: Reverse Bias Diode

+ VD All diodes in MOS digital circuits are reverse biased; the dynamic response of the diode is determined by depletionregion charge or junction capacitance Cj = Cj0/((1 VD)/0)m where Cj0 is the capacitance under zero-bias conditions (a function of physical parameters), 0 is the built-in potential (a function of physical parameters and temperature) and m is the grading coefficient
m = for an abrupt junction (transition from n to p-material is ins tantaneous) m = 1/3 for a linear (or graded) junction (transition is gradual)

Nonlinear dependence (that decreases with increasing reverse bias)

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MOS Capacitance Model

CGS = CGCS + CGSO CGS S CSB CSB = CSdiff B CGB = CGCB
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CGD = CGCD + CGDO CGD D CGB CDB CDB = CDdiff

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Transistor Capacitance Values for 0.25

Example: For an NMOS with L = 0.24 m, W = 0.36 m, Ldrain = Lsource = 0.625 m CGSO = CGDO = Cox LD W = Co W = CGC = Cox WL = so Cgate_cap = CoxWL + 2CoW = Cbp = Cj LSource W = Csw = Cjsw (2LSource + W) = so Cdiffusion_cap =
Cox (fF/m2) NMOS PMOS
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Co (fF/m) 0.31 0.27

Cj (fF/m2) 2 1.9

mj 0.5 0.48

b (V) 0.9 0.9

Cjsw (fF/m) 0.28 0.22

mjsw 0.44 0.32

bsw
(V)

6 6

0.9 0.9
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Alpana Agarwal, Thapar University

Transistor Capacitance Values for 0.25

Example: For an NMOS with L = 0.24 m, W = 0.36 m, Ldrain = Lsource = 0.625 m CGSO = CGDO = Cox LD W = Co W = 0.11 fF CGC = Cox WL = so Cgate_cap 0.52 fF = CoxWL + 2CoW = 0.45 fF 0.45 fF 0.74 fF

Cbp = Cj LSource W = so Cdiffusion_cap =

Cox (fF/m2) NMOS PMOS
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Csw = Cjsw (2LSource + W) = 0.90 fF

Cj (fF/m2) 2 1.9

Co (fF/m) 0.31 0.27

mj 0.5 0.48

b (V) 0.9 0.9

Cjsw (fF/m) 0.28 0.22

mjsw 0.44 0.32

bsw
(V)

6 6

0.9 0.9
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Alpana Agarwal, Thapar University

Review: Sources of Capacitance

Vin Vout CL CG4
M4

Vout2

M2

Vin

CGD12 pdrain
ndrain

CDB2 CDB1

Vout Cw
M3

Vout2

M1

CG3

intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance
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Extrinsic (Fan-Out) Capacitance (FanThe extrinsic, or fan-out, capacitance is the total gate capacitance of the loading gates M3 and M4. Cfan-out = Cgate (NMOS) + Cgate (PMOS) = (CGSOn+ CGDOn+ WnLnCox) + (CGSOp+ CGDOp+ WpLpCox) Simplification of the actual situation
Assumes all the components of Cgate are between Vout and GN D (or VDD) Assumes the channel capacitances of the loading gates are c onstant

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Layout of Two Chained Inverters

VDD

PMOS 1.125/0.25
1.2m =2 In Out Metal1

Polysilicon

0.125
NMOS 0.375/0.25
GND

0.5

W/L NMOS PMOS

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AD (m2) 0.3 0.7

PD (m) 1.875 2.375

AS (m2) 0.3 0.7

PS (m) 1.875 2.375

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0.375/0.25 1.125/0.25

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Components of CL (0.25 m)
Expression C Term CGD1 CGD2 CDB1 CDB2 CG3 CG4 Cw CL 2 Con Wn 2 Cop Wp KeqbpnADnCj + KeqswnPDnCjsw KeqbppADpCj + KeqswpPDpCjsw (2 Con)Wn + CoxWnLn (2 Cop)Wp + CoxWpLp from extraction Value (fF) HL 0.23 0.61 0.66 1.5 0.76 2.28 0.12 6.1 Value (fF) LH 0.23 0.61 0.90 1.15 0.76 2.28 0.12 6.0

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Wiring Capacitance
The wiring capacitance depends upon the length and width of the connecting wires and is a funct ion of the fan-out from the driving gate and the number of fan-out gates. Wiring capacitance is growing in importance wit h the scaling of technology.

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Parallel Plate Wiring Capacitance

current flow L electrical field lines W H tdi dielectric (SiO2) substrate permittivity constant (SiO2= 3.9)
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Cpp = (di/tdi) WL
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Permittivity Values of Some Dielectr ics

Material Free space Teflon AF Aromatic thermosets (SiLK) Polyimides (organic) Fluorosilicate glass (FSG) Silicon dioxide Glass epoxy (PCBs) Silicon nitride Alumina (package) Silicon di 1 2.1 2.6 2.8 3.1 3.4 3.2 4.0 3.9 4.5 5 7.5 9.5 11.7

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Sources of Interwire Capacitance

Cwire = Cpp + Cfringe + Cinterwire = (di/tdi)WL + (2di)/log(tdi/H) + (di/tdi)HL

fringe interwire pp

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Impact of Interwire Capacitance

(from [Bakoglu89])
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Insights
For W/H < 1.5, the fringe component dominates the paralle l-plate component. Fringing capacitance can increase the ov erall capacitance by a factor of 10 or more. When W < 1.75H interwire capacitance starts to dominate Interwire capacitance is more pronounced for wires in the hi gher interconnect layers (further from the substrate) Rules of thumb
Never run wires in diffusion Use poly only for short runs Shorter wires lower R and C Thinner wires lower C but higher R

Wire delay nearly proportional to L2

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Wiring Capacitances
Field Poly Al1 Al2 Al3 Al4 Al5 88 54 30 40 13 25 8.9 18 6.5 14 5.2 12 41 47 15 27 9.4 19 6.8 15 5.4 12 57 54 17 29 10 20 7 15 5.4 12 36 45 15 27 8.9 18 6.6 14 41 49 15 27 9.1 19 35 45 14 27 38 52 Active Poly Al1 Al2 Al3 Al4

pp in fringe in aF/m

aF/m2

Poly Interwire Cap

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Al1 95

Al2 85

Al3 85

Al4 85

Al5 115
25

40

per unit wire length in aF/m for minimally-spaced wires Alpana Agarwal, Thapar University

Dealing with Capacitance

Low capacitance (low-k) dielectrics (insulators) such as polymide or even air instead of SiO2
family of materials that are low-k dielectrics must also be suitable thermally and mechanically and compatible with (copper) interconnect

Copper interconnect allows wires to be thinner without increasing their resistance, thereby de creasing interwire capacitance SOI (silicon on insulator) to reduce junction ca pacitance

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Gate Capacitance
Approximate channel as connected to source Cgs = oxWL/tox = CoxWL = CpermicronW Cpermicron is typically about 2 fF/m

polysilicon gate W tox n+ L p-type body n+ SiO2 gate oxide (good insulator, ox = 3.90)

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Diffusion Capacitance
Csb, Cdb Undesirable, called parasitic capacitance Capacitance depends on area and perimeter
Use small diffusion nodes Comparable to Cg for contacted diff Cg for uncontacted Varies with process

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Questions, if any?