SUBMITTED BY:

Semiconductor Technologies
VEDANT
VLSI DESIGN EDUCATION AND TRAINING LUCKNOW CENTRE

To Whom It May Concern This is to certify that Names have successfully completed their project on:

VHDL code for VMC in VHDL

With all its functionalities during the winter training course from Semiconductor Technologies, Vedant their work was authentic and conduct was diligent & sincere. The project satisfies the norms of the company and was developed under the guidance of Ms. Anupam Maurya & Mr. Amit Chandra. Certificate is awaited

CERTIFIED BY:

Ms. Anupam Maurya

Mr.Sachin Kr. Kanodia

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(Project Guide)

(Head)

ACKNOWLEDGEMENT
No academic endeavor can be single handedly accomplished. This work is no exception. At the outset, we would like to record our gratitude to Mr. Sachin Kr. Kanodia for initiating us into this training. We sincerely acknowledge our thanks to our project guide Ms. Anupam Maurya & Mr. Amit Chandra for their valuable suggestions and time to time consultation. Last, but not the least, we would like to thank all the staff of VLSI Design Department, Semiconductor Laboratory (SCL), Vedant, Lucknow especially Ms. Charu Agarwal for their kind cooperation and assistance during our training period.

PREFACE
The evolution of Very large scale integration (VLSI) technology has developed to the point where millions of transistors can be integrated on a single die or chip where integrated circuits once filled the role of subsystem component partitioned at analog-digital boundaries. They now integrate complete systems on a chip by combining both analog-digital functions. Complementary metal oxide semiconductors technology has been the mainstay in mixed signal implementations because it provides density and power savings on the digital side, and a good mix of components for analog design. Due in part to the regularity and granularity of digital circuit computer aided design (CAD) methodologies have been very successful in automating the design of digital systems given a behavioral description of the function desired. Such is not the case for analog circuit design. Analog design still requires a hands on design approach in general. Moreover many of the design techniques used for discrete circuits are not applicable to the design of analog /mixed signal VLSI circuits. It is necessary to examine closely the design
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process of analog circuit and to identify those principles that will increase design productivity and the designers chances for success.

CONTENT

Page no.

SEMICONDUCTOR TECHNOLOGIES VEDANT INTRODUCTION TO VLSI INTRODUCTION TO VHDL IEEE LIBRARIES INTRODUCTION TO FIR VHDL CODE SYNTHESIS REPORT BIBLIOGRAPHY

06 08 09 12 13 14 15 24 71

SEMICONDUCTOR TECHNOLOGIESVEDANT
AN ISO 9001:2000 CERTIFIED INSTITUTION

Semiconductor Technologies has always been in sync with the future. It has understood and appreciated the needs of India, its people and its ever-growing industry. Over the last six 20 years tell the saga of VEDANT contribution in leading the national effort in the vital areas of microelectronics.

M/s Semiconductor Technologies-VEDANT is Indias premier VLSI Design & Embedded System Design organization since 2002. While VEDANT is Indias pioneer in the field of VLSI Design & Embedded System Design and Testing. VEDANT is providing Education & Training on VLSI Design & Embedded System Design through state-of-theart lab facilities, equipped with the Industry Standard tools.
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VLSI Design / Embedded Systems Design Engineer design such Silicon chipsmaking a career in VLSI Design / ESD is highly respected & rewarding one. Furthermore we would like to bring in your notice that VEDANT is a member of Indian Semiconductor Association as well. Semiconductor Technologies-VEDANT (Now an ISO 9001: 2000 Certified Institution) is center for the training crafted in VLSI/ESD education module followed with VLSI Design software along with the FPGA programming & 8051 Microcontroller kit.

VEDANT
VEDANT (VLSI design and training) is one of the prestigious projects of SCL, a pioneer with vertically integrated facility in the country. SCL VEDANT program covers the complete spectrum of VLSI design inclusive of front end, back end and provides of exposure to the IC fabrication process. Industry standard CAD tools are used for the purpose of training backed up by project work under the guidance of experts. VEDANT (LUCKNOW CENTER) is the institute, which provides training in VLSI design to students. The working environment is concentrated on front-end design process. It runs two programs PG diploma in VLSI designing of four months and certificate course of two months. It also provides Summer & Winter Training in VLSI Design or Embedded System. It has an advanced lab which is equipped with latest industry standard Electronic Design Automation (EDA) and FPGA tools and 8051 Development Kits inclusive of Model Sim 6.0a Xilinx tools
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FPGA Kit 8051 Development Kit Keil Software Flash Magic (Rom burning)

INTRODUCTION TO VLSI
For any given design, if the architecture of the fixed LSI and VLSI blocks suit the application then the design time is considerably shortened. When a one-chip microprocessor is not quite suitable, micro programmable architectures can often provide sufficient customization. Micro programmable architectures, such as bit-slice, allow a closer control over the architecture but not total control. The basic building blocks are still designed by the chip manufacturer for generic applications. Bit-slice architectures include interruptible sequencers and 32-bit ALUs. The customization of the bit-slice modules to an application is done through customer-designed module interconnection, the implemented commands and their sequences. The commands or instruction set is called the micro-program for the design. ASIC (VLSI, VHLSI) The 1980s saw the acceptance of ASICs ( Application Specific Integrated Circuits), VLSI devices large enough to allow designers to implement architectures that were suited to solving the design problem rather than forcing one architecture to solve everything. It was the natural extension to the bit-slice architectures, where some control of architecture was possible through microprogramming but where the basic building blocks were fixed designs. Not far behind the ASIC and ASIC developments, multimedia and design integration saw a need to incorporate analog functions into digital systems. For years the trend had been away from analog design as a chosen career and now
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there was a shortage of design engineers. First came massive re-training of internal staff as companies struggled to cope. Then came the creation of Electrically Programmable Analog Circuit (EPAC) and related devices. Application- specific solutions also includes the standard product mix where the market for a device is so large that product are developed specific to a mass application. PCI controllers is an example where one interface controller is targeted to handle the interface for many devices and device types, the control problem tailored to the device via programming. The application-specific customization of the design solution allows the designer to have the creative power of a gate-level breadboard design while keeping the production advantages of VLSI. Over the years, there has been an evolution of the universal building blocks used by logic circuit designers. In the mid-1960s, there were SSI gates; NAND, NOR, EXOR, and NOT or INVERT. In the early 1970s, MSI blocks, registers, decoders, multiplexers, and other blocks made their appearances. In the late 1970s, ALUs (arithmetic logic units) with on-board scratchpad registers, interrupt controllers, micro program sequencers, ROMs/PROMs, and other LSI devices up to and including a complete one-chip microprocessor (control, ALU and registers) became readily available. (And from this the PC was born.) SSI (small scale integration) is defined here to include chips containing approximately 2-10 gates. MSI (medium scale integration) is used for chips containing 20-100 gates. LSI (large scale integration) ships contain 200-1000 gates, with the upper limit continually extending as VLSI (very large scale integration) became a reality. In the mid-1980s, ASIC (application-specific integrated circuits) ranged from 1000 gates to 20,000 gates (bipolar technology) or 200,000 (CMOS technology).

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INTRODUCTION TO VHDL
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Excel VHDL is a user friendly windows based package which encapsulates the powerful Simily VHDL engine. A typical VHDL source file contains zero or more design units. Examples of design units are entity, architecture, package, etc. When a VHDL source file is compiled, the results of successful compilation are stored in a library .So, in effect; the design units contained within the VHDL source file are placed in a library. A design unit that has been compiled into one library can reference other designs units in any other library through the use of clauses and library statements. In VHDL, the current working library is always called work. When using a VHDL compiler or simulator, there is always a concept of a current working library. If no particular library is specified as a current working library, the current working library is assumed to be work. You can associate the work library with any other library. There are two kinds of design units: Primary and Secondary design units. The design units of type entity, package and configuration are primary design units. Design units or type architecture and package body are secondary design units. Secondary design units are always associated with a primary design unit. Secondary units typically contain the implementation of their primary units.

SIMPLE RULES TO REMEMBER

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All primary units in a given library must have unique names. Note: VHDL language actually allows the entity to have the same name, as one of its configurations but VHDL Similar requires that all primary units have unique names in a given library. All secondary units for a given primary unit must also be named uniquely. A primary design and its associated design unit must both reside in the same library.

IEEE LIBRARIES
There is a VHDL standard library with a special name std. This library and its contents (the packages standard and textio) are built
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into the tools and cant be controlled. This also means that you cant have user defined library called std. The other IEEE libraries are stored I lib folder of the installation directory. The source code is present in IEEE folder and the compiled code is present in the IEEE.SYM folder. You may view the source code folder to see the definitions for use in your code.

Introduction to Optimized FIR

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VHDL Generation of Optimized FIR Filters:- This work proposes an VHDL generation software for optimized FIR filters. In this paper a near optimum algorithm for constant coefficient FIR filters was used. This algorithm uses general coefficient representation for the optimal sharing of partial products in Multiple Constants Multiplications (MCM). The developed tool was compared to Matlab FDA toolbox. Synthesis results show that our tool is able to produce significantly better hardware than FDA toolbox, doubling the speed and reducing the silicon area by 75%. The software produces a generic VHDL output, synthesizable to ASIC or FPGA. FIR FILTER DESIGN:- In digital circuits, a FIR (Finite Impulse Response) filter can be viewed as a functional block, as shown in Figure 1-

Figure 1: Transposed form of a 4 taps FIR filter implementation. The MCM block is shown inside the striped line rectangle. where N is the number of coefficients (or taps) of the filter, X is the input signal, Y the output signal, Y[n] the current output sample and H represents the filter coefficients.

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CODE for Optimized FIR Filter

------------------------TOP MODULE OF OPTIMIZED FILTER---------------------

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; entity TOP_MODULE is Port ( RST,CLK : in STD_LOGIC; X : in STD_LOGIC_VECTOR (15 downto 0); yout : out STD_LOGIC_VECTOR (31 downto 0); cout : out STD_LOGIC); end TOP_MODULE; architecture Behavioral of TOP_MODULE is COMPONENT sixteenbit_fa1 is Port ( a : in STD_LOGIC_VECTOR (31 downto 0); b : in STD_LOGIC_VECTOR (31 downto 0); yout : out STD_LOGIC_VECTOR (31 downto 0); cout : out STD_LOGIC); end COMPONENT; COMPONENT mult16 is Port ( a : in std_logic_vector(15 downto 0); b : in std_logic_vector(15 downto 0); prod : out std_logic_vector(31 downto 0)); end COMPONENT; component dealy is Port ( rst,clk : in STD_LOGIC; din: in STD_LOGIC_VECTOR (31 downto 0); yout : out STD_LOGIC_VECTOR (31 downto 0)); end component; type coefficients is array (15 downto 0)of std_logic_vector(15 downto 0); constant k:coefficients :=("0000000000000010","0000000000000001","0000000000000011", "0000000000000100","0000000000000101","00000000000 00110", "00000000000001 11","0000000000001000","0000000000001001", "00000000000010 10","0000000000001011","0000000000001100", "00000000000011 01","0000000000001110","0000000000001111", "00000000000100 00"); type mcmblock is array (15 downto 0)of std_logic_vector(31 downto 0); signal mcm:mcmblock; type addition is array (16 downto 0)of std_logic_vector(31 downto 0); signal add:addition; type addition1 is array (15 downto 0)of std_logic_vector(31 downto 0); signal add1:addition1; SIGNAL C : std_logic_vector(15 downto 0);

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BEGIN m1:for i in 0 to 15 generate a1: mult16 PORT MAP(x,k(i),mcm(i)); end generate m1; --add1(0)<=(others=>'0'); m111:for i in 0 to 15 generate B0: sixteenbit_fa1 PORT MAP (MCM(i),add1(i),ADD(i+1),C(i)); c0:dealy port map (rst,clk,add(i+1),add1(i)); end generate m111; yout<=add(15); cout<=c(14); --m11:for i in 0 to 15 generate --end generate m11;

END Behavioral;

---------------------------dealy---------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; entity dealy is Port ( rst,clk : in STD_LOGIC; din: in STD_LOGIC_VECTOR (31 downto 0); yout : out STD_LOGIC_VECTOR (31 downto 0)); end dealy; architecture Behavioral of dealy is begin process(clk,rst) begin if rst='1' then yout<=(others=>'0'); elsif clk'event and clk='1' then yout<=din; end if; end process; end behavioral; ----VHDL code for sixteen bit adder ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL;

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entity sixteenbit_fa1 is Port ( a : in STD_LOGIC_VECTOR (31 downto 0);------15 TO 0 b : in STD_LOGIC_VECTOR (31 downto 0);--15 TO 0 yout : out STD_LOGIC_VECTOR (31 downto 0);--15 TO 0 cout : out STD_LOGIC); end sixteenbit_fa1; architecture Behavioral of sixteenbit_fa1 is signal s: std_logic_vector(31 downto 0);--15 TO 0 signal carry1: std_logic_vector(32 downto 0);--16 TO 0 COMPONENT FA PORT(a : IN std_logic; b : IN std_logic; cin : IN std_logic; sum : OUT std_logic; cout : OUT std_logic); END COMPONENT; begin carry1(0)<='0'; g1 : for i in 0 to 31 generate----0 TO 15 f0 : FA PORT MAP(a(i), b(i),carry1(i),yout(i), carry1(i+1)); -- inter_carr<=carry(i+1); end generate g1; cout<=carry1(32);-----16 end Behavioral; -----------------------------TWO_BIT_ADD------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; entity FA IS PORT(a : IN std_logic; b : IN std_logic; cin : IN std_logic; sum : OUT std_logic; cout : OUT std_logic); END FA; architecture Behavioral of FA is begin SUM<=(A XOR (B XOR CIN)); COUT<= (A AND B) OR (B AND CIN) OR (CIN AND B);

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end Behavioral;

---------VHDL code for array multiplier library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mult16 is Port ( a : in std_logic_vector(15 downto 0);---7 T0 0 b : in std_logic_vector(15 downto 0);---7 T0 0 prod : out std_logic_vector(31 downto 0));-----15 T0 0 end mult16; architecture Behavioral of mult16 is constant n:integer :=16;---8 subtype plary is std_logic_vector(n-1 downto 0); type pary is array(0 to n) of plary; signal pp,pc,ps:pary; begin pgen:for j in 0 to n-1 generate pgen1:for k in 0 to n-1 generate pp(j)(k)<=a(k) and b(j); end generate; pc(0)(j)<='0'; end generate; ps(0)<=pp(0); prod(0)<=pp(0)(0); addr:for j in 1 to n-1 generate addc:for k in 0 to n-2 generate ps(j)(k)<=pp(j)(k) xor pc(j-1)(k) xor ps(j-1)(k+1); pc(j)(k)<=(pp(j)(k) and pc(j-1)(k)) or (pp(j)(k) and ps(j-1)(k+1)) or (pc(j-1)(k)and ps(j-1)(k+1)); end generate; prod(j)<=ps(j)(0); ps(j)(n-1)<=pp(j)(n-1); end generate; pc(n)(0)<='0';

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addlast:for k in 1 to n-1 generate ps(n)(k)<=pc(n)(k-1) xor pc(n-1)(k-1) xor ps(n-1)(k); pc(n)(k)<=(pc(n)(k-1) and pc(n-1)(k-1)) or (pc(n)(k-1) and ps(n-1)(k)) or (pc(n-1)(k-1)and ps(n-1)(k)); end generate; prod(2*n-1)<=pc(n)(n-1); prod(2*n-2 downto n)<=ps(n)(n-1 downto 1); end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TOP_MODULE is generic ( m : in integer:=15); Port (clk : in std_logic; rst : in std_logic; x : in std_logic_vector(0 to(m)); YOUT : out std_logic_vector(0 to (31))); end TOP_MODULE; architecture Behavioral of TOP_MODULE is COMPONENT mcm_block_loop is generic ( m : in integer:=15); Port ( x : in std_logic_vector(0 to(m)); mcm0,mcm1 : out std_logic_vector(0 to (31)); mcm2,mcm3 : out std_logic_vector(0 to (31)); mcm4,mcm5 : out std_logic_vector(0 to (31)); mcm6,mcm7 : out std_logic_vector(0 to (31)); mcm8,mcm9 : out std_logic_vector(0 to (31)); mcm10,mcm11 : out std_logic_vector(0 to (31)); mcm12,mcm13 : out std_logic_vector(0 to (31)); mcm14,mcm15 : out std_logic_vector(0 to (31))); end COMPONENT; SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL mcm0,mcm1 : mcm2,mcm3 : mcm4,mcm5 : mcm6,mcm7 : mcm8,mcm9 : mcm10,mcm11 mcm12,mcm13 mcm14,mcm15 ADD0,ADD1 : ADD2,ADD3 : ADD4,ADD5 : ADD6,ADD7 : ADD8,ADD9 : ADD10,ADD11 std_logic_vector(0 to (31)); std_logic_vector(0 to (31)); std_logic_vector(0 to (31)); std_logic_vector(0 to (31)); std_logic_vector(0 to (31)); : std_logic_vector(0 to (31)); : std_logic_vector(0 to (31)); : std_logic_vector(0 to (31));

std_logic_vector(0 to (31)); std_logic_vector(0 to (31)); std_logic_vector(0 to (31)); std_logic_vector(0 to (31)); std_logic_vector(0 to (31)); : std_logic_vector(0 to (31));

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SIGNAL ADD12,ADD13 : std_logic_vector(0 to (31)); SIGNAL ADD14,ADD15 : std_logic_vector(0 to (31)); begin MCM_BLOCK: MCM_BLOCK_LOOP GENERIC MAP (M) PORT MAP (X,mcm0,mcm1,mcm2,mcm3,mcm4,mcm5,mcm6,mcm7, mcm8,mcm9,mcm10,mcm11,mcm12,mcm13,mcm14,mcm15); PROCESS(CLK,RST) BEGIN IF RST='1' THEN YOUT<=(OTHERS=>'0'); ELSIF CLK'EVENT AND CLK='1' THEN ADD0<=MCM0+'0'; ADD1<=ADD0+MCM1; ADD2<=ADD1+MCM2; ADD3<=ADD2+MCM3; ADD4<=ADD3+MCM4; ADD5<=ADD4+MCM5; ADD6<=ADD5+MCM6; ADD7<=ADD6+MCM7; ADD8<=ADD7+MCM8; ADD9<=ADD8+MCM9; ADD10<=ADD9+MCM10; ADD11<=ADD10+MCM11; ADD12<=ADD11+MCM12; ADD13<=ADD12+MCM13; ADD14<=ADD13+MCM14; YOUT<=ADD14+MCM15; END IF; END PROCESS; end behavioral; --------------------------------------------MCM BLOCK------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mcm_block_loop is generic ( m : in integer:=15); -----------------16 tabs FIR filter-----------Port ( x : in std_logic_vector(0 to(m)); -----------------input signal-------------mcm0,mcm1 : out std_logic_vector(0 to (31)); mcm2,mcm3 : out std_logic_vector(0 to (31)); mcm4,mcm5 : out std_logic_vector(0 to (31)); mcm6,mcm7 : out std_logic_vector(0 to (31));

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mcm8,mcm9 : out std_logic_vector(0 to (31)); mcm10,mcm11 : out std_logic_vector(0 to (31)); mcm12,mcm13 : out std_logic_vector(0 to (31)); mcm14,mcm15 : out std_logic_vector(0 to (31))); end mcm_block_loop; architecture Behavioral of mcm_block_loop is ------------------------------coefficient declaration------------------------------constant constant constant constant constant constant constant constant constant constant constant constant constant constant constant constant begin -----------------------------------------------mcm_block_description--------------------mcm0<=x*k0; mcm1<=x*k1; mcm2<=x*k2; mcm3<=x*k3; mcm4<=x*k4; mcm5<=x*k5; mcm6<=x*k6; mcm7<=x*k7; mcm8<=x*k8; mcm9<=x*k9; mcm10<=x*k10; mcM11<=x*k11; mcm12<=x*k12; mcm13<=x*k13; mcm14<=x*k14; mcm15<=x*k15; end behavioral; k0 : k1 : k2 : k3 : k4 : k5 : k6 : k7 : k8 : k9 : k10: k11: k12: k13: k14: k15: std_logic_vector(0 to(m)):="0000000000000010"; std_logic_vector(0 to(m)):="0000000000000001"; std_logic_vector(0 to(m)):="0000000000000011"; std_logic_vector(0 to(m)):="0000000000000100"; std_logic_vector(0 to(m)):="0000000000000101"; std_logic_vector(0 to(m)):="0000000000000110"; std_logic_vector(0 to(m)):="0000000000000111"; std_logic_vector(0 to(m)):="0000000000001000"; std_logic_vector(0 to(m)):="0000000000001001"; std_logic_vector(0 to(m)):="0000000000001010"; std_logic_vector(0 to(m)):="0000000000001011"; std_logic_vector(0 to(m)):="0000000000001100"; std_logic_vector(0 to(m)):="0000000000001101"; std_logic_vector(0 to(m)):="0000000000001110"; std_logic_vector(0 to(m)):="0000000000001111"; std_logic_vector(0 to(m)):="0000000000010000";

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SYNTHESIS REPORT OF Optimized FIR

Release 8.2i - xst I.31 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to ./xst/projnav.tmp CPU : 0.00 / 0.88 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.88 s | Elapsed : 0.00 / 1.00 s --> Reading design: TOP_MODULE.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report
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9) Final Report 9.1) Device utilization summary 9.2) TIMING REPORT

====================================================== =================== * Synthesis Options Summary * ====================================================== =================== ---- Source Parameters Input File Name Input Format : "TOP_MODULE.prj" : mixed

Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name Output Format Target Device ---- Source Options Top Module Name Automatic FSM Extraction FSM Encoding Algorithm FSM Style RAM Extraction RAM Style ROM Extraction Mux Style : lut : Yes : Auto : Yes : Auto
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: "TOP_MODULE" : NGC : xc3s50-5-pq208

: TOP_MODULE : YES : Auto

Decoder Extraction Priority Encoder Extraction Shift Register Extraction Logical Shifter Extraction XOR Collapsing ROM Style Mux Extraction Resource Sharing Multiplier Style

: YES : YES : YES : YES : YES : Auto : YES : YES : auto : No

Automatic Register Balancing ---- Target Options Add IO Buffers Global Maximum Fanout Register Duplication Slice Packing Pack IO Registers into IOBs Equivalent register Removal ---- General Options Optimization Goal Optimization Effort Keep Hierarchy RTL Output Global Optimization Write Timing Constraints Hierarchy Separator Bus Delimiter :/ : <>

: YES : 500 :8 : YES : YES : auto : YES

Add Generic Clock Buffer(BUFG)

: Speed :1 : NO : Yes : AllClockNets : NO

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Case Specifier Slice Utilization Ratio

: maintain : 100 :5

Slice Utilization Ratio Delta ---- Other Options lso Read Cores cross_clock_analysis verilog2001 safe_implementation use_clock_enable use_sync_set use_sync_reset

: TOP_MODULE.lso : YES : NO : YES : No : Yes : Yes : Yes

Optimize Instantiated Primitives : NO

====================================================== ===================

====================================================== =================== * HDL Compilation * ====================================================== =================== Compiling vhdl file "D:/anupam MAURYA/anu maurya/fir_filter/opti.vhd" in Library work. Architecture behavioral of Entity top_module is up to date. Architecture behavioral of Entity dealy is up to date. Architecture behavioral of Entity sixteenbit_fa1 is up to date.
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Architecture behavioral of Entity fa is up to date. Architecture behavioral of Entity mult16 is up to date. ====================================================== =================== * Design Hierarchy Analysis * ====================================================== =================== Analyzing hierarchy for entity <TOP_MODULE> in library <work> (architecture <behavioral>). Analyzing hierarchy for entity <mult16> in library <work> (architecture <behavioral>). Analyzing hierarchy for entity <sixteenbit_fa1> in library <work> (architecture <behavioral>). Analyzing hierarchy for entity <dealy> in library <work> (architecture <behavioral>). Analyzing hierarchy for entity <FA> in library <work> (architecture <behavioral>). Building hierarchy successfully finished. ====================================================== =================== * HDL Analysis *
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====================================================== =================== Analyzing Entity <TOP_MODULE> in library <work> (Architecture <behavioral>). Entity <TOP_MODULE> analyzed. Unit <TOP_MODULE> generated. Analyzing Entity <mult16> in library <work> (Architecture <behavioral>). Entity <mult16> analyzed. Unit <mult16> generated. Analyzing Entity <sixteenbit_fa1> in library <work> (Architecture <behavioral>). Entity <sixteenbit_fa1> analyzed. Unit <sixteenbit_fa1> generated. Analyzing Entity <FA> in library <work> (Architecture <behavioral>). Entity <FA> analyzed. Unit <FA> generated. Analyzing Entity <dealy> in library <work> (Architecture <behavioral>). Entity <dealy> analyzed. Unit <dealy> generated.

====================================================== =================== * HDL Synthesis * ====================================================== =================== Performing bidirectional port resolution... Synthesizing Unit <mult16>.
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Related source file is "D:/anupam MAURYA/anu maurya/fir_filter/opti.vhd". WARNING:Xst:646 - Signal <pc<0><15>> is assigned but never used. WARNING:Xst:1780 - Signal <pc<1><15>> is never used or assigned. WARNING:Xst:1780 - Signal <ps<16><0>> is never used or assigned. Summary: inferred 224 Xor(s). Unit <mult16> synthesized.

Synthesizing Unit <dealy>. Related source file is "D:/anupam MAURYA/anu maurya/fir_filter/opti.vhd". Found 32-bit register for signal <yout>. Summary: inferred 32 D-type flip-flop(s). Unit <dealy> synthesized.

Synthesizing Unit <FA>. Related source file is "D:/anupam MAURYA/anu maurya/fir_filter/opti.vhd". Found 1-bit xor3 for signal <sum>. Summary: inferred 1 Xor(s). Unit <FA> synthesized.

Synthesizing Unit <sixteenbit_fa1>.

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Related source file is "D:/anupam MAURYA/anu maurya/fir_filter/opti.vhd". WARNING:Xst:1780 - Signal <s> is never used or assigned. Unit <sixteenbit_fa1> synthesized.

Synthesizing Unit <TOP_MODULE>. Related source file is "D:/anupam MAURYA/anu maurya/fir_filter/opti.vhd". WARNING:Xst:646 - Signal <C<15>> is assigned but never used. WARNING:Xst:646 - Signal <C<13:0>> is assigned but never used. WARNING:Xst:1780 - Signal <add<0>> is never used or assigned. Unit <TOP_MODULE> synthesized.

====================================================== =================== HDL Synthesis Report Macro Statistics # Registers 32-bit register # Xors 1-bit xor2 1-bit xor3 : 16 : 16 : 4352 : 256 : 4096

====================================================== ===================
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====================================================== =================== * Advanced HDL Synthesis * ====================================================== =================== Loading device for application Rf_Device from file '3s50.nph' in environment C:\Xilinx. ====================================================== =================== Advanced HDL Synthesis Report Macro Statistics # Registers Flip-Flops # Xors 1-bit xor2 1-bit xor3 : 32 : 32 : 4352 : 256 : 4096

====================================================== =================== ====================================================== =================== * Low Level Synthesis * ====================================================== ===================

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Optimizing unit <TOP_MODULE> ... Optimizing unit <sixteenbit_fa1> ... Optimizing unit <dealy> ... Mapping all equations... WARNING:Xst:1291 - FF/Latch <m111[15].c0/yout_0> is unconnected in block <TOP_MODULE>. WARNING:Xst:1291 - FF/Latch <m111[15].c0/yout_1> is unconnected in block <TOP_MODULE>. WARNING:Xst:1291 - FF/Latch <m111[15].c0/yout_2> is unconnected in block <TOP_MODULE>. Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block TOP_MODULE, actual ratio is 4. Final Macro Processing ... ====================================================== =================== Final Register Report Macro Statistics # Registers Flip-Flops : 32 : 32

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====================================================== =================== ====================================================== =================== * Partition Report * ====================================================== =================== Partition Implementation Status ------------------------------No Partitions were found in this design. ------------------------------====================================================== =================== * Final Report * ====================================================== =================== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics
34

: TOP_MODULE.ngr : TOP_MODULE

: NGC : Speed : NO

# IOs Cell Usage : # BELS # # # # # # # # # # # # # # # LUT2 LUT2_D LUT2_L LUT3 LUT3_D LUT3_L LUT4 LUT4_D LUT4_L MUXF5 VCC FDC BUFGP IBUF OBUF

: 51

: 131 :9 :5 :1 : 20 :7 :7 : 55 :9 : 12 :5 :1 : 32 : 32 :1 :1 : 50 : 17 : 33

# FlipFlops/Latches # Clock Buffers # IO Buffers

====================================================== =================== Device utilization summary: --------------------------Selected Device : 3s50pq208-5

35

Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: Number of GCLKs:

65 out of

768

8% 2% 8% 41%

32 out of 1536 125 out of 1536 51 51 out of 1 out of 124 8

12%

====================================================== =================== TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ----------------------------------------------------+------------------------+-------+ Clock Signal CLK | Clock buffer(FF name) | Load | | BUFGP | 32 | -----------------------------------+------------------------+-------+ -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------36

-----------------------------------+------------------------+-------+ Control Signal RST | Buffer(FF name) | IBUF | 32 | | Load | -----------------------------------+------------------------+-------+ -----------------------------------+------------------------+-------+ Timing Summary: --------------Speed Grade: -5 Minimum period: 7.614ns (Maximum Frequency: 131.334MHz) Minimum input arrival time before clock: 7.866ns Maximum output required time after clock: 15.068ns Maximum combinational path delay: 15.419ns Timing Detail: -------------All values displayed in nanoseconds (ns) ====================================================== =================== Timing constraint: Default period analysis for Clock 'CLK' Clock period: 7.614ns (frequency: 131.334MHz) Total number of paths / destination ports: 1030 / 32 ------------------------------------------------------------------------Delay: Source: Destination: Source Clock: 7.614ns (Levels of Logic = 5) m111[14].c0/yout_13 (FF) m111[14].c0/yout_17 (FF) CLK rising
37

Destination Clock: CLK rising Data Path: m111[14].c0/yout_13 to m111[14].c0/yout_17 Gate Cell:in->out FDC:C->Q LUT3_D:I2->O LUT4_D:I2->O LUT4:I2->O LUT2:I1->O (N1098) LUT4:I2->O FDC:D Total 2 0.479 0.000 0.176 m111[14].c0/yout_17 m111[14].B0/sixteenbit_fa1_014_xo<1>1 (yout_17_OBUF) ---------------------------------------7.614ns (3.197ns logic, 4.417ns route) (42.0% logic, 58.0% route) ====================================================== =================== Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK' Total number of paths / destination ports: 697 / 32 ------------------------------------------------------------------------Offset: 7.866ns (Levels of Logic = 6)
38

Net

fanout Delay Delay Logical Name (Net Name) 6 0.626 0.912 m111[14].c0/yout_13 2 0.479 0.804 1 0.479 0.740 16 0.479 1.221 1 0.479 0.740 m111[14].B0/g1[16].f0/cout1_SW4

---------------------------------------- -----------(m111[14].c0/yout_13) m111[14].B0/g1[13].f0/cout1_SW0 (N995) m111[14].B0/g1[14].f0/cout1_SW0 (N1019) m111[14].B0/g1[12].f0/cout1_SW1 (N1035)

Source: Destination:

X<13> (PAD) m111[14].c0/yout_17 (FF)

Destination Clock: CLK rising Data Path: X<13> to m111[14].c0/yout_17 Gate Cell:in->out IBUF:I->O LUT3_D:I0->O LUT4_D:I2->O LUT4:I2->O LUT2:I1->O (N1098) LUT4:I2->O FDC:D Total 2 0.479 0.000 0.176 m111[14].c0/yout_17 m111[14].B0/sixteenbit_fa1_014_xo<1>1 (yout_17_OBUF) ---------------------------------------7.866ns (3.286ns logic, 4.580ns route) (41.8% logic, 58.2% route) ====================================================== =================== Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK' Total number of paths / destination ports: 1081 / 33 ------------------------------------------------------------------------39

Net

fanout Delay Delay Logical Name (Net Name) 4 0.715 1.074 X_13_IBUF (X_13_IBUF) 2 0.479 0.804 1 0.479 0.740 16 0.479 1.221 1 0.479 0.740 m111[14].B0/g1[16].f0/cout1_SW4

---------------------------------------- ------------

m111[14].B0/g1[13].f0/cout1_SW0 (N995) m111[14].B0/g1[14].f0/cout1_SW0 (N1019) m111[14].B0/g1[12].f0/cout1_SW1 (N1035)

Offset: Source: Destination: Source Clock:

15.068ns (Levels of Logic = 8) m111[14].c0/yout_1 (FF) cout (PAD) CLK rising

Data Path: m111[14].c0/yout_1 to cout Gate Cell:in->out FDC:C->Q (m111[14].c0/yout_1) LUT4_D:I2->LO (N1166) LUT3:I2->O LUT4_D:I3->O LUT4:I0->O LUT4:I0->O LUT4:I0->O LUT4:I3->O (C<14>) OBUF:I->O Total 4.909 cout_OBUF (cout) ---------------------------------------15.068ns (8.888ns logic, 6.180ns route) (59.0% logic, 41.0% route)
40

Net

fanout Delay Delay Logical Name (Net Name) 2 0.626 0.804 m111[14].c0/yout_1 1 0.479 0.159 m111[14].B0/g1[1].f0/cout1 4 0.479 0.802 m111[14].B0/g1[2].f0/cout1 5 0.479 1.078 m111[14].B0/g1[4].f0/cout1 1 0.479 0.976 m111[14].B0/g1[8].f0/cout1 1 0.479 0.976 m111[14].B0/g1[24].f0/cout1 1 0.479 0.704 m111[14].B0/g1[28].f0/cout1 1 0.479 0.681 m111[14].B0/g1[31].f0/cout1

---------------------------------------- ------------

(m111[14].B0/carry1<3>) (m111[14].B0/carry1<5>) (m111[14].B0/carry1<9>) (m111[14].B0/carry1<25>) (m111[14].B0/carry1<29>)

====================================================== =================== Timing constraint: Default path analysis Total number of paths / destination ports: 727 / 33 ------------------------------------------------------------------------Delay: Source: Destination: 15.419ns (Levels of Logic = 9) X<0> (PAD) cout (PAD)

Data Path: X<0> to cout Gate Cell:in->out IBUF:I->O LUT4_D:I0->LO (N1166) LUT3:I2->O LUT4_D:I3->O LUT4:I0->O LUT4:I0->O LUT4:I0->O LUT4:I3->O (C<14>)
41

Net

fanout Delay Delay Logical Name (Net Name) 3 0.715 1.066 X_0_IBUF (X_0_IBUF) 1 0.479 0.159 m111[14].B0/g1[1].f0/cout1 4 0.479 0.802 m111[14].B0/g1[2].f0/cout1 5 0.479 1.078 m111[14].B0/g1[4].f0/cout1 1 0.479 0.976 m111[14].B0/g1[8].f0/cout1 1 0.479 0.976 m111[14].B0/g1[24].f0/cout1 1 0.479 0.704 m111[14].B0/g1[28].f0/cout1 1 0.479 0.681 m111[14].B0/g1[31].f0/cout1

---------------------------------------- ------------

(m111[14].B0/carry1<3>) (m111[14].B0/carry1<5>) (m111[14].B0/carry1<9>) (m111[14].B0/carry1<25>) (m111[14].B0/carry1<29>)

OBUF:I->O Total

4.909

cout_OBUF (cout)

---------------------------------------15.419ns (8.977ns logic, 6.442ns route) (58.2% logic, 41.8% route) ====================================================== =================== CPU : 427.25 / 428.26 s | Elapsed : 427.00 / 428.00 s --> Total memory usage is 217356 kilobytes Number of errors : Number of infos : 0 ( 0 filtered) 0 ( 0 filtered)

Number of warnings : 503 ( 0 filtered)

SYNTHESIS REPORT OF Transposed FIR Filter

Release 8.2i - xst I.31 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to ./xst/projnav.tmp CPU : 0.00 / 0.95 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.95 s | Elapsed : 0.00 / 1.00 s

42

--> Reading design: TOP_MODULE.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) TIMING REPORT

====================================================== =================== * Synthesis Options Summary * ====================================================== =================== ---- Source Parameters Input File Name Input Format : "TOP_MODULE.prj" : mixed

Ignore Synthesis Constraint File : NO ---- Target Parameters

43

Output File Name Output Format Target Device ---- Source Options Top Module Name Automatic FSM Extraction FSM Encoding Algorithm FSM Style RAM Extraction RAM Style ROM Extraction Mux Style Decoder Extraction Priority Encoder Extraction Shift Register Extraction Logical Shifter Extraction XOR Collapsing ROM Style Mux Extraction Resource Sharing Multiplier Style

: "TOP_MODULE" : NGC : xc3s50-5-pq208

: TOP_MODULE : YES : Auto : lut : Yes : Auto : Yes : Auto : YES : YES : YES : YES : YES : Auto : YES : YES : auto : No

Automatic Register Balancing ---- Target Options Add IO Buffers Global Maximum Fanout Register Duplication

: YES : 500 :8
44

Add Generic Clock Buffer(BUFG) : YES

Slice Packing

: YES : auto : YES

Pack IO Registers into IOBs Equivalent register Removal ---- General Options Optimization Goal Optimization Effort Keep Hierarchy RTL Output Global Optimization Write Timing Constraints Hierarchy Separator Bus Delimiter Case Specifier Slice Utilization Ratio Slice Utilization Ratio Delta ---- Other Options lso Read Cores cross_clock_analysis verilog2001 safe_implementation use_clock_enable use_sync_set use_sync_reset :/ : <>

: Speed :1 : NO : Yes : AllClockNets : NO

: maintain : 100 :5

: TOP_MODULE.lso : YES : NO : YES : No : Yes : Yes : Yes

Optimize Instantiated Primitives : NO

45

====================================================== ===================

====================================================== =================== * HDL Compilation * ====================================================== =================== WARNING:HDLParsers:3215 - Unit work/TOP_MODULE is now defined in a different file: was D:/anupam MAURYA/anu maurya/fir_filter/opti.vhd, now is D:/anupam MAURYA/anu maurya/fir_filter/mcm_block.vhd WARNING:HDLParsers:3215 - Unit work/TOP_MODULE/Behavioral is now defined in a different file: was D:/anupam MAURYA/anu maurya/fir_filter/opti.vhd, now is D:/anupam MAURYA/anu maurya/fir_filter/mcm_block.vhd Compiling vhdl file "D:/anupam MAURYA/anu maurya/fir_filter/mcm_block.vhd" in Library work. Architecture behavioral of Entity top_module is up to date. Architecture behavioral of Entity mcm_block_loop is up to date. ====================================================== =================== * Design Hierarchy Analysis * ====================================================== =================== Analyzing hierarchy for entity <TOP_MODULE> in library <work> (architecture <behavioral>) with generics. m = 15
46

Analyzing hierarchy for entity <mcm_block_loop> in library <work> (architecture <behavioral>) with generics. m = 15 Building hierarchy successfully finished. ====================================================== =================== * HDL Analysis * ====================================================== =================== Design Repository: return true for module <TOP_MODULE> Analyzing generic Entity <TOP_MODULE> in library <work> (Architecture <behavioral>). m = 15 Entity <TOP_MODULE> analyzed. Unit <TOP_MODULE> generated. Design Repository: return true for module <mcm_block_loop> Analyzing generic Entity <mcm_block_loop> in library <work> (Architecture <behavioral>). m = 15 Entity <mcm_block_loop> analyzed. Unit <mcm_block_loop> generated.

====================================================== =================== * HDL Synthesis *

47

====================================================== =================== Performing bidirectional port resolution... Synthesizing Unit <mcm_block_loop>. Related source file is "D:/anupam MAURYA/anu maurya/fir_filter/mcm_block.vhd". Found 16x16-bit multiplier for signal <mcm10>. Found 16x16-bit multiplier for signal <mcm11>. Found 16x16-bit multiplier for signal <mcm12>. Found 16x16-bit multiplier for signal <mcm13>. Found 16x16-bit multiplier for signal <mcm14>. Found 16x16-bit multiplier for signal <mcm2>. Found 16x16-bit multiplier for signal <mcm4>. Found 16x16-bit multiplier for signal <mcm5>. Found 16x16-bit multiplier for signal <mcm6>. Found 16x16-bit multiplier for signal <mcm8>. Found 16x16-bit multiplier for signal <mcm9>. Summary: inferred 11 Multiplier(s). Unit <mcm_block_loop> synthesized.

Synthesizing Unit <TOP_MODULE>. Related source file is "D:/anupam MAURYA/anu maurya/fir_filter/mcm_block.vhd". WARNING:Xst:1780 - Signal <ADD15> is never used or assigned. Found 32-bit register for signal <YOUT>.
48

Found 32-bit adder for signal <$add0000> created at line 81. Found 32-bit adder for signal <$add0001> created at line 75. Found 32-bit adder for signal <$add0002> created at line 76. Found 32-bit adder for signal <$add0003> created at line 77. Found 32-bit adder for signal <$add0004> created at line 78. Found 32-bit adder for signal <$add0005> created at line 79. Found 32-bit adder for signal <$add0006> created at line 66. Found 32-bit adder for signal <$add0007> created at line 67. Found 32-bit adder for signal <$add0008> created at line 68. Found 32-bit adder for signal <$add0009> created at line 69. Found 32-bit adder for signal <$add0010> created at line 70. Found 32-bit adder for signal <$add0011> created at line 71. Found 32-bit adder for signal <$add0012> created at line 72. Found 32-bit adder for signal <$add0013> created at line 73. Found 32-bit adder for signal <$add0014> created at line 74. Found 32-bit register for signal <ADD0>. Found 32-bit register for signal <ADD1>. Found 32-bit register for signal <ADD10>. Found 32-bit register for signal <ADD11>. Found 32-bit register for signal <ADD12>. Found 32-bit register for signal <ADD13>. Found 32-bit register for signal <ADD14>. Found 32-bit register for signal <ADD2>. Found 32-bit register for signal <ADD3>. Found 32-bit register for signal <ADD4>. Found 32-bit register for signal <ADD5>. Found 32-bit register for signal <ADD6>. Found 32-bit register for signal <ADD7>. Found 32-bit register for signal <ADD8>.
49

Found 32-bit register for signal <ADD9>. Summary: inferred 512 D-type flip-flop(s). inferred 15 Adder/Subtractor(s). Unit <TOP_MODULE> synthesized.

====================================================== =================== HDL Synthesis Report Macro Statistics # Multipliers 16x16-bit multiplier # Adders/Subtractors 32-bit adder # Registers 32-bit register : 15 : 16 : 16 : 11 : 11 : 15

====================================================== =================== ====================================================== =================== * Advanced HDL Synthesis * ====================================================== ===================

50

Loading device for application Rf_Device from file '3s50.nph' in environment C:\Xilinx. ====================================================== =================== Advanced HDL Synthesis Report Macro Statistics # Multipliers 16x16-bit multiplier # Adders/Subtractors 32-bit adder # Registers Flip-Flops : 15 : 512 : 512 : 11 : 11 : 15

====================================================== =================== ====================================================== =================== * Low Level Synthesis * ====================================================== =================== INFO:Xst:2261 - The FF/Latch <ADD0_31> in Unit <TOP_MODULE> is equivalent to the following 15 FFs/Latches, which will be removed : <ADD0_14> <ADD0_13> <ADD0_12> <ADD0_11> <ADD0_10> <ADD0_9> <ADD0_8> <ADD0_7> <ADD0_6> <ADD0_5> <ADD0_4> <ADD0_3> <ADD0_2> <ADD0_1> <ADD0_0>
51

WARNING:Xst:1710 - FF/Latch <ADD0_31> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1710 - FF/Latch <ADD1_0> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD1_1> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD1_2> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD1_3> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD1_4> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD1_5> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD1_6> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD1_7> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD1_8> (without init value) has a constant value of 0 in block <TOP_MODULE>.
52

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD1_9> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD1_10> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD1_11> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD1_12> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD1_13> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD2_0> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD2_1> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD2_2> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD2_3> (without init value) has a constant value of 0 in block <TOP_MODULE>.

53

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD2_4> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD2_5> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD2_6> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD2_7> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD2_8> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD2_9> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD2_10> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD2_11> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD2_12> (without init value) has a constant value of 0 in block <TOP_MODULE>.

54

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD3_0> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD3_1> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD3_2> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD3_3> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD3_4> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD3_5> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD3_6> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD3_7> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD3_8> (without init value) has a constant value of 0 in block <TOP_MODULE>.

55

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD3_9> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD3_10> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD3_11> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD4_0> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD4_1> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD4_2> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD4_3> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD4_4> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD4_5> (without init value) has a constant value of 0 in block <TOP_MODULE>.

56

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD4_6> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD4_7> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD4_8> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD4_9> (without init value) has a constant value of 0 in block <TOP_MODULE>. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ADD4_10> (without init value) has a constant value of 0 in block <TOP_MODULE>. INFO:Xst:2261 - The FF/Latch <ADD0_30> in Unit <TOP_MODULE> is equivalent to the following FF/Latch, which will be removed : <ADD1_31> Optimizing unit <TOP_MODULE> ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block TOP_MODULE, actual ratio is 43. Final Macro Processing ... Processing Unit <TOP_MODULE> : Found 2-bit shift register for signal <ADD3_31>.
57

Found 2-bit shift register for signal <ADD3_30>. Found 2-bit shift register for signal <ADD7_31>. Found 2-bit shift register for signal <ADD7_30>. Found 2-bit shift register for signal <ADD7_29>. Found 2-bit shift register for signal <ADD11_31>. Found 2-bit shift register for signal <ADD11_30>. Found 2-bit shift register for signal <ADD13_31>. Unit <TOP_MODULE> processed. ====================================================== =================== Final Register Report Macro Statistics # Registers Flip-Flops # Shift Registers 2-bit shift register : 429 : 429 :8 :8

====================================================== =================== ====================================================== =================== * Partition Report * ====================================================== =================== Partition Implementation Status
58

------------------------------Preserved Partitions:

Implemented Partitions: Partition "/TOP_MODULE": There was no implementation for this Partition. -------------------------------

Partition NGC Files ------------------------------Partition "/TOP_MODULE": NGC File: TOP_MODULE.ngc ------------------------------====================================================== =================== * Final Report * ====================================================== =================== Final Results RTL Top Level Output File Name Top Level Output File Name : TOP_MODULE.ngr : TOP_MODULE
59

Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs Cell Usage : # BELS # # # # # # # # # # # # # # # GND INV LUT1 LUT2 LUT3 MUXCY VCC XORCY FDC FDE SRL16E BUFGP IBUF OBUF MULT18X18 :1 : 50

: NGC : Speed : NO

: 1777 :1 :1 : 101 : 491 : 12 : 593 : 577 : 437 : 32 : 405 :8 :8 :1 :1 : 49 : 17 : 32 :4 :4

60

# FlipFlops/Latches

# Shift Registers # Clock Buffers # IO Buffers

# MULTs

====================================================== =================== Device utilization summary: --------------------------Selected Device : 3s50pq208-5 Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number used as logic: Number of IOs: Number of bonded IOBs: Number of MULT18X18s: Number of GCLKs: Number used as Shift registers: 50 50 out of 4 out of 1 out of 8 124 40% 4 100% 12% 331 out of 768 43% 28% 39%

437 out of 1536 613 out of 1536 605 8

====================================================== =================== TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
61

Clock Information: ----------------------------------------------------+------------------------+-------+ Clock Signal clk | Clock buffer(FF name) | Load | | BUFGP | 445 | -----------------------------------+------------------------+-------+ -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: --------------------------------------------------------------------------+------------------------+-------+ Control Signal rst | Buffer(FF name) | IBUF | 32 | | Load | -----------------------------------+------------------------+-------+ -----------------------------------+------------------------+-------+ Timing Summary: --------------Speed Grade: -5 Minimum period: 5.018ns (Maximum Frequency: 199.288MHz) Minimum input arrival time before clock: 11.320ns Maximum output required time after clock: 6.216ns Maximum combinational path delay: No path found Timing Detail: -------------All values displayed in nanoseconds (ns)
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====================================================== =================== Timing constraint: Default period analysis for Clock 'clk' Clock period: 5.018ns (frequency: 199.288MHz) Total number of paths / destination ports: 11545 / 429 ------------------------------------------------------------------------Delay: Source: Destination: Source Clock: 5.018ns (Levels of Logic = 33) ADD4_31 (FF) ADD5_0 (FF) clk rising

Destination Clock: clk rising Data Path: ADD4_31 to ADD5_0 Gate Cell:in->out FDE:C->Q LUT2:I1->O MUXCY:S->O MUXCY:CI->O (Madd__add0010_cy<1>) MUXCY:CI->O (Madd__add0010_cy<2>) MUXCY:CI->O (Madd__add0010_cy<3>) MUXCY:CI->O (Madd__add0010_cy<4>)
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Net

fanout Delay Delay Logical Name (Net Name) 1 0.626 0.851 ADD4_31 (ADD4_31) 2 0.479 0.000 Madd__add0010_lut<0> (N78) 1 0.435 0.000 Madd__add0010_cy<0> 1 0.056 0.000 Madd__add0010_cy<1> 1 0.056 0.000 Madd__add0010_cy<2> 1 0.056 0.000 Madd__add0010_cy<3> 1 0.056 0.000 Madd__add0010_cy<4>

---------------------------------------- ------------

(Madd__add0010_cy<0>)

MUXCY:CI->O (Madd__add0010_cy<5>) MUXCY:CI->O (Madd__add0010_cy<6>) MUXCY:CI->O (Madd__add0010_cy<7>) MUXCY:CI->O (Madd__add0010_cy<8>) MUXCY:CI->O (Madd__add0010_cy<9>) MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O

1 0.056 0.000 Madd__add0010_cy<5> 1 0.056 0.000 Madd__add0010_cy<6> 1 0.056 0.000 Madd__add0010_cy<7> 1 0.056 0.000 Madd__add0010_cy<8> 1 0.056 0.000 Madd__add0010_cy<9> 1 0.056 0.000 Madd__add0010_cy<10> 1 0.056 0.000 Madd__add0010_cy<11> 1 0.055 0.000 Madd__add0010_cy<12> 1 0.056 0.000 Madd__add0010_cy<13> 1 0.056 0.000 Madd__add0010_cy<14> 1 0.056 0.000 Madd__add0010_cy<15> 1 0.056 0.000 Madd__add0010_cy<16> 1 0.056 0.000 Madd__add0010_cy<17> 1 0.056 0.000 Madd__add0010_cy<18>

(Madd__add0010_cy<10>) (Madd__add0010_cy<11>) (Madd__add0010_cy<12>) (Madd__add0010_cy<13>) (Madd__add0010_cy<14>) (Madd__add0010_cy<15>) (Madd__add0010_cy<16>) (Madd__add0010_cy<17>) (Madd__add0010_cy<18>)

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MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O XORCY:CI->O (_add0010<31>) FDE:D Total

1 0.056 0.000 Madd__add0010_cy<19> 1 0.056 0.000 Madd__add0010_cy<20> 1 0.056 0.000 Madd__add0010_cy<21> 1 0.056 0.000 Madd__add0010_cy<22> 1 0.056 0.000 Madd__add0010_cy<23> 1 0.056 0.000 Madd__add0010_cy<24> 1 0.056 0.000 Madd__add0010_cy<25> 1 0.056 0.000 Madd__add0010_cy<26> 1 0.056 0.000 Madd__add0010_cy<27> 1 0.056 0.000 Madd__add0010_cy<28> 1 0.056 0.000 Madd__add0010_cy<29> 0 0.056 0.000 Madd__add0010_cy<30> 1 0.786 0.000 Madd__add0010_xor<31> 0.176 ADD5_0

(Madd__add0010_cy<19>) (Madd__add0010_cy<20>) (Madd__add0010_cy<21>) (Madd__add0010_cy<22>) (Madd__add0010_cy<23>) (Madd__add0010_cy<24>) (Madd__add0010_cy<25>) (Madd__add0010_cy<26>) (Madd__add0010_cy<27>) (Madd__add0010_cy<28>) (Madd__add0010_cy<29>) (Madd__add0010_cy<30>)

---------------------------------------5.018ns (4.167ns logic, 0.851ns route)

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(83.0% logic, 17.0% route) ====================================================== =================== Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 421789 / 846 ------------------------------------------------------------------------Offset: Source: Destination: 11.320ns (Levels of Logic = 36) x<13> (PAD) ADD14_0 (FF)

Destination Clock: clk rising Data Path: x<13> to ADD14_0 Gate Cell:in->out IBUF:I->O LUT2:I0->O Net fanout Delay Delay Logical Name (Net Name) 32 0.715 1.870 x_13_IBUF (x_13_IBUF) 1 0.479 0.000

---------------------------------------- ------------

MCM_BLOCK/Mmult_mcm14_Madd_lut<2> (MCM_BLOCK/Mmult_mcm14_Madd_2) MUXCY:S->O 1 0.435 0.000 MCM_BLOCK/Mmult_mcm14_Madd_cy<2> (MCM_BLOCK/Mmult_mcm14_Madd_cy<2>) MUXCY:CI->O 1 0.056 0.000 MCM_BLOCK/Mmult_mcm14_Madd_cy<3> (MCM_BLOCK/Mmult_mcm14_Madd_cy<3>) MUXCY:CI->O 1 0.056 0.000 MCM_BLOCK/Mmult_mcm14_Madd_cy<4> (MCM_BLOCK/Mmult_mcm14_Madd_cy<4>)
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MUXCY:CI->O

1 0.056 0.000

MCM_BLOCK/Mmult_mcm14_Madd_cy<5> (MCM_BLOCK/Mmult_mcm14_Madd_cy<5>) MUXCY:CI->O 1 0.056 0.000 MCM_BLOCK/Mmult_mcm14_Madd_cy<6> (MCM_BLOCK/Mmult_mcm14_Madd_cy<6>) MUXCY:CI->O 1 0.056 0.000 MCM_BLOCK/Mmult_mcm14_Madd_cy<7> (MCM_BLOCK/Mmult_mcm14_Madd_cy<7>) MUXCY:CI->O 1 0.056 0.000 MCM_BLOCK/Mmult_mcm14_Madd_cy<8> (MCM_BLOCK/Mmult_mcm14_Madd_cy<8>) XORCY:CI->O 2 0.786 1.040 MCM_BLOCK/Mmult_mcm14_Madd_xor<9> (MCM_BLOCK/Mmult_mcm14_Madd_9) LUT2:I0->O MUXCY:S->O 1 0.479 0.000 1 0.435 0.000 MCM_BLOCK/Mmult_mcm14_Madd2_lut<9> (N410) MCM_BLOCK/Mmult_mcm14_Madd2_cy<9> (MCM_BLOCK/Mmult_mcm14_Madd2_cy<9>) MUXCY:CI->O 1 0.056 0.000 MCM_BLOCK/Mmult_mcm14_Madd2_cy<10> (MCM_BLOCK/Mmult_mcm14_Madd2_cy<10>) MUXCY:CI->O 1 0.056 0.000 MCM_BLOCK/Mmult_mcm14_Madd2_cy<11> (MCM_BLOCK/Mmult_mcm14_Madd2_cy<11>) MUXCY:CI->O 1 0.056 0.000 MCM_BLOCK/Mmult_mcm14_Madd2_cy<12> (MCM_BLOCK/Mmult_mcm14_Madd2_cy<12>)
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MUXCY:CI->O

1 0.056 0.000

MCM_BLOCK/Mmult_mcm14_Madd2_cy<13> (MCM_BLOCK/Mmult_mcm14_Madd2_cy<13>) MUXCY:CI->O 1 0.056 0.000 MCM_BLOCK/Mmult_mcm14_Madd2_cy<14> (MCM_BLOCK/Mmult_mcm14_Madd2_cy<14>) MUXCY:CI->O 1 0.056 0.000 MCM_BLOCK/Mmult_mcm14_Madd2_cy<15> (MCM_BLOCK/Mmult_mcm14_Madd2_cy<15>) MUXCY:CI->O 1 0.056 0.000 MCM_BLOCK/Mmult_mcm14_Madd2_cy<16> (MCM_BLOCK/Mmult_mcm14_Madd2_cy<16>) MUXCY:CI->O 1 0.056 0.000 MCM_BLOCK/Mmult_mcm14_Madd2_cy<17> (MCM_BLOCK/Mmult_mcm14_Madd2_cy<17>) MUXCY:CI->O 1 0.056 0.000 MCM_BLOCK/Mmult_mcm14_Madd2_cy<18> (MCM_BLOCK/Mmult_mcm14_Madd2_cy<18>) XORCY:CI->O LUT2:I0->O MUXCY:S->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O 1 0.786 0.976 1 0.479 0.000 Madd__add0005_lut<19> (N532) 1 0.435 0.000 Madd__add0005_cy<19> 1 0.056 0.000 Madd__add0005_cy<20> 1 0.056 0.000 Madd__add0005_cy<21> 1 0.056 0.000 Madd__add0005_cy<22>
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MCM_BLOCK/Mmult_mcm14_Madd2_xor<19> (mcm14<12>)

(Madd__add0005_cy<19>) (Madd__add0005_cy<20>) (Madd__add0005_cy<21>) (Madd__add0005_cy<22>)

MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O MUXCY:CI->O XORCY:CI->O (_add0005<31>) FDE:D Total

1 0.056 0.000 Madd__add0005_cy<23> 1 0.056 0.000 Madd__add0005_cy<24> 1 0.056 0.000 Madd__add0005_cy<25> 1 0.056 0.000 Madd__add0005_cy<26> 1 0.056 0.000 Madd__add0005_cy<27> 1 0.056 0.000 Madd__add0005_cy<28> 1 0.056 0.000 Madd__add0005_cy<29> 0 0.056 0.000 Madd__add0005_cy<30> 1 0.786 0.000 Madd__add0005_xor<31> 0.176 ADD14_0

(Madd__add0005_cy<23>) (Madd__add0005_cy<24>) (Madd__add0005_cy<25>) (Madd__add0005_cy<26>) (Madd__add0005_cy<27>) (Madd__add0005_cy<28>) (Madd__add0005_cy<29>) (Madd__add0005_cy<30>)

---------------------------------------11.320ns (7.434ns logic, 3.886ns route) (65.7% logic, 34.3% route) ====================================================== =================== Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 32 / 32 ------------------------------------------------------------------------Offset: 6.216ns (Levels of Logic = 1)
69

Source: Destination: Source Clock:

YOUT_0 (FF) YOUT<0> (PAD) clk rising

Data Path: YOUT_0 to YOUT<0> Gate Cell:in->out FDC:C->Q OBUF:I->O Total Net fanout Delay Delay Logical Name (Net Name) 1 0.626 0.681 YOUT_0 (YOUT_0) 4.909 YOUT_0_OBUF (YOUT<0>)

---------------------------------------- ------------

---------------------------------------6.216ns (5.535ns logic, 0.681ns route) (89.0% logic, 11.0% route) ====================================================== =================== CPU : 54.53 / 55.66 s | Elapsed : 55.00 / 56.00 s --> Total memory usage is 153932 kilobytes Number of errors : Number of infos : 0 ( 0 filtered) 2 ( 0 filtered)

Number of warnings : 54 ( 0 filtered)

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BIBLIOGRAPHY
Following is the list of books from which help has been taken for the completion of this project. 1 2 3 VHDL-PRIMER MODERN DIGITAL ELECTRONICS DIGITAL DESIGN J.Bhasker R.P.Jain MorisMano

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