International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com Volume 1, Issue 3, September October 2012 ISSN 2278-6856

STUDY AND ANALYSIS OF HIGH PERFORMANCE XNOR BASED 1-BIT FULL ADDER CELL
Subhadeep Nandy
Department of Electronics and Communication Engineering Camellia Institute of Technology Kolkata, India

Abstract: In this paper a low power and high performance

XNOR based 1 bit Full Adder cell is proposed. According to many simulations and comparisons with state of the art designs, this design demonstrates some achievement. This new full adder cell has been compared with Conventional CMOS Full Adder cell and a few number of different logical adder cell (Transmission Gate(TG) adder, Transmission function adder(TFA), Complementary pass transistor logic(CPL) adder, N-cell adder). The most important parameters of performance are speed and power consumption. This Full adder has been simulated using HSPICE with 0.18m CMOS technology at different supply voltages ranges from 1v to 3.5v with 0.5 steps. The delay of the cell has been measured from the moment that inputs reach 50% of supply voltage level to the moment that latest of the sum and carry signals reach the same voltage level and power consumption is the average of power consumption during all transitions. The results confirm that this proposed adder achieved significant improvement in terms of power, delay and power delay product. Three input pulses and sum and carry signals are taken from the COSMOS SCOPE software.

fast growing technologies in mobile communication and computation. The battery technology doesnt advance at the same rate as the microelectronics technology. There is a limited amount of power available for the mobile systems. So designers are faced with more constraints: high speed, high throughput, small silicon area, and at the same time, low-power consumption [1]. So building low-power, high-performance adder cells is of great interest. Designing systems aiming for low power is not a straightforward task, as it is involved in all the IC design stages beginning with the system behavioral description and ending with the fabrication and packaging processes. In some of these stages there are guidelines that are clear and there are steps to follow that reduce power consumption, such as decreasing the power-supply voltage. While in other stages there are no clear steps to follow, so statistical or probabilistic heuristic methods are used to estimate the power consumption of a given design [2], [3].

2. SOURCES OF POWER DISSIPATION

There are three major sources of power dissipation in digital CMOS circuits, which are summarized in the following equation : Ptotal = pt (CL . V. Vdd . fclk) + Isc . Vdd + Ileakage . Vdd (1) The first term represents the switching component of power, where CL is the loading capacitance, fclk is the clock frequency, and pt is the probability that a power consuming transition occurs (the activity factor). In most cases, the voltage swing V is the same as the supply voltage Vdd ; however in some logic circuits , such as in single gate pass transistor implementations, the voltage swing on some internal nodes may be slightly less[8] . the second term is due to the direct path short circuit current Isc , which arises when both the PMOS & NMOS transistor are simultaneously active, conducting current directly from supply to ground[4],[5]. Finally, leakage current Ileakage , which can arise from substrate injection & subthreshold effects, is primarily determined by fabrication technology considerations [6].The dominant term in well-designed circuit is the switching Page 85

Keyword: Addition, Arithmetic circuits, Delay, Full adder, Low Power, PDP, XNOR, Electric, HSPICE, COSMOS SCOPE

1. INTRODUCTION
The Explosive growth in laptop, portable system, and cellular networks has intensified the research efforts in low power microelectronics. Today we find number of portable applications requiring low power and high throughput circuits. Addition is one of the fundamental arithmetic operations. It is used extensively in many VLSI systems such as application-specific DSP architectures and microprocessors. In addition to its main task, which is adding two binary numbers, it is the nucleus of many other useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder is part of the critical path that determines the overall performance of the system. That is why enhancing the performance of the 1bit full-adder cell (the building block of the binary adder) is a significant goal. Recently, building low-power VLSI systems has emerged as highly in demand because of the Volume 1, Issue 3 September-October 2012

International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com Volume 1, Issue 3, September October 2012 ISSN 2278-6856
components, & low power design thus becomes the task of minimizing pt, CL, Vdd and fclk, while retaining the required functionality. The power delay product can be interpreted as the amount of energy expended in each switching event (or transition) and is thus particularly useful in comparing the power dissipation of various circuit styles. If it is assumed that only the switching component of power dissipation is important then it is given by Energy per transition = Ptotal / fclk = Ceffective . V2 dd (2) Where Ceffective is the effective capacitance being switched to perform a computation and is given by Ceffective= pt. CL Figure 2: The Complementary Pass-transistor Logic (CPL) Transmission Gate full adder (TG) [9][12] includes 20 transistors, and generates a+b and its complement to produce the sum and carry signals. It uses complementary input signals (a,b,c) as the complementary CMOS full adder [6,7] .It is less area consuming than conventional adder. Due to less output voltage swing that is the result of one Vt loss in the output. However it reduces noise margin and causes serious problems in cascading, especially at low voltages[11]. Area optimization cant be done in this circuit.

3. CONVENTIONAL FULL ADDER LOGIC STYLE

Various static CMOS logic styles have been used to implement low-power and high-performance 1-bit Full Adder cells. The 1-bit conventional CMOS full adder cell [7] has 28 transistors is shown in figure-1. Different logic styles can be investigated from different points of view. Evidently, they tend to favour one performance aspect at the expense of others. In other words, it is different design constraints imposed by the application that each logic style has its place in the cell library development. The CMOS structure combines PMOS pull-up and NMOS pull-down networks to produce considered outputs. In this style all transistors (either PMOS or NMOS) are arranged in completely separate branches, each may consist of several sub-branches. Mutually exclusiveness of pull-up and pull-down networks is of a great concern. Conventional CMOS Style is[8]

Figure 3: Transmission Gate full adder Transmission Full Adder (TFA) [10] has simpler schematic than the conventional CMOS full adder shown in Figure 4.The TFA needs fewer MOS transistors in comparison with the previous one. The transistor count of TFA is 16 transistor, while the conventional CMOS full adder requires 28 transistors. TFA provides buffered outputs of the proper polarity with equal delay for both sum (S) and carry-out (C). Its disadvantage is slow speed and high power consumption.

Figure 1: Conventional CMOS full Adder.

4. PREVIOUS WORKS
The Complementary Pass-transistor Logic (CPL) Full Adder [9] of Figure 2 has 38 transistors and is based on nMOS pass-transistor network. This circuit generate many intermediate node & their complements in order to generate their final signal. Due to production of complement circuit have high rate of switching activity [12] .So it is not suitable for low power application. CPL consumes less power than standard static CMOS circuits. Volume 1, Issue 3 September-October 2012 Figure 4: Transmission Full adder N-CELL1 Full Adders [8], which is shown in Figure:5 are based on low-power XOR/XNOR circuit .N-CELL1 has 14 transistors and utilizes the low power XNOR circuit and a pass transistors network to produce a non full swing Sum signal and uses four transistors to Page 86

International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com Volume 1, Issue 3, September October 2012 ISSN 2278-6856
generate a full swing Cout signal, which do not provide enough driving power[11] .

7. SIMULATION COMPARISON

RESULTS

AND

Figure 5: N-CELL1 Full Adders

5. PROPOSED XNOR BASED FULL ADDER

Proposed XNOR based adder consist of 12 transistors which is the lowest number in comparison to the previous adder mentioned above. Output means sun and carry are taken from a multiplexer based transmission gate and pass transistor based transmission gate respectively to get the full swing output.

The simulation result of XNOR based full adder circuit is shown in figure 8. The three input pulses are taken in different frequencies (100MHZ, 50MHZ, 25MHZ). The three inputs of different frequencies are represented by the first three pulses in Figure 8. The output of sum & carry is shown by the next two pulses respectively in Figure 8. Simulation result (Input & Output pattern) of XNOR based full-adder circuit is taken by using COSMOS SCOPE software.

Figure 8: Simulated input and output waveform of XNOR Adder (COSMOS SCOPE view) Table 1: AVERAGE POWER OF CONVENTIONAL AND XNOR ADDER

Figure 6: XNOR based full adder (Electric VLSI Design Software view) The circuit consist of one XNOR block, one inverter block, one multiplexer based transmission gate block and one pass transistor based transmission gate block. A,B & C are the three inputs of the circuit. Sum & Carry are the output of circuit. This inputs & outputs can be described by the following equation. sum= (A xnor B)C + C(A xnor B). carry= (A xnor B)A + (A xnor B)C.

6. FUNCTIONALITY TEST

Table 2: PROPAGATION DELAY OF CONVENTIONAL AND XNOR ADDER

Figure 7: Functionality test of the XNOR based full adder (Electric VLSI Design Software view) Volume 1, Issue 3 September-October 2012 Page 87

International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com Volume 1, Issue 3, September October 2012 ISSN 2278-6856
Table 3: POWER-DELAY-PRODUCT OF CONVENTIONAL AND XNOR ADDER
power-delay-product is done. Based on survey & testing, it is concluded that the XNOR based adder has good signal level, consume less power and have high speed compare to conventional adder and other type of adder circuits. At 1.8 volt supply voltage the result shows that average power saving in proposed XNOR based adder circuit is 17.81% than conventional CMOS adder circuit. The proposed circuit also shows the degradation of delay 14.41% than conventional CMOS. After all the proposed XNOR based adder circuit shows the improvement of performance 29.63% in comparison to conventional CMOS adder circuit. At 1.8v supply voltage the proposed XNOR based full adder shows better performance with Pass Transistor (PT) gates is better than TFA & N-Cell adder. According to HSPICE result the suggested XNOR based full adder shows better performance with PT gates consumes 14.55% less power compared to TFA adder. Though the power consumption of XNOR based full adder & N-Cell full adder is about same in 1.8 volt . Power-delay product of the proposed XNOR based adder is less than other compared adders. The results show 25.15% improvement in regards of PDP of proposed XNOR based adder, when being compared with the TFA adder & shows 24% improvement of performance when compared with N-Cell adder.

Table 4: This table shows the comparison among XNOR based full adder circuit and other different logical adder circuit. All the data are taken in 1.8 volt supply voltage & the same input signal as in the proposed XNOR adder circuit, are given to the input of each type adder circuit. In all cases (W/L)nMOS=2(W/L)pMOS. Name of Averag Power* the e Propagation Delay adder power delay (WATT(WAT (SECOND) SECON T) D) Conventio 1.05E7.98E-09 8.37E-13
nal CMOS Full Adder 04

REFERENCES
7.25E-09 8.26E-13
[1] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, A System Perspective. Reading, MA: AddisonWesley, 1993. [2] G. M. Blair, Designing low-power CMOS,Inst. Elect. Eng. Electron Commun. Eng. J., vol. 6, pp. 229236, Oct. 1994. [3] S. Devadas and S. Malik, A survey of optimization techniques targeting low- power VLSI circuits, in Proc. 32nd ACM/IEEE Design Automation Conf., San Francisco, CA, June 1995, pp. 242 247. [4] H. J. M. Veendrick, Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits, IEEE J. Solid-State Circuits, vol. SC-19, pp. 468-473, Aug. 1984. [5] N. Weste and K. Eshragian, Principles of CMOS VLSI Design: A Systems Perspective. Reading, MA: Addison- Wesley, 1988. [6] Weste N. N. and K. Eshragian, 1993. Principles of CMOS VLSI Design: A System rspective, pp: 531. [7] Abu-Shama, E. and M. Bayoumi, 1996. A new cell for low power adders, In:Proceedings of IEEE International Symposium on Circuits and Systems, Atlanta, GA, USA, pp. 49-52. [8] Arash Shoarinejad Sue Ann Ung, and Wael Badawy, Low Power Single Bit Full Adder Cells, Can. Jl. Of Electrical and Computer Engineering, vol. 28, no. 1, pp.3-9, Jan. 2003. [9]Keivan Navi , Mohammad Reza Saatchi, Omid Daei A High-Speed Hybrid Full adder Page 88

Complem entary passtransistor Logic (CPL) Transmis sion Gate (TG) CMOS adder Transmis sion function adder (TFA) NCELL1 full adder XNOR based full adder

1.14E04

1.03E04

7.88E-09

8.11E-13

1.01E04

7.80E-09

7.87E-13

8.63E05 8.63E05

8.97E-09

7.75E-13

6.82E-09

5.89E-13

8. CONCLUSION
In this paper, the comparison of various full adder cell with XNOR based adder in term of power, delay and Volume 1, Issue 3 September-October 2012

International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com Volume 1, Issue 3, September October 2012 ISSN 2278-6856
Department of Electrical & Computer Engineering and Microelectronics Research CenterShahid Beheshti University. [10] Neda Khandel The Design of a High-Performance Full Adder Cell by Combining Common Digital Gates and Majority Function Keivan Navi Department of Electrical & Computer Engineering and Microelectronics Research Center, Shahid Beheshti University Email: {navi, mrc-ecef}@sbu.ac.ir Tel: (+98)21-29902286; [11]Mohammad Hossein & Reza Mirzaee, Keivan Nevi, Two low power high performance full adders science & research branch of Islamic Azad university,Teheran,Iran. [12]Amir ali Khatibazadeh, Kaamran Raahemifar, A study & comparison of full adder cells based on the standard static CMOS logicdept. Of Electrical & Computer Engg.,Ryerson university,Toronto, Canada.

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