Code: 9A04401 B.

Tech III Year I Semester (R09) Regular & Supplementary Examinations, November 2012 SWITCHING THEORY AND LOGIC DESIGN
(Mechatronics)

Time: 3 hours

Max Marks: 70

(a)

(b) 2 (a) (b)

Answer any FIVE questions All questions carry equal marks ***** Convert the following numbers: (i) (4567) 10 to base 8. (ii) (53.175) 10 to base 2. Represent + 25 and 25 in sign magnitude, sign -1s complement and representation. Draw three symbols and truth tables of all logic gates and explain. Develop a circuit for each of the following Boolean expression using only NAND gates: (i) Y = (A+C) (B+D). (ii)Y = AB(C+D). Simplify the function using Karnaugh map and implement logic with NAND gates only (F(W,X,Y,Z) = (1,3,7,11,15) + d(0,2,5).

(a) (b) (a) (b) (a) (b)

Implement full- adder using decoder and OR gates. Realize the Boolean function T(x, y, z) = (1, 3, 4, 5) using logic gates for hazard free. Explain the architecture of PLDs. Construct 128X8 ROM using 32X8 ROM. Draw the circuit of a negative edge triggered JK flip-flop with active high preset and clear, explain its operation with the help of truth table. Define: (i) Hold time. (ii) Setup time. Explain the following related to sequential circuits with suitable examples: State diagram. State table. State assignment. Explain salient features of the ASM chart. Draw an ASM chart and state diagram for the synchronous circuit having the following description: The circuit has a control input X. Clock and outputs A and B. If X = 1, on every clock edge (rising or falling) the code on BA changes from 00 011100 and repeats. If X =0, the circuit holds the present state. *****

7 (a) (b) (c) 8 (a) (b)

Code: 9A04401 B.Tech III Year I Semester (R09) Regular & Supplementary Examinations, November 2012 SWITCHING THEORY AND LOGIC DESIGN
(Mechatronics)

Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** Explain error correction and error detection codes with examples. Convert the following hexadecimal number to octal decimal, and binary: (i) ABCD 73. (ii) 2ACF 78. Draw the logic diagram to implement the following Boolean expressions:

Max Marks: 70

(a) (b)

(a) (b)

(i) Y = A+ B+ (A+ ). (ii) Y = A (B D) + . (iii) Y = A + CD + ABC. Express the Boolean function F = A+ C as a sum of min terms. Use the tabulation procedure to generate the set of prime implicants and to obtain all the minimal expressions for the following functions F(W,X,Y,Z) = m (0,1,4,5,6,7,9,11,15) + d (10,14).

(a) (b)

Design BCD to excesses 3 code converter using logic gates. What is meant by hazards? Explain the different types of hazards. Obtain hazard free realization circuit for the function (F(A,B,C,D) = M(0,2,6,7,8,10,12). Explain capabilities and limitations of threshold gates. Design a BCD of excesses 3 code converter using PLA. Design a MOD 6 synchronous counter using J-K flip flops. Classify the sequential circuits with one example. What are the capabilities and limitations of finite state machines? Sketch mealy circuit and explain. What is ASM chart? How it differs from the conventional flow chart? What are the symbols in ASM? Explain steps in designing the sequential circuit using ASM technique. *****

(a) (b) (a) (b) (a) (b) (a) (b)

Code: 9A04401 B.Tech III Year I Semester (R09) Regular & Supplementary Examinations, November 2012 SWITCHING THEORY AND LOGIC DESIGN
(Mechatronics)

Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a)

Max Marks: 70

(b)

Given the binary numbers a = 1010.1, b = 101.01, c = 1001.1 perform the following: (i) a+c; (ii) a-b; (iii) a.c. (iv) a/b. A receiver with even parity hamming code is received the data as 1110110 determine the correct code. What are the universal gates? Realize AND, OR, NOT, XOR gates using universal gates. Simplify the following Boolean function to maximum number of literals. (i) XYZ + +X . (ii) XY + .

(a) (b)

Simplify function using Karnaugh map method and implement them using NAND gates F(A,B,C,D) = (4,5,7,12,14,15) + D (3,8,10). Implement the following function F(A,B,C,D) = M(0,13,4,7,10,12,14) using (i) 16: 1MUX. (ii) 8: 1MUX. (iii) 4: 1MUX. (a) (b) (a) (b) Design a full adder circuit using ROM. Explain about the PAL. Draw the circuit diagram of 4 bit ring counter using D flip-flops and explain its operation with the help of bit pattern. Distinguish between translation table and excitation table. Define state equivalence and machine equivalence connection with sequential machine. Explain briefly about merger graphs. Explain salient features of ASM chart. Draw the state diagram and ASM chart for 2-bit up-down counter having mode control input M = 0 down counting, M = 1 up counting. The circuit should generate a output whenever count becomes minimum or maximum. *****

(a) (b) (a) (b)

Code: 9A04401 B.Tech III Year I Semester (R09) Regular & Supplementary Examinations, November 2012 SWITCHING THEORY AND LOGIC DESIGN
(Mechatronics)

Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) 2

Max Marks: 70

Convert the following: (i) (1234) 10 in to binary equivalent. (ii) (6547) 12 to base 16. Find the subtraction operation using 2s complement of (111001) 2 (101011) 2 . Develop a circuit for each of the following Boolean expression using only NAND gates: (i) Y = (A+C) (B+D). (ii) Y = AB (C+D). Simplifies the function using Karnaugh map method and implement them using NAND gates only. F(A,B,C,D) = (4,5,7,12,14) + D (3,8,10).

(a) (b) (a) (b)

What is a decoder? Explain 4 lines to 16 line decoder with logic diagram and truth table. What is encoder? Design a octal to binary encoder. Explain the architecture of PLDs. Tabulate the PLA programming table for the following Boolean functions (i) A(x, y, z) =m (1, 3, 5, 7). (ii) B(x, y, z) = m (2, 4, 5, 6). (iii) C(x, y, z) = m (3, 5). Design the sequence detector which detects 110010 using T flip-flops. Compare synchronous and asynchronous circuits. Give moore circuit and explain. Explain state minimization procedure. Construct an ASM block that has 3 inputs variables (A, B, C), 4 outputs. Variables (W, X, Y, Z) and 2 exit paths for this block, output Z is always 1 and W is 1 if A and B both are, if C = 1 and A = 0, Y = 1 and exit path 1 is taken. If C = 0 or A = 1, X = 1 and exit path 2 is taken. Realize the above using multiplexer and register. *****

(a) (b) (a) (b)