International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.

5, October 2012

IMPACT OF DEVICE PARAMETERS OF TRIPLE GATE SOI-FINFET ON THE PERFORMANCE OF CMOS INVERTER AT 22NM
Prathima. A1, Kiran Bailey 2 , K.S.Gurumurthy 3
1, 2

Department of Electronics and Communication Engineering, BMSCE, Bangalore

1

prathima.prathi@gmail.com 2 kiranbailey@gmail.com drksgurumurthy@gmail.com

Department of ECE, UVCE, Bangalore University, Bangalore

3

ABSTRACT
A simulation based design evaluation is reported for SOI FinFETs at 22nm gate length. The impact of device parameters on the static power dissipation and delay of a CMOS inverter is presented. Fin dimensions such as Fin width and height are varied. For a given gate oxide thickness increasing the fin height and fin width degrades the SCEs, while improves the performance. It was found that reducing the fin thickness was beneficial in reducing the off state leakage current (IOFF), while reducing the fin height was beneficial in reducing the gate leakage current (IGATE). It was found that Static power dissipation of the inverter increases with fin height due to the increase in leakage current, whereas delay decreased with increase fin width due to higher on current. The performance of the inverter decreased with the downscaling of the gate oxide thickness due to higher gate leakage current and gate capacitance.

KEYWORDS
DIBL, Process and Device simulation, SCEs, SOI FinFETs, Sub threshold Slope, TCAD

1. INTRODUCTION
Following the International Technology Roadmap of Semiconductors (ITRS), various nonclassical silicon on insulator (SOI) device structures having thin silicon bodies promise increased transistor speed, reduced power consumption and enhanced device scalability. Several innovative multiple gates SOI structures such as Double Gate (DG) MOSFET [1], fully depleted lean channel transistor (DELTA) [2] Gate All Around(GAA) MOSFET [3], Pi-gate MOSFET [4] and FinFET [5-8], have been proposed by various researchers. It is expected that sustained scaling during the next decade will see the complete evolution from the single gate (SG) conventional device to the above mentioned multiple gate MOSFETs (MuGFETs)[9]. One of the main advantages of MuGFETs is that they offer superior scalability with manufacturability of conventional planar transistors. The self-aligned gates wrapping around both sides of the fin can be fabricated with a single lithography and etch step. On the other hand, the fabrication process of MuGFETs suffers from some process challenges such as the precise control of the fin width and fin height and non-uniformity of the gate oxide on the etched sidewall of the fin, which is difficult to achieve. Similarly, the channeloxide interface condition is determined by the sidewall roughness of the fin and large parasitic resistance between the channel and source/drain is another challenge to the performance of MuGFET devices. Since real devices go through many processing steps, reliable evaluation or design optimization of final devices depend on the optimized unit process development.
DOI : 10.5121/vlsic.2012.3507 79

International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012

Technology Computer Aided Design or TCAD process simulation is therefore a prerequisite to device optimization or device design through device simulation. Due to the inherent link between process simulation and device simulation enabling the full optimization loop from unit process to device characteristics, one can correlate the electrical behavior of the device with small changes in the unit processes (e.g.time, temperature, doses, and energies). Since the process simulation enables virtual processing and in this way explores parameter space of processing options, a necessary prerequisite is that the processes to be modeled have adequately been implemented in the modeling software and that the required parameters have been calibrated.

Figure 1: 3D Cross sectional view of a 22nm triple gate SOI FinFET device. Double gate and Triple gate FinFETs are promising candidates because of their quasi-planar structure, excellent roll-off characteristics, drive current and they are close to their root, the conventional MOSFET in terms of layout and fabrication. FinFET devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling CMOS to 22 nm and below. Such devices include double gate FinFETs, Triple gate or Multigate FinFETs and allow the scaling down to sub-50nm gate length. Both logic and SRAM FinFET technologies have been previously demonstrated [10]. Previous work have shown the performance and power advantage of FinFET circuits over bulk CMOS [11-13]. FinFET technology has been used to improve the performance, standby power consumption, and variability in nanoscale-CMOS digital ICs, which find its application in SRAM Cells extensively [14]. Pei et al. [15] have presented design consideration based on 3D analytical modeling using Laplace equation. Short-channel effects (SCEs) and subthreshold behaviour of FinFETs were studied with different fin height, fin thickness and channel length. Muhammad Nawaz et [16] has evaluated the performance of 30nm SOI FinFET for different device parameters within the context of assessing the device design and underlying fabrication process. He has compared the performance of SOI FinFETs with the Bulk FinFETS for their usage in DRAM, SRAM and I/O applications [17]. Muhammad Nawaz has demonstrated SRAM cells and ring oscillators with inverter delay of 13.9 pS using metal gate SOI FinFETs [18]. To bring more functionality to a chip, the number of transistors is increased, resulting in increased power density and total power consumption. Total power consumption is dominated by active
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power during switching of a transistor. However, in deep submicrometer technology nodes, the contribution of leakage power dissipation (due to sub threshold and gate leakage) to the total power is increasing. Increased power results in high die temperatures and hence necessitates efficient cooling solutions. Aditya Bansal and Kaushik Roy have analysed FinFET based circuits for leakage and static power dissipation for thermal runaway [19,20].

(a)

(b)

Figure 2: Internal view of (a) SOI FinFET showing the Fin and (b) Poly gate wrapping around the Fin This work focuses on the implementation of a complete process flow of 22nm triple gate SOI FinFET into a commercially available numerical 3D process and device simulation environment. Modelling, Analysis and Device Characterization of the device is carried out by implementing a full process flow using a commercial three-dimensional technology CAD (TCAD) tool. The device parameters are varied and the impact of the device parameters on the performance of CMOS inverter has been presented by evaluating the inverter for static power dissipation and delay.

2. PROCESS AND DEVICE SIMULATION

The Device targeted here is 22nm triple gate SOI based FinFET. This section describes the complete modeling and simulation of the device. We also discuss the circuit performance of the device in a CMOS inverter.

2.1. Process simulation

Commercially available TCAD Sentaurus-process and Sentaurus-device simulators from Synopsys [21] have been used in this work. Semiconductor process simulation is the modeling of the fabrication of semiconductor devices. The ultimate goal of process simulation is an accurate prediction of the active dopant, stress distribution and the device geometry. The critical process steps for FinFETs on standard SOI involve fin formation, gate oxide growth, gate formation (100nm polysilicon), spacer formation (silicon nitride) and source-drain formation. No halo implants were used for setting threshold voltage in the nominal process flow. Figure 1 shows 3D cross sectional view of the triple gate SOI FinFET device with all regions. Figure 2 shows the internal view of the device showing the thin fin formed between source and drain in a NSOI FinFET. Figure also shows the patterned fin wrapped under the poly gate. Table 1 summarizes the device parameters and their dimensions for a nominal device. Process Simulation is carried out by meshing the device and generating the mesh for the further device simulation.
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Table 1: Nominal Device Dimensions

DEVICE PARAMETERS VALUE (nm) Gate length 22 Fin Width 5 Fin Height 20 Gate Oxide 1.5 Spacer Width 10 BOX Thickness 150

2.2. Device Simulation

Device simulation starts from the output of process simulation. Device simulation tools simulate the electrical characteristics of semiconductor devices, as a response to external electrical, thermal or optical boundary conditions imposed on the structure. Device simulations have been performed using Hydrodynamic carrier transport model, which solves the carrier temperature and heat flow equations in addition to the Poisson and carrier continuity equations. This model is useful in simulating devices ranging from deep submicron MOSFETs beyond the 0.18m generation and heterostructure devices. IOFF was defined at VGS=0V, and VDS=1V. Similarly, ION was defined at VGS=VDS=1V.

2.3. CMOS Inverter Realization

The performance of the SOI FinFET devices has been evaluated by implementing the devices in the basic inverter circuit comprising of a PSOI FinFET and a NSOI FinFET device with 22nm gate length. The width ratio of PMOS to NMOS is 2:1 to obtain symmetrical characteristics. The dual fin architecture provides for the necessary area factor. Mixed mode simulations are carried out to realize the inverter circuit. The Noise margins and delays are calculated from the inverters voltage transfer characteristics and transient response curves respectively. The total gate capacitance of the device is obtained by simulating the device for AC analysis and obtaining the CV (capacitance- voltage) sweep. The main aim is to control the off state leakage current and direct gate tunnelling current thereby minimizing the total static power dissipation of the circuit. The power and delays for other dimension variations are calculated analytically and analysed.

3. RESULTS AND DISCUSSION

Following the process flow, the 22nm gate length SOI FinFET is simulated for various device parameter variations and the transfer characteristics are obtained. Also the SCEs are noted for each case and analysed in this section. Figure 3 shows the transfer characteristics of the device with varying fin width for a fixed fin height and also for varying fin height for fixed fin width. As the fin widths are varied for 5, 8, 12nm and fin heights through 10, 20 and 40nm the on current and transconductance increases. On current increases linearly for thicker and higher fin devices. For example on current increases from 0.824mA to 1.08mA (31%) for a fin width increase from 5nm to 12nm for a fixed fin height of 20nm whereas increases from 0.558mA to 0.837mA (50%) for a fin height increase from 10nm to 40nm for a fixed fin width of 5nm.That is, the transconductance increases by 27.3% and 44% for fin width and fin height variations respectively. Both ION and IOFF increase with the increase in fin width. With increasing fin width, IOFF increases from 0.171pA to 3.42pA, which is because of increased short channel effects, while ION increases due to decreased external resistance and threshold voltage. The on/off-current
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behavior extracted from fin height variation shows that the on current increases quasi-linearly with fin height, while off current remains approximately unaffected at fixed fin width. For a given gate length, the simulation results show that on current is higher for taller fin devices.

(a)

(b)
Figure 3: Transfer characteristics of SOI FinFET for different (a) Fin Widths and (b) Fin heights It is found that fin width is the dominant factor that controls the short channel effects. Figures 4 and 5 show the SCE behavior for fin width and fin height variations. Figures show off state leakage current (IOFF), threshold voltage (VTH), drain induced barrier lowering (DIBL), sub threshold voltage slope (SS) and gate leakage current (IGATE) behavior for varying fin widths and fin heights. We observe that the subthreshold slope, drain induced barrier leakage and IOFF are quite sensitive to the variation in fin width. For example DIBL and SS change from 33 to 59mV/V (69%) and 63.7 to 69.8 mV/dec (8.2%) respectively, with fin width variation from 5 to
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12nm at 20nm fin height. The threshold voltage decreases from 0.707V to 0.689V (2.6%), when fin width is increased from 5nm to 12nm for an NSOI FinFET.

(a)

(b)

(c )

(d)

(e)
Figure 4: Impact of Fin width on (a) IOFF behavior, (b) Threshold Voltage, (c) DIBL, (d) Subthreshold Slope and (e) Gate leakage current. As ultra thin oxide is needed for scaled sub-50nm MOSFETs, direct tunneling current results in exponential increase in the gate leakage current, increased power consumption and hence deterioration in the device performance. The SCE behaviour of the devices for different oxide thickness of 1,1.5 and 1.8 nm at fixed fin width and fin height, are reported in Figure 6. As the gate dielectric gets thinner, the gate voltage controls the channel more effectively. The effect of DIBL and SS also reduces with thinner gate oxide.A quasi-linear decrease in DIBL and SS was observed with varying gate oxide from 1.8 to 1 nm. DIBL and SS change from 36 to 28mV/V(28.5%) and 64.3 to 62.7 mV/dec(2.5%), respectively, with gate oxide thickness
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reducing from 1.8 nm to 1nm at fixed fin width and fin height for a N type FinFET.The threshold voltage decreases by 1.6% i.e 0.1V decrease for approximately 1nm reduction in gate

(a)

(b)

(c )

(d)

(e) Figure 5: Impact of Fin height on (a) IOFF behavior, (b) Threshold Voltage, (c) DIBL, (d) Subthreshold Slope and (e) Gate leakage current. oxide thickness.On current and transconductance increases with decrease in gate oxide. On current increases from 742A to 928A (25%) for reduction of gate oxide thickness from 1.8 to 1nm.The most important factor being the direct gate tunneling current, increases from 0.1pA to 2.68 nA i.e by 3 orders of magnitude (2.6*103 ) when the gate oxide is reduced from 1.8nm to 1nm for a NSOI FinFET. The off current reduces with decrease in oxide thickness.Though the other SCEs reduce, the leakage factor is the dominant factor which limits the continuous scaling of the gate oxide thickness ,which leads to high static power dissipation.
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(a)

(b)

(c)

(d)

(e) Figure 6: Impact of Gate oxide thickness on (a) IOFF behavior, (b) Threshold Voltage, (c) DIBL, (d) Sub threshold Slope and (e) Gate leakage current. We have studied the impact of the device parameter variations on the performance of CMOS inverter (Static power dissipation and Delay). We evaluated the delay (Td) and the static power dissipation (Pstatic) for an inverter with nominal values and also for other parameter variations. Delay is better figure of merit, since it takes into account the capacitance associated with the structure as well as the current drivability. [22, 23] The delay associated with inverter, Td is given by the equation Td= Cgg*VDD/ION , where Cgg is the total gate capacitance which can be obtained by the CV sweep of the devices and VDD is the supply voltage (1 volt). We have calculated the rise time delay (Trd ) with respect to on current of the P-device and fall time delay (Tfd) with respect to the on current of the N-device in each case of variation.
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Power dissipation of any logic gate can be expressed as: Ptotal = Pdyn + Pstatic , where Pdyn represents dynamic power dissipation due to charging, discharging of capacitances when the output signal of a logic gate makes a transition. Pstatic is the static power consumption due to the leakage current whose major components are the subthreshold leakage (IOFF), gate direct tunneling leakage (IGATE), and junction band-to-band tunneling leakage (Ibtbt) [24]. Hence Static power dissipation of the inverter is given by: Pstatic = VDD * Istatic = VDD * (IGATE + IOFF +Ibtbt). In double gate and triple gate SOI devices such as FinFETs, static power consumption is dominated by the subthreshold leakage and gate tunneling leakage. [25] In our FinFET devices, the body is left undoped, and the band-to-band tunneling leakage (Ibtbt) becomes negligible. Static power consumption is a strong function of temperature, while dynamic power consumption is weakly coupled with temperature variation, hence we do not consider these components (Pdyn and Ibtbt ) of leakage in this paper. Figure 7 shows the Voltage Transfer characteristics (VTC) and Transient response of a Basic Inverter with nominal device dimensions. The noise margins for the inverter were calculated from the graphical method. The high level noise margin ( NMH) and low level noise margin (NML) was found to be 0.509Volts and 0.492 volts respectively. AC analysis was performed for a PSOI FinFET to obtain the total gate capacitance. The gate capacitance of the NSOI FinFET device is half of its counter part and hence total gate capacitance of the inverter is calculated. The gate capacitances for the other variations are calculated analytically, which is given by the equation, Cgg = ox/tox*Gate Area, where ox is the permittivity of the gate oxide and tox is thickness of the gate oxide. As gate area or oxide thickness varies, capacitance also varies. Table 2: Static power dissipation and Delay in an Inverter varying with Fin width for VDD = 1volt

Table 2 summarizes the static power dissipation and delay of inverters for nominal fin width and for inverters whose fin widths are varied. We observe that though the total gate capacitance (Cgg) increases with increase in fin width, the rise time and fall time delays reduce which is due to higher on currents for thicker fins. The rise time and fall time delays reduce by 13.5% and 14.5% respectively, as the Fin width is increased from 5 to 12nm. There is marginal variation in static power dissipation (Input=1) as the fin widths are varied by a smaller factor.

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Figure 7: Voltage transfer characteristics of a static CMOS Inverter (top) and Transient response of the Inverter (bottom) Similarly Table 3 summarizes the static power dissipation and delay of inverters for different fin heights. The static power dissipation increases by 2.5 times (77%) and delays increase by 3.6 times when the Fin height is increased from 10nm to 40nm. Increase in power dissipation is due to increasing leakage currents (Gate leakage and IOFF) with Fin height, whereas increase in delay is due to increasing gate capacitance with gate area.
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Table 3: Static power dissipation and Delay in an Inverter varying with Fin height for VDD = 1volt

The static power dissipation and delay of inverters for different gate oxide thickness are tabulated in Table 4. The Static power dissipation increases exponentially from 0.15pW to 2.68nW (18*103 times) for approximately 1nm reduction in gate oxide thickness. This is primarily due to large gate leakage current in ultra thin oxides. We also observe that gate delay increases by 46% with reduction in gate oxide thickness from 1.8nm to 1nm. This is due to the large gate capacitances associated with thinner oxides. Hence the overall performance of the inverter is not improved with the scaling of the gate oxide thickness. Table 4: Static power dissipation and Delay in an Inverter varying with gate oxide thickness for VDD = 1volt

3. CONCLUSIONS
A full process flow for a 22nm triple gate SOI FinFET has been implemented in this work. Various device parameters such as Finwidth, Fin height and Gate oxide thickness have been varied and the impact of these device parameters on the static power dissipation and delay of a CMOS inverter are presented. For a given fin thickness and increasing fin height, the threshold voltage, off-current, delay and SCEs remain approximately insensitive, while the on-current and transconductance increases approximately linearly with the increase in fin height. On the other hand DIBL, SS and off-current ( IOFF) are quite sensitive to the variations in fin width at fixed fin height. We found out that gate leakage increased exponentially with decrease in gate oxide thickness. The rise time and fall time delays of the CMOS inverter reduced by 13.5% and 14.5% respectively, as the Fin width is increased from 5nm to 12nm, showing improved performance in terms of delay. When the fin height is increased from 10nm to 40nm, the static power dissipation increased by 2.5 times (77%) and delays increased by 3.6 times. We observed increase in the Static power dissipation from 0.15pW to 2.68nW (18*103 times for Vin =1) for approximately 1nm reduction in gate oxide thickness and increase in gate delay by 43.2% and 45.8%(Fall time delay and Rise time delay) with reduction in gate oxide thickness from 1.8nm to 1nm.Hence performance of the inverter degrades by increasing the Fin Height and with reduction in gate oxide thickness. Better Figure of merit in terms of delay is obtained with increase in Fin width. Keeping device scalability in mind, simulated device parameters like Static power dissipation, delay and capacitances based on realistic process flow provide a useful guide to the circuit
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designer for low power, analog, RF and digital applications. Further scope of work may include improving the performance of inverter for other device design considerations.

ACKNOWLEDGEMENTS
This research is supported by the BMS College of Engineering, Bangalore.The authors wish to thank BMS college of Engineering for supporting this work by encouraging and supplying the necessary tools.

REFERENCES
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Authors
Prathima. A received her B.E degree from BMS College of Engineering of Visvesvaraya Technological University, Belgaum 2004.Her areas of interest are VLSI design and VLSI circuits. She is presently a post graduate student(M.Tech-Electronics) from B.M.S. college of Engineering of Visvesvaraya Technological University.

Kiran Bailey received her B.E degree from Dayananda College of Engineering of Bangalore University, Bangalore in the year 1997. She got her M.Tech degree from B.M.S. college of Engineering of Visvesvaraya Technological University, Bangalore in 2001. She joined BMSCE in 1998 and has since been teaching Electronics related subjects. Her areas of interest are solid state devices, VLSI design, Low power VLSI circuits. Presently she is an Assistant professor in the dept. of E&C, BMSCE, Bangalore Dr. K.S. Gurumurthy (M2000) obtained his B.E degree from M.C.E Hassan of Mysore University in the year 1973. He got his M.E Degree from University of Roorkee (now IIT-Roorkee) in 1982. He joined UVCE in 1982 and he has since been teaching Electronics related subjects. He obtained his PhD degree in 1990 from IISc Bangalore. He is a University gold medal winner from University of Roorkee and a recipient of the Khosla award for the best technical paper published in 1 982. His interests are Low power VLSI, Multi valued logic circuits, Deep submicron Devices. Presently he is a professor in the DOS in E & CE Dept., UVCE, Bangalore University, Bangalore

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