Project 2

Design of Reconfigurable Digital Machines

ECE 5570 Design of Reconfigurable Digital Machines Design of 16 Bit RISC Processor

Chandra Shekar Patil

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Contents 1) Project Objectives 2) RISC Processors 3) Instructions a) Instruction Set I. Execute instructions II. Internal Register Instructions III. External Memory Instructions IV. Branch Instructions 4) Block Diagram a) Arithmetic Logic Unit b) Register Banks c) Control and Status Registers d) External Bus Interface 5) Integrated State Machine 6) Conclusion 7) Appendix a) VHDL Code b) Design Summary c) User Constraint File d) Pin Out Report

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1. Project Objectives The objective of the Project 2 is to design, simulate, build, and demonstrate the correct operation of a simple 8-bit RISC processor core along with an external bus to facilitate testing and debugging. The Implemented RISC Processor shall contain the following feature The list of commands to be implemented is specified in table 1. No interrupts will be available. The instructions must consist of either two, or four 8-bit words. The number of memory cycles to fetch and execute an instruction must be limited to six The Control Unit finite state machine FSM should have the following states: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), Write Result (WR). A virtual program/data memory should be implemented on the solder-less breadboard using DIP-switches and Bar-LEDs. A single-step logic module should be added to your processor in order to facilitate debugging and the demonstration of the performance of your design.

2. RISC Processors RISC stands for Reduced Instruction Set Code, IBM Introduced the first RISC architecture in 1970s. As the name indicates the RISC processors have reduced number of instruction code, in the sense there are few basic instructions than many instructions doing complicated process. These controllers are used in various applications due to their speed and simplicity. In this project we design a 16 bit RISC processor which borrows some ideas from 32 bit controllers from Rensas technology.

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3. Instructions The instructions set for the 16 bit processor are designed as shown in the figure 1. The op-code is 16 bit wide and the immediate data input is also 16 bit wide. As code shown in the figure.1 the most significant 4 bits and the least significant 4 bits plays major role in determining the type of the instruction. The instruction set is designed in such a way that no two instructions share a common op op-code and each instruction are very unique.

Figure 1 Op Op-code format (16 bit) MSB: Most significant bit of the opcode it is a hex number specific to the each instructions mmmm: Is a hex number which denotes the destination register in most of the operations where registers are involved, otherwise it is a constant hex number for op-code which does not inv code involve registers like CMP instruction. nnnn: Is a hex number which represents the register number which will be used as a secondary register for the particular operation like LSL instruction. ter instruction. zzzz: Is a hex number which represents the second register used in a particular operation like ADD instruction Table 1 gives more details about individual code design.

a. Instructions Set The instruction set are divided in to 4 different categories such as I. II. III. IV. Execute instructions Internal Register Instructions External Memory Instructions l Branch Instructions

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Clas sify EX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MT 16 17 18 19 LS 20 21 22 23 BR 24 MOV LDIL LDIH NOP 0MN5 0M30 0M40 9000 0000_mmmm_nnnn_010 1 0000_0mmm_0011_0000 iiii_iiii_iiii_iiii 0000_1mmm_0100_0000 iiii_iiii_iiii_iiii 1001_0000_0000_0000 Move Rm, Rn Mnemonic HEX Op-code (16 bits) Name

Design of Reconfigurable Digital Machines

Function States No memory access IF/ID/EX IF/ID/EX IF/ID/EX IF/ID/EX IF/ID/EX IF/ID/EX IF/ID/EX IF/ID/EX IF/ID/EX IF/ID/EX IF/ID/EX IF/ID/EX IF/ID/EX IF/ID/EX IF/ID/EX No memory access IF/ID/EX IF/ID/EX IF/ID/EX IF/ID/EX Memory Access IF/OF/ID/EX IF/OF/ID/EX IF/OF/ID/EX /WR IF/OF/ID/EX /WR PC, SPC, PSW IF/ID/EX Flags OVF,S,Z,CY, BR,M

CMP CLR AND OR XOR INC ADD ADC SUB SUBB LSL LSR ASL ASR MUL

0M00 0M10 1MNZ 2MNZ 3MNZ 0M20 4MNZ 5MNZ 6MNZ 7MNZ 0MN1 0MN2 0MN3 0MN4 8MNZ

0000_mmmm_0000_0000 0000_mmmm_0001_0000 0001_mmmm_nnnn_zzzz 0010_mmmm_nnnn_zzzz 0011_mmmm_nnnn_zzzz 0000_mmmm_0010_0000 0100_mmmm_nnnn_zzzz 0101_mmmm_nnnn_zzzz 0110_mmmm_nnnn_zzzz 0111_mmmm_nnnn_zzzz 0000_mmmm_nnnn_000 1 0000_mmmm_nnnn_001 0 0000_mmmm_nnnn_001 1 0000_mmmm_nnnn_010 0 1000_mmmm_nnnn_zzzz

Complement Rm Clear Rm AND Rm,Rn,Rz OR Rm,Rn,Rz XOR Rm,Rn,Rz Increment Rm Add w/o carry Rm, Rn, Rz Add w/ carry Rm, Rn, Rz Subtract w/o borrow Rm, Rn, Rz Subtract w/ borrow Rm, Rn, Rz Logic shift left Rm, n Logic shift right Rm, n Arithmetic shift left Rm, n Arithmetic shift right Rm, n Signed multiply Rm, Rn, Rz

Rm:= not(Rm) Rm:= 0 Rm:= Rn and Rz Rm:= Rn or Rz Rm:= Rn XOR Rz Rm:= Rm PLUS 1 Rm:= Rn + Rz Rm:= Rn + Rz + CY Rm:= Rn - Rz Rm:= Rn Rz - BW Rm:= LSL(Rm), n Rm:= LSR(Rm), n Rm:= ASL(Rm),n Rm:= ASR(Rm),n Rm:= Rn x Rz

OVF,Z,S OVF,Z,S CY,Z,S OVF,Z,S BR,Z,S Z,S Z,S Z,S Z,S Z,S

Rm:= Rn Rm:= #imm Rm:= #imm Do nothing

Load Rm (R0 to R7), imm Load Rm (R8 to R15), imm No operation

LDR LDD STR STD

0MN6 0MN7 0MN8 0MN9

0000_mmmm_nnnn_011 0 0000_mmmm_nnnn_011 1 0000_mmmm_nnnn_100 0 0000_mmmm_nnnn_100 1 1001_0001_0000_0000 dddd_dddd_dddd_dddd 1001_0010_0000_0000 dddd_dddd_dddd_dddd 1001_0011_0000_0000 dddd_dddd_dddd_dddd 1001_0100_0000_0000

Load Rm, mem(Rn) Load double Rm, mem(Rn) Store Rm, mem(Rn) Store double Rm, mem(Rn) Conditional branch (F), addr Branch, addr Branch to subroutine, addr Return from subroutine

Rm:= mem(Rn) Rm:= mem(Rn) double mem(Rn):= Rm mem(Rn):= Rm double PC:=addr if F=1, otherwise update PC PC:= addr SPC:=PC, SPSW:=PSW, M=1 PC:=SPC, PSW:=SPSW, M=0

CBR

9100

25 26 27

BRA BRS RTS

9200 9300 9400

IF/ID/EX IF/ID/EX IF/ID/EX M=1 M=0

Table 1: Instruction Set

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Design of Reconfigurable Digital Machines

I.

Execution Instructions This set of instructions 1 to 15 Table 1 do not need any memory access and execute the operation in just Execute State of the state machine. Figure 2 shows the post route simulation for one of this instruction CMP, the operation is performed on register 7. First the register 7 is loaded a data followed by register 8 and the register 7 is complemented. The wave form contains the following signals, /stm_prt/CLK : Clock input /stm_prt/ack : acknowledgement from the memory unit /stm_prt/ex_ctrl : internal execute control signal /stm_prt/da_i : data line /stm_prt/in_fet_opcode: internal op-code information (op-code and operand) /stm_prt/in_de_opcode: Op-code /stm_prt/in_de_imm: Immediate data /stm_prt/in_de_m: target output register /stm_prt/in_de_n: secondary register 1 /stm_prt/in_de_z: secondary register 2 /stm_prt/rm: Resltant data to be stored in Rm /stm_prt/in_exe_bank1(m): Individual register m in bank 1

Figure 2 II. Memory Transfer Instructions: The memory transfer Instructions loads an individual memory register with the immediate data (LDIL, LDIH). This group also contains instruction to transfer memory in between individual registers- MOV. As shown in the figure 2, both LDIL and LDIH instructions are executed, as described in the waveforms, the data 5555 is loaded in to the register 7 using LDIL instruction and further LDIH instruction is executed to load the data 7856 in to register 8.

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Design of Reconfigurable Digital Machines

III.

Load & Store Instructions. This instruction group contains instruction used to read and write data into the external memory. These instructions contain the 16 bit address of the target memory in the nnnn register. Figure 3 shows the detailed waveforms of the LDD instructions, this instruction will load the double data into the register pair specified mmmm. In this case R7 will contain the address of the memory, when LDD is executed the data from the memory location specified in R7 i.e. CCBB and the next location which is AA55 are loaded in to R6 and R5 respectively

Figure 3 IV. Branch Instructions This group consists of instructions necessary to take the program execution sequence to a different memory locations, this group contains conditional and unconditional branch statements. Other than branch this group also contains the RTS statement. Figure 4 shows the instructions executed in the below sequence > BRS 0x7787 (PC = 0000) Contents after execution. > LDIL R7 0xFFFF (PC = 7768) > LDIH R7 0xA55A (PC = 7769) > INC R7 (PC = 776A) > RTS (PC = 0001)

Figure 4 Also in the above figure it could be observed that the bank 2 registers are used while in subroutine.
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Design of Reconfigurable Digital Machines

4. Block Diagram
The design of the RISC processor core consisted of several parts that worked in tandem to produce the t desired result. The block diagram of the design is as shown Figure 5

Figure 5 Control Logic perations Drives the operations of the RISC processor, the control logic contains a finite state machine whose operation is explained in Section 5. The control logic contains two blocks i.e. Instruction Decoder and External Bus Interface Instruction Decoder: The instruction decoder is responsible to decode the machine Hex code, this blocks output determine the further operations to be performed. This result is interpreted by the control logic which would formed. determine the states of the I/O signals of this block. External Bus Interface This block facilitates the reading from and writing to Interface: acilitates external memory by using signals that c communicate with the control logic. h logic External memory address is represented by switches and LEDs. An ACK# switch facilitates single single-stepping

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CPU The CPU operation can be broken down in to the following basic blocks. Register Bank: The RISC processor contains two sets of register bank the register banks are toggled based on the sub routines. The bank 1 is the main register bank and it is used as the target register bank while the program flow is in main control, the processor switches to the bank 2. The switches size of the registers is 16 bit each. Control Registers: The control registers contain two 16 bit registers which keeps the track of the program counter(PC) and the program status word (PSW). The PSW registers contain the status of the previous airthmatic or the logic operations. ALU: The arithmetic logic unit consists of blocks which are used to perform operations like OR, AND, XOR and arithmetic blocks like adder, sub tractor and multiplier. The ALU block is invoked by the control logic based on the logic instruction decoders output.

Integrated State Machine: The finite state machine designed has the states as described in the Figure 6

Figure 6
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Design of Reconfigurable Digital Machines

Below are the states for the finite state Machines Instruction Fetch (IF): In this state the instruction is fetched from the external data bus and passed on to the next state as shown in the Figure 7. Instruction Decoder (ID): The instruction decode state decodes the instructions and pass it on to the next state, based on the type of instruction the next state is decided. For example if the instruction required a immediate data then the OPC state is executed otherwise the next state will be EX. Op-Code Fetch OPC: This state is reached if only the processor requires additional data as input. After this state the fetched data will be passed on to the next state which is EX. Execute EX: This state executes the operation based on the instructions; this state invokes the CPUs components as required by the opcode. Write WR: The WR state will write data on to the external memory, this state is invoked if the instruction requires external memory operation.

6. Conclusion The 16 bit RISC processor was successfully implemented, we had difficulty in getting the external bus signal right. The major challenge faced in this project was the implementation of state machine. As a part of learning we understood the internals of a RISC processor and its configuration of internal blocks for example: The integration of the Instruction Decoder to the control logic and also we understood how the state machine could be used to implement the processor logic.

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Appendix

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