MC0030 ADVANCE COMPUTER ARCHITECTURE

[1 mark each] 1. Computer architecture is abstracted by its ___________. a. Instruction b. Instruction set c. Organization d. None of the above 2. Instruction sets includesa. Opcode b. Addressing modes c. Registers d. All of the above 3. Sequential computer was improved from bit serial toa. Bit-parallel b. Byte serial c. Word-parallel d. None of the above 4. The Von Newmann architecture is slow due to _________ execution of instructions in a program. a. Sequential b. Parallel c. Non-execution d. None of the above 5. The term computer architecture was coined ina. 1972 b. 1978 c. 1964 d. 1968 6. _______ levels can be used for describing a computera. 1 b. 2 c. 3 d. 4

7. _______ Model is more suitable for special purpose computations. a. SIMD b. MISD c. MIMD d. Both a and b 8. Hazards in pipelines can make it necessary to _________ the pipeline. a. Stall b. Stake c. Storm d. None of the above 9. When a machine is pipelined, the _________ execution of instructions requires pipelining of functional unit. a. Overloaded b. Over ridded c. Overlapped d. Over crowded 10. The ratio which stays constant as performance and cost is increased by equal factors is called asa. Performance Ratio b. Cost Ratio c. Cost-Performance Ratio d. All of the above 11. The cost-performance ratio is a good indicator of _________ quality for small changes. a. Relative b. Absolute c. Absolute relative d. All of the above 12. The processors in a multiprocessor system communication with each other through _________.

a. Shared memory b. Shared variable in a common memory c. Both a & b d. None of the above 13. Interprocessor communication is done through __________ among nodesa. Shared variable b. Shared memory c. Message passing d. None of the above 14. Explicit vector instructions were introduced with the appearance of _____________. a. Processors b. Micro processor c. Intel processors d. Vector processors 15. An SIMD computer exploits ___________ parallelisma. Spatial b. Temporal c. Both a & b d. None of the above 16. Associate memory can be used to build __________ associative processors. a. SISD b. SIMD c. MISD d. MIMD 17. ___________ architecture supports the pipelined flow of vectors operands directly from the memory to pipelines and then back to memory. a. Memory to memory b. Register to memory c. Memory to register d. Register to register 18. ___________ Architecture uses vector registers to interface between the memory and functional lines. a. Memory to memory

b. Register to memory c. Memory to register d. Register to register 19. There are _______ families of pipelined vector processors. a. 1 b. 2 c. 3 d. 4 20. At the system level the description of the ___________ architecture is based on processor level building blocks. a. Abstract b. Concrete c. Encapsulated d. None of the above 21. The _________ architecture of a processor of ten referred to as simply the architecture of the processor. a. Abstract b. Concrete c. Encapsulated d. None of the above 22. ________ classification shows the architectural evolution from sequential scalar computers to vector processors and parallel computers. a. Von-Neumanns b. Nyquists c. Flynns d. None of the above 23. Pipelining offers an economical way to realize _____________ parallelism in digital computers. a. Spatial b. Temporal c. Concurrent d. None of the above 24. The concept of _________ processing in a computer is similar to assembly lines in an industrial plan.

a. Vector b. Sequential c. Pipeline d. None of the above 25. __________ are streamed into the pipe and get executed in an over-tapped fashion at the subtask level. a. Successive tasks b. Independent tasks c. Concurrent tasks d. All of the above 26. Weather modeling is ____________ numeric computation. a. Structured b. Unstructured c. Highly-structured d. None of the above 27. CPI stands fora. Clock cycles per instructions b. Click per instructions c. Cycles per inch d. None of the above 28. Pipelining yields a reduction in the ________ per instruction. a. Fetching Line b. Executions tine c. Average execution time d. None of the above 29. Pipelining _________ the clock cycle time. a. Decreases b. Increases c. Stabilizes d. None of the time 30. In __________ pipeline all tasks have equal processing time in all station facilities. a. Delay b. Uniform-delay c. Non-uniform delay

d. None of the above 31. CPU of a modern digital computers can generally be partitioned into ________ sections. a. 1 b. 2 c. 3 d. 4 32. Partitions of CPU isa. Instructions unit b. Instruction queue c. Execution unit d. All of the above 33. __________ is a faster storage of copies of programs and data. a. RAM b. ROM c. CACHE d. Hard disk 34. Programs and data reside in the __________, which usually consists of interleaved memory modules. a. Hard disk b. Main memory c. Cache d. ROM 35. ________ are fast registers for holding the intermediate results. a. Latches b. J.K c. RS d. Master slave 36. The instruction queue is ________ storage areaa. FIFO b. LIFO c. FILO d. All of the above

37. ___________ may contain multiple functional pipelines for arithmetic logic functions. a. Instruction queue b. Instruction unit c. Execution unit d. All of the above 38. ____________ Hazard in pipelines is caused by resource conflicts. a. Structural b. Data c. Control d. None of the above 39. __________ hazards arises when an instruction depends on the results of a previous instruction in a way that is exposed by the overlapping of instructions in the pipeline. a. Structural b. Data c. Control d. None of the above [2 marks each] 40. _________ hazards arise from the pipelining of branches and other instructions the change the PC. a. Structural b. Data c. Control d. None o the above 41 Computer has gone through two major stages of development ___________ & ______________. a) Mechanical & Electrical b) Pipelining & Distributed c) Electrical & Concurrency d) Pipelining & Mechanical 42 The study of Computer architecture involves both _-- organization and _________ requirements. a) Hardware & Software b) Register & Addressing Modes c) Assembly & operation codes d) Software & CPU

43 The term Computer Architecture was coined in ___________ by the Chief architects of the ______________ a) 1974, 360 System b) 1965, AT & T c) 1964, IBM System d) 1984, ENCI System 44 True/False 1. The sequential computer was improved bit-serial to word- parallel operations 2. The von-Neumann architecture is fast due to sequential execution of instructions in Program. a) b) c) d) Only 1 Only 2 Both 1 & 2 None of the above

45 The study of architecture covers both __________ and __________________. a) Evolutional, Revolution b) IBM System, Revolution c) Instruction-set architecture, Machine implementation organizations d) Evolutional, IBM System 46 ________________ Architecture supports the pipelined flow of vector operands directly from the memory to Pipelines and then back to the memory. ________________ Architecture uses vector registers to interface between the memory and functional Pipelines. a) Memory to-register, Register to Register b) Memory to-Memory, Register to Register c) Memory to-Pipelines, Register to Memory d) Memory to-register, Register to Pipelines 47 ______________ offers an economical way to realize temporal parallelism in ___________ computers. a) Pipelining, Super b) Pipelining, Digital c) IBM System, Super d) Evolutional, Digital 48 True/False 1. Pipelining is an implementation technique where multiple instructions are overlapped in execution. 2. A Pipeline is a complier line. a) Only 1 b) Only 2 c) Both 1 & 2

d) None of the above 49 ___________ is a faster storage of copies of programs & data, which are ready for execution. The Cache is used to close up the speed gap between Main memory and the ___________. a) Cache Memory, CPU b) CPU, Cache Memory c) Primary Memory, Cache Memory d) None of these 50 There are three classes of Hazards ________, _________ & ___________. a) Structural Hazards, Data Hazards, Control hazards. b) Pipeline, System hazards, Data hazards c) Linear, Uniform Linear, Cache d) Pipeline, Linear, Cache 51 ____________ Complier must be developed to detect : The concurrency among vector instructions, which can be realized with pipelining. A ________ complier would regenerate parallelism lost in the use of sequential languages. a) Intelligent, Vectorizing b) Vectorizing, Intelligent c) Parallel, Pipeline d) Cache Memory, data hazards 52 A ___________ scheduling model is presented for multi-pipeline vector processes. A long vector task can be partitioned into many ___________. a) Parallel task, Sub vectors. b) Sub vectors, parallel task c) Vectors, Pipelining d) None of these 53 The instruction Processing Unit fetches and decodes __________ and __________ instructions. a) Vector, Sub vector b) Pipelines, parallel task c) Scalar, Vector d) Pipelines, Scalar 54 The super scalar issue was first formulated as early as ________. The super scalar processors have to issue multiple instructions per cycle, the first task necessarily is ___________. a) 1970, parallel decoding b) 1975, Pipelines c) 1980, CISC processors d) None of these

55 Super scalar instruction issue comprises two major aspects a) Pipelines, Superscalar b) Vector, Sub vector c) Issue Policy, Issue Rate d) None of these 56 Super scalar processors have introduced intricate instruction issue policies, involving advanced techniques such as : a) Shelving, Register naming, Speculative branch processing b) Parallel decoding, Register naming, Shelving c) Design space, Issue Policy, Issue Rate d) None of these 57 Issue Policy consists of four major aspects : 1. Coping with false data dependencies 2. Use of shelving 3. Handling of issue blockage 4. Copying with unresolved control dependencies. 5. Register renaming a) 1,2,3,4 b) 2,3,4,5 c) 1,3,4,5 d) 1,2,4,5 58 Which is True 1. A large number of instructions typically from 100 to 250 instructions 2. Some instructions that perform a specialized task and are used infrequently. a) Only 1 b) Only 2 c) Both 1 & 2 d) None of these 59 A __________ machine with memory Memory 1. operations can easily be substituted by the complier and used as a register register machine. 2. _____________ processors have fewer and simpler instructions than CISC processors. a) GPR, RISC b) RISC, GPR c) CPU, CISC d) RISC, CPU 60 Which specific task is not included in superscalar processing? a) Parallel decoding b) Superscalar instruction c) Parallel instruction d) Pipelines

[4 marks each] 61 Computer architecture is abstracted by its instruction set, which includes ________, __________, _____________ & __________________ a) opcode, addressing modes, registers, virtual memory b) Pipelining, Rectorization, concurrency, opcode c) Addressing modes, Pipelining, Register, opcode d) Register, virtual memory, rectorization, pipelining 62 Computer architecture identified four levels that can be used for describing a computer these are the ___________ level, _____________ level, _____________ level & __________ level. a) Electronic-circuit, Logic design, Programming, Processor-MemorySwitch(PMS) b) Logic Design, PMS, IBM system, parallel Computing c) Vector Processors, PMS, Logic Design, Programming d) Logic Design, IBM system, parallel Computing, Vector processor 63 Parallel Computers are those that executes programs in ________ mode. There are two major classes of parallel computers namely ____________ multi- processors and _________ multi computers a) MIMD, Shared Memory, message parsing b) IBM, Pipelining, Message parsing c) SIMD, vector, spatial parallelism d) MIMD, message-parsing, IBM System 64 The technology of parallel processing is the outgrowth of four decades of research and industrial advances in a) Memory Systems, Peripheral devices, Operating system b) Application Programs, System Programs, OS c) Language evolution, System Programs, OS d) High level language, language evolution, System Programs 65 High performance computers provide fast and accurate solutions to : a) Scientific, business, Social, Defense problems b) Pipelines, Business, System Programs c) Education, business, Railways, Trade d) Social, Education, Trade, research 66 Representative Real life problems include: a) Large-scale database management, AI b) High level programs, Crime, Control c) DBMS, AI, Circuits 67 Which statement is correct : 1. In a computer pipeline, each step in the pipeline completes a part of an instruction

2. The assembly line, different steps are completing different parts of different instruction in parallel a) Only 1 b) Only 2 c) Both 1 & 2 d) None of these 68 1. In a __________ all tasks have equal processing time in all station facilities. 2. __________ can process a succession of sub tasks with a linear precedence graph. 3. __________Stages are pure ___________ circuits performing arithmetic or logic operations over the data stream following through the pipe. a. Uniform delay, 2-Linear, 3-Processing. Combinational b. Linear 2-Uniform delay, 3-High level, Sequential c. Uniform delay, 2-Procedurer, 3-Processing. Combinational d. Procedure, 2-Linear, 3-OS, combinational 69. Which statements is correct 1. The latches are fast registers for holding the intermediate results between the stages 2. A linear pipeline can process a successive of sub tasks with a non-linear precedence graph. a. Only 1 b. Only 2 c. Both 1 & 2 d. None of the above 70. The Central Processing Unit (CPU) of a modern digital computer can generally be partitioned into three sections a) The Instruction unit, The instruction queue, The execution unit b) Uniform-delay, Procedure, Linear c) Processing stage, Combinational, Processing Unit d) None of these 71. 1. _____________ that prevent the next instruction in the instruction stream from executing during its designated clock cycle. 2. __________ arise from the pipelining of branches and other instructions that change the PC. (a) Hazards, Control hazards (b) Structure hazards, control hazards (c) Structure hazards, data hazards (d) Hazards, structure hazards 72. Which is true A. For tthe pipelines when an instruction is installed, all instructions issued. B. Hazards in the pipelines can make it necessary to stall the pipelines C. New instructions are fetched during the stall D. Control Hazards can cause a greater performance loss than the data hazards

)a )b )c )d

A&B A, C, & D only A, B & D Only Except A all

73. 1. ___________ contains an ordered set of n elements, where n is called the _________ of the vector 2. A __________ instruction will shorten a vector under the control of a masking vector. 3. A ____________ instruction combines two vectors under the control of a masking vector. a. vector operand, length, 2- compress, 3- merge b. Boolean operand, vector, 2- compress, 3- merge c. vector operand, vector, 2- compress, 3- merge d. vector compress, length, 2- Boolean , 3- merge 74. 1.__________ are repeatedly invoked many times, each of which can be sub divided into sub processes. 2. __________ are fed through the pipeline segments and require as few buffers and local controls as possible. 3. ___________ executed by distinct pipelines should be able to share expensive resources, in the system a. Identical processes, 2- successive operands, 3- operations b. successive operands, 2- Identical processes,3- operations c. Vector, 2-Identical processes, 3- successive operands d. Boolean vector, 2- successive operands, 3- Identical Processes 75. Which statement is correct : 1. The address increment between the elements must be specified. 2. A Masking vector may be used to mask off some of the elements without changing the contents of the original vectors 3. Microcode control is used to set up the required resources. 4. Memory-to Memory architecture, in which source operands, intermediate and final results are retrieved directly from the main memory a. 1, 2 & 4 only b. 1,2, 3 & 4 c. 1, 2 & 3 only d. Except 1 All 76. ________ is a standard technique for removing false date dependencies. __________ & ______ dependencies, among register data. a) Register naming, WAR, WAW b) WAR, WAW, shelving c) Register naming, shelving, WAW d) None of these