Design Issues in CMOS Oscillators

D. Solanki#1, R. Chandel#2, T. Alam #3, A.K. Nishad 4

Electonics and Communication Department, National Institute of Technology Hamirpur, Hamirpur (H.P.)-177005 India
1

mr.dhrubsolanki@gmail.com 2 rchandel@nitham.ac.in
4

talam.nith@gmail.com atulnishad@hotmail.com

Abstract An analysis of phase noise in differential crosscoupled inductancecapacitance (LC) oscillators is presented. An analysis of phase noise in differential cross-coupled LC oscillators was presented. The VCO was implemented in a 0.18m CMOS process and verified in simulations using TANNER SPICE. A 123 MHz LC oscillator using CMOS technology 600 kHz while dissipating 21.54 W of power. Keywords Inductance Capacitance-Voltage Oscillator, Ultra-wideband frequency, VCO. Controlled

Aluminum microstructure [6] shows better Q values. MEMS Inductor using Micromachining is being fabricated for low power applications [7]. Low-power, low-phase noise design of a fully-integrated 2.4GHz CMOS cross-coupled LC VCO is presented [8]. CMOS cross-coupled VCO technique is used to design a low power and optimized design [9].

II.

VOLTAGE CONTROL OSCILLATOR

I. INTRODUCTION Wave Generators play a prominent role in the field of electronics. They generate signals from few hertz to several gigahertzs. Even though significant amount of research work had been carried out, VCO is still a challenging component among RF designers. It is because more stringent requirements are imposed on VCOs as the need for wireless communications like Global System for Mobile Telecommunication (GSM) and Code Division Multiple Access (CDMA) is increasing and new applications are coming into wireless market at higher frequencies. The major issue in recent VCO research is to achieve monolithic integration of VCOs with low-power consumption at higher frequencies. MEMS are made up of components between 1 to 100 micrometers in size. MEMS technology can be implemented using a number of different materials and manufacturing techniques. The choice of which will depend on the device being created and the market sector in which it has to operate. So it is essential to design a complete control circuitry for designed MEMS inductor and capacitor. VCO design has therefore been attempted in the present project, which shall be part of the control circuitry. Due to the ever-increasing demand for the communication markets with small, cheap and low power consumption, efforts to integrated inductor capacitor LC-VCOs are presented in a number of realizations [1-3].To implement a VCO a switched capacitor array and variable inductor is being used to obtain the optimized inductor and capacitors [4]. Double cross coupled NMOS and PMOS differential pair with Copper inductor is being used to have low power [5]. High Q variable capacitor is realized by a surface micro-machined all

Generally, VCO is one of the building blocks of modern communication such as wireless and mobile phones. VCO performance in terms of phase noise, tuning range of frequency and power dissipation determine the basic performance of a transceiver. VCO is a circuit thats its output frequency is linearly proportional to its voltage control. The inductance L and capacitance C consist of a parallel resonance tank. RL and RC are the parasitic resistances of L and C, respectively. In order to compensate the losses coming from RL and RC, active components like CMOS transistors are used to realize a negative resistance (R). The basic principle operation of the VCO oscillator is controlled operation of the LC-tank circuit. A general LC tank circuit (LC-VCO) [8]. The inductance L and capacitance C consist of a parallel resonance tank. RL and RC are the parasitic resistances of L and C, respectively. In order to compensate the losses coming from RL and RC, active components like CMOS transistors are used to realize a negative resistance (R). The ring oscillator is a member of the class of time delay oscillators. A time delay oscillator consists of an inverting amplifier with a delay element between the amplifier output and its input. Because a single inverter computes the logical NOT of its input, it can be shown that the last output of a chain of an odd number of inverters is the logical NOT of the first input. This final output is asserted a finite amount of time after the first input is asserted; the feedback of this last output to the input causes oscillation. A circular chain composed of an even number of inverters cannot be used as a ring oscillator; the last output in this case is the same as the input. Therefore a 5-stage inverter chain is chosen as shown in Fig. 1. It provides high

VDD

M1

M4

M6

M8

M10

uses both NMOS and PMOS MOSFETs in a cross-coupled fashion. Each of these topologies can be further modified by adding a tail current source, which controls whether the devices operate in the so called voltage limited or current limited regime [11]. For the same current consumption, the CMOS version exhibits better phase noise than the NMOS only version [11].
VDD

M2

M3

M5

M7

M9

L1 L2 Vtune C1 M4 NEMOS C2

Fig. 1. Schematic of the Ring Oscillator.

M6 NEMOS M1 NEMOS M2 NEMOS

met, so as to optimize the design [10]. oscillating frequency as well as minimum area constraints is A) VCO core design It is well known that the active devices (NMOS1, NMOS2, PMOS1, and PMOS2) serve as the negative resistor to compensate for the energy loss from the tank due to the tank effective resistor. For a given power in the current limited some improvements over the NMOS-only VCO [8,10]. First, it has a tank amplitude twice that of the NMOS-only topology for a given current. Second, it could be optimized to have more symmetry in the output waveform leading to further phase noise reduction. Third, the complementary VCO consumes less power for a given phase noise if operated in the current limited region because of the same current, output amplitude of the former is twice that of an NMOS-only circuit. The schematic diagram of the complementary VCO is shown in Fig 2. One of the main goals of this design is to concurrently achieve low power consumption and low phase noise. Recently, it was recognized that the tail transistor may be the largest contributor to the phase noise in a VCO, especially to the phase noise close to the oscillation frequency. In this work, the switched tail transistors were used to force a trap and release its captured electron, rendering the transistor to be memory-less, and the flicker noise will be reduced [11]. Otherwise, the MOSFET we choose which was fabricated with deep n-well and it can obtain better substrate noise isolation because of an additional PN junction. Considering the above descriptions, complementary VCO with memory reduction tail current source is chosen. The symmetry of the circuit with respect to the vertical axis including inductor and DC pad layout could be used to lower the amplitude of the drain node voltage oscillation and hence, minimizing the up conversion to 2f0. The two varactors have been laid out with shared source/drain to minimize the fixed parasitic capacitance. MOS VCO topologies can he classified into two categories: 1) NMOS only core and 2) Complementary core (CMOS) which

VOUT

VOUT1

M5 NEMOS V2

M7 NEMOS M3 NEMOS

R1

R2

Figure. 2. Schematic LC-VCO

The superiority is due to the fact that CMOS structures provide higher transconductance for a given bias current, which results in faster switching of the cross-coupled differential pair. CMOS topologies have better rise and fall time symmetry, which tends to reduce the corner frequency [11]. Advantage of this topology are tank amplitude twice that of the NMOS-only topology for a given current. Second, it could be optimized to have more symmetry in the output waveform leading to further phase noise reduction. Third, the complementary VCO consumes less power for a given phase noise if operated in the current limited region because of the same current, output amplitude of the former is twice that of an NMOS-only circuit. [8,10] One disadvantage of this topology is that the maximizes signal swing is limited to the supply voltage. In situations where the supply voltage is low, NMOS only structures could he an option since they can provide voltage swings greater than the supply voltage hut at the expense of increased current drain and reduced efficiency. Large voltage swings above supply voltage could be a reliability issue. III. RESULTS AND DISCUSSION SPICE simulation is being done for ring oscillator. Fig. 3 shows variation of voltage with time for ring oscillator. From Fig. 3 it is seen that there is no control for the frequency of oscillation. Since there is no control mechanism, therefore it cannot be used as a good voltage controlled oscillator.

Fig. 3. Transient Response of the Ring Oscillator

Fig.5. Frequency Results of the LC-VCO

Fig. 3 shows the variation of control voltage with time for LCVCO. It is seen that there is controlled frequency of oscillation. SPICE simulation is being done for differential stage and biased resistor in order to control the frequency of oscillation in circuit given in Fig. 3. Here a controlled oscillating frequency output is obtained. Since there is a control mechanism, therefore it act as a good voltage controlled oscillator.

Power Dissipation with control voltage for LC-VCO is shown in Fig. 6. From Fig. 6 it is seen that power increases linearly and gradually with the change in the control voltage for the range from 0.2V to 1V. However, the power sharply varies with the change in the control voltage range from 1V to 1.8V. Also it is seen that for control voltage range from 0.8V to 1V as operating range, the power dissipation is 21.54 mW.

Fig. 6. Power Dissipation with control voltage for LC-VCO Table 1. Power dissipation for LC-VCO and Ring Oscillator PARAMETERS RING OSCILLATOR LC-VCO

Power Dissipation Fig. 3. Tuned Output Voltage variation with Time a) Tuning input, b) Tuned output, c) Tuned output-1

90.65 mW

21.54 mW

IV. V. CONCLUSION An analysis of phase noise in differential cross-coupled LC oscillators was presented. The VCO was implemented in a 0.18m CMOS process and verified in simulations using TANNER SPICE. Table 1 shows that 123 MHz LC oscillator using CMOS technology 600 kHz while dissipating 21.54 mW of power.

Fig. 4 shows variation of frequency with control voltage for LC-VCO. It is inferred from Fig. 4 that for the control voltage range from 0.8V to 1V the frequency of oscillation is found to be 118.5MHz. The theoretically calculated value for this is 120 MHz . Hence there is an error of 1.25%. Also it is seen that for control voltage range from 1.4V to 1.8V the frequency of oscillation is nearly constant and equal to 117MHz.

VI. ACKNOWLEDGEMENT The authors express sincere gratitude to MCIT, DIT, Govt. of India for providing financial and technical facilities under VLSI SMDP-II Project at NIT Hamirpur HP. Our sincere thanks are also due to the authorities of NIT Hamirpur HP for providing us the best facilities which have enabled us to learn the latest EDA tools. REFERENCES
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