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11/8/12

ASIC interv iew Question & Answer: PrimeTime

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ASIC interview Question & Answer


A blog to collect the interview questions and answer for ASIC related positions

Showing posts with label PrimeTime. Show all posts Friday, January 29, 2010

Prime Time Questions


1) What's PrimeTime? Answer: PrimeTime is a full chip static analysis tool that can fully analyze a multimillion gate ASIC in a short amount of time. 2) What files are required for PrimeTime to run? Answer: PrimeTime needs four types of files before you can run it: 1. Netlist file: Verilog, VHDL, EDIF 2. Delay file: SPEF(standard parasitic format, it's from STARRC or place&route tool), SPF, SDF(standard delay format) 3. Library file: DB ( From library vendors) 4. Constrains file: Synopsys Design Constraints(SDC) include 3 min requirement, clock, input delay and output delay 3) Can I use script in PrimeTime? Answer: Yes, you should use tcl( Tool command language) whenever possible.

4) What PrimeTime check? Answer: PrimeTime will check the following violations: 1. Setup violations: The logic is too slow compare to the clock. With that in mind there are several things a designer can do to fix the setup violations. Reduce the amount of buffering in the path.
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11/8/12

ASIC interv iew Question & Answer: PrimeTime

ASIC Gate (3) ASIC Logic (4) ASIC SystemVerilog (10) ASIC timing (2) ASIC Verification (1) C++ (2) Design Complier (1) M emory Interface (1) Networking (2) perl (9) PLL (1) Previous Interview Questions (1) PrimeTime (1) SVA (2) Verilog Interview Questions (6)

Replace buffers with 2 inverters place farther apart Reduce larger than normal capacitance on a books output pin Increase the size of books to decrease the delay through the book. Make sure clock uncertainty is not to large for the technology library that you are using. Reduce clock speed. This is a poor design technique and should be used as a last resort. 2. hold time violations: the logic is too fast. To fix hold violations in the design, the designer needs to simply add more delay to the data path. This can be done by Adding buffers/inverter pairs/delay cells to the data path. Decreasing the size of certain books in the data path. It is better to reduce the books closer to the capture flip flop because there is less likely hood of affecting other paths and causing new errors. Add more capacitance to the output pin of books with light capacitance. Fix the setup time violation first, and then hold time violation. If hold violations are not fixed before the chip is made, more there is nothing that can be done post fabrication to fix hold problems unlike setup violation where the clock speed can be reduced. 3. Transition Violations: When a signal takes too long transiting from one logic level to another, a transition violation is reported. The violation is a function of the node resistance and capacitance. The designer has two simple solutions to fix the transitions violations. Increase the drive capacity of the book to increase the voltage swing or decrease the capacitance and resistance by moving the source gate closer to sink gate. Increase the width of the route at the violation instance pin. This will decrease the resistance of the route and fix the transition violation 4. Capacitance Violations: The capacitance on a node is a combination of the fan-out of the output pin and the capacitance of the net. This check ensures that the device does not drive more capacitance than the device is characterized for.

Blog Archive
2010 (49)
November (1) October (2) June (2) May (2) April (7) February (12) January (23) ASIC Gate Interview Questions Part#3 Asic Flow Prime Time Questions Design Constraints and Synthesis Questions CAM related Questions Network Questions & Answer Basic OPP questions, SystemVerilog Interview Quest... System Verilog Interview Questions 2 Clock Domain Crossing Timing Q&A Ethernet Questions Memory Interface Questions ASIC Timing Interview Questions ASIC Logic Interview Questions Part #4 ASIC Gate Interview Questions Part #2 ASIC Logic Interview Questions Part # 3 ASIC Logic Interview Questions Part # 2
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11/8/12

ASIC interv iew Question & Answer: PrimeTime

ASIC Logic Interview Questions Part # 1 Verilog Interview Question Part # 5 Verilog Interview Questions Part #4 Verilog Interview Questions Part #3 Verilog Interview Questions Part #2 Verilog Interview Questions Part #1 ASIC Gate Interview Questions Part #1

The violation can be removed by increasing the drive strength of the book By buffering the some of the fan-out paths to reduce the capacitance seen by the output pin.

5) What conditions are used to check setup violation? Answer: WorstCase => setup violations BestCase => hold violations We use the worst case delay when testing for setup violations and then we use the best case delay when testing for hold violations. 6) How to run PrimeTime in the unix?

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[Linux] user@gmu>> pt_shell f pt_script.tcl |& tee pt.log Here are the sample PrimeTime script :

About Me
Roy Chan Specialties in ASIC Design and Verification from front-end to backend activities, including RTL coding, verification (testbench development, testcase generation and test regression), logic synthesis, static timing analysis, Place and route, power analysis, ECO and final tapeout process. Currently, I am still looking for a new career. View my complete profile

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A total of three scripts must be created, one for each timing corner. # -----------------------------------------------------------# Library Declarations. # -----------------------------------------------------------set search_path ". /proj/timing/etc" set link_path "*" lappend link_path "stdCell_tt.db" # -----------------------------------------------------------# Read in Design # -----------------------------------------------------------# Read in netlist read_file -f verilog top_level.v # Define top level in the hierarchy current_design "top_level" # Combine verilog and db files and identify any errors. link_design # Read in SPEF file read_parasitics -quiet -format SPEF top_level.spef.gz # -----------------------------------------------------------# Apply Constraints # -----------------------------------------------------------# Read in timing constraits read_sdc -echo top_level.sdc # Propagate clocks and add uncertainty to setup/hold calculations set_propagated_clock [all_clocks] set_clock_uncertainty 0.2 [all_clocks] 21 # -----------------------------------------------------------# Time
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asic-interv iew.blogspot.in/search/label/PrimeTime

11/8/12

ASIC interv iew Question & Answer: PrimeTime

# -----------------------------------------------------------set_operating_conditions -min WORST -max WORST # Register to Register report_timing -from [all_registers -clock_pins] \ -to [all_registers -data_pins] -delay_type max \ -path_type full_clock nosplit \ -max_paths 1 -nworst 1 \ -trans -cap -net > tc_reg2reg_setup.rpt report_timing -from [all_registers -clock_pins] \ -to [all_registers -data_pins] -delay_type min \ -path_type full_clock nosplit \ -max_paths 1 -nworst 1 \ -trans -cap -net > tc_reg2reg_hold.rpt # Register to Out report_timing -from [all_registers -clock_pins] \ -to [all_outputs] -delay_type max \ -path_type full_clock nosplit \ -max_paths 1 -nworst 1 \ -trans -cap -net > tc_reg2out_setup.rpt report_timing -from [all_registers -clock_pins] \ -to [all_outputs] -delay_type min \ -path_type full_clock nosplit \ -max_paths 1 -nworst 1 \ -trans -cap -net > tc_reg2out_hold.rpt # In to Register report_timing -from [all_inputs] -to [all_registers -data_pins] \ -delay_type max \ -path_type full_clock nosplit \ -max_paths 1 -nworst 1 -trans \ cap -net > tc_in2reg_setup.rpt report_timing -from [all_inputs] \ -to [all_registers -data_pins] \ -delay_type min -path_type full_clock \ -nosplit -max_paths 1 -nworst 1 \ -trans -cap -net > tc_in2reg_hold.rpt # All Violators Find Cap/Tran Violations # Summary of Setup/Hold Violations report_constraints -all_violators > tc_all_viol.rpt # Clock Skew report_clock_timing -type skew -verbose > tc_clockSkew.rpt exit
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ASIC interv iew Question & Answer: PrimeTime

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