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ASIC interv iew Question & Answer: ASIC Verif ication



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ASIC interview Question & Answer

A blog to collect the interview questions and answer for ASIC related positions

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Showing posts with label ASIC Verification. Show all posts Wednesday, April 21, 2010

ASIC Verification Interview Questions

1) What if design engineer and verification engineer do the same mistake in Test bench BFM(Bus Functional Model) and RTL(DUT)? How can you able to detect errors? Answer: 1. Code reviews & protocol checkers 2. IP gets verified in multiple environments .. like block level test bench, out of box testbench (connecting DUT back to back) , full fledged testbench using proven BFM, SoC level testbench using processor and all that etc... this all environments SHOULD be executed by diferent persons and so you should be able to catch that bug in one of this testbench ... 3. customer will catch the problem ( worst case ) 2) If you got a failure from the customer, how do you debug this? How do you prevent it to happen again?

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Answer: 1. First, try to reproduce the problem in your own environment. Try to get customer's vector, so you can inject the same vector to create the problem in house. 2. If you confirm the problem and fix them, you should put the new assertion or test to catch the problem again. Add this new test in the future test plan, so the problem will not happen again.

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Posted by Roy Chan at 9:40 AM Labels: ASIC V er ification

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ASIC interv iew Question & Answer: ASIC Verif ication

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November (1) October (2) June (2) May (2) April (7) SystemVerilog Interview Question 9 SystemVerilog Interview Questions 7 SystemVerilog Interview Questions 6 SystemVerilog Interview Question 5 SystemVerilog interview Questions 4 Systemverilog Interview Questions 3 ASIC Verification Interview Questions February (12) January (23)

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Roy Chan

asic-interv Verif ication



ASIC interv iew Question & Answer: ASIC Verif ication

Specialties in ASIC Design and Verification from front-end to backend activities, including RTL coding, verification (testbench development, testcase generation and test regression), logic synthesis, static timing analysis, Place and route, power analysis, ECO and final tapeout process. Currently, I am still looking for a new career. View my complete profile

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asic-interv Verif ication