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Computer Systems Architecture Dr Rob Williams

Course text: "Computer Systems Architecture - a networking approach" Edition 2 Prentice Hall, 2006

CSA Ch 01
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 01 - p 1

CSA Rob Williams Pearson Education (c) 2006

CSA ch 01 - p 2

1. CSA - the Hardware / Software Interface

Computer Architecture?

h/w

s/w

Interaction of h/w & s/w

User code

myprog.c WIN32 API O/S Kernel CPU Graphics Sound

Software
Operating Systems Procedures

Hardware

Layered hierarchy of s/w on a h/w bed

CSA Rob Williams Pearson Education (c) 2006

CSA ch 01 - p 3

108 Intel PII NEC 64Mb DRAM 7 10 Siemens 16Mb DRAM 1 Mb DRAM 106 Motorola 68000 256kbb DRAM 105 Intel 8086 Number of 4 64kb DRAM 10 transistors 3 1103 DRAM 10 Intel 4004 102 10 1 1970 1975 1980

Design year
3m

1985

1990

1995

2000

Circuit line width m 1

10

2.0m 1.0m 0.4m 0.35m 0.15m 0.1m ?

0.1

Moores Law of technological progress


ENTITY decoder8 IS PORT (sel: IN std_logic_vector (2 DOWNTO 0); -- select i/p signals sig: out std_logic_vector (7 downto 0)); -- eight o/p signals END decoder8; ARCHITECTURE rtl OF decoder8 BEGIN s <= "0000_0001" WHEN (sel "0000_0010" WHEN (sel "0000_0100" WHEN (sel "0000_1000" WHEN (sel "0001_0000" WHEN (sel "0010_0000" WHEN (sel "0100_0000" WHEN (sel "1000_0000"; END rtl; IS = = = = = = = X"0") X"1") X"2") X"3") X"4") X"5") X"6") ELSE ELSE ELSE ELSE ELSE ELSE ELSE

Modern h/w development: VHDL

CSA Rob Williams Pearson Education (c) 2006

CSA ch 01 - p 4

TIC

Control Computer

System Bus TDM Voice Bus LIC LIC LIC LIC

2.048Mbps Trunk Lines to other Switches

Monitoring terminal

Line interface cards

Telephone Switch showing the embedded computer

Windows le browser

CSA Rob Williams Pearson Education (c) 2006

CSA ch 01 - p 5

DLL initialization failure C:\WINNT\System32\KERNEL32.DLL The process is terminating abnormally

The local ATM gives an error message

% cat .cshrc umask 077 limit core 0 setenv TERM vt100 setenv PRINTER lw set prompt = "hostname > " set history = 25 biff y mesg n alias tt99 setenv DISPLAY TT99:0 set path = ( . /usr/ucb /usr/bin/X11 /bin /usr/bin /usr/local set path = ($path /etc /usr/etc /usr/lang /usr/local $home/bin)

Unix set up script or batch le

CSA Rob Williams Pearson Education (c) 2006

CSA ch 01 - p 6

hyper text DARPA/NSF LANs PSTN email ftp WWW Netscape

WANs CERN WIMP interfaces Unix + uucp archie

Original sources of the WWW

Dialup modem

Domestic PC

ISP

Ofce Network

ISP National/International Trunk Line ISP


Sun

WWW Ser vice Ser ver Provider

The Internet

CSA Rob Williams Pearson Education (c) 2006

CSA ch 01 - p 7

Hub

Ether Switch

ATM Switch

Router Mail server

DB server
100Mbps Ethernet
Ether Switch ATM Switch

Internet Gateway

Sun

Gateway Workstations Server

University LAN

8 bytes Preamble

6 bytes
Destination Address

6 bytes
Source Address

46 - 1500 bytes Type data payload

4 bytes Error Check

Ethernet packet structure


Williams R, Computer Systems Architecture, Prentice Hall, Tanenbaum A S, "Structured Computer Organization", Prentice Hall, Heuring & Jordon, "Computer Systems Design and Architecture", Addison Wesley Hamacher, Vranesic & Zaky, "Computer Organization", McGraw Hill

Patterson & Hennessy, "Computer Organization & Design: The Hardware/Software Inter Morgan Kaufmann

Buchanan W, "PC Interfacing, Communications & Windows Programming", Addison We

CSA Rob Williams Pearson Education (c) 2006

CSA ch 01 - p 8

CSA Ch 02
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 02 - p 9

2. CSA - the von Neumann Interitance


Input data Process Output data

All under program control


0010 0000 0011 1001 1101 0000 0001 0010 0000 0001 0001 0010 0011 0100 1101 0000 1011 1001

instructions

Central Processor Unit

Program Memory

Stored program control


Computer Smar t Card Microcontroller Games Console Home PC Workstation Ofce Server Mainframe Supercomputer Application Telephone/credit card Washing machine controller Interactive enter tainment Web information browsing Design layouts for circuit boards Central ling on local network Corporate Database Flight simulation studies

Common applications of computers

CSA Rob Williams Pearson Education (c) 2006

CSA ch 02 - p 10

from HLL:

i = j + k;

to assembler mnemonics: mov EAX,[12011234] add EAX,[12011238] mov [1201123C],EAX to machine binary: 0010 0000 0011 1001 0001 0010 0000 0001 0001 0010 0011 0100 1101 0000 1011 1001 0001 0010 0000 0001 0001 0010 0011 1000 0010 0011 1100 0000 0001 0010 0000 0001 0001 0010 0011 1100

Semantic Gap

HLL, assembler & machine code

1. Data Transfer and Manipulation 2. Input / Output 3. Transfer of Program Control 4. Machine Control

Categories of machine instructions

CSA Rob Williams Pearson Education (c) 2006

CSA ch 02 - p 11

Edit

HLL source le

Compile

Binar y object les

Executable le

Link
Errors

Load RUN

Librar y Errors les

Phases of a HLL compiler

Source les edit

Macros

Object libraries Link

Dynamic libraries Build RUN

Compile

Code sharing at different phases

CSA Rob Williams Pearson Education (c) 2006

CSA ch 02 - p 12

Mod. 1 Mod. 4 Mod. 2 Mod. 3 Call to Subroutine

Linking code modules

Edit

HLL source le Analysis Errors


Tokenised instruction

Command Routines Decode Select & Execute

Java source le Edit javac compiler

Java bytecodes java inter preter

java applet Netscape browser HTML text page

Java language interpreters

CSA Rob Williams Pearson Education (c) 2006

CSA ch 02 - p 13

409620481024 512 256 128 64

32

16

weighting

1 1 1 1 0 1 0 1 1 1 0 0 1
4096 + 2048 + 1024 + 512 + 128 + 32 + 16 + 8 + 1 = 7865

1111101000 0001100100 0000001010 0000000001

weighting

0010 x 1111101000 + 0011 x 0001100100 + 1001 x 0000001010 + 0111 x 0000000001 = 100101011101

Binary to decimal & decimal to binary conversion


remainders written from right to left 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

1 1 1 1 1 1 0 1 -------2 ) 2 3 9 7 1 1 9 8 5 9 9 2 9 9 1 4 9 7 4 3 7 1 8 9 4 2 1 0

results written down

Hex & binar y

CSA Rob Williams Pearson Education (c) 2006

CSA ch 02 - p 14

\ b i t s 765 | 000 001 010 011 100 101 110 111 \ | bi ts\ dec | 0 16 32 48 64 80 96 112 4321 \ hex | 0 10 20 30 40 50 60 70 --------------|--------------------------------------------0000 0 0 | NUL DLE SP 0 @ P p 0001 1 1 | SOH DC1 ! 1 A Q a q 0010 2 2 | STX DC2 " 2 B R b r 0011 3 3 | ETX DC3 # 3 C S c s 0100 4 4 | EOT DC4 $ 4 D T d t 0101 5 5 | ENQ NAK % 5 E U e u 0110 6 6 | ACK SYN & 6 F V f v 0111 7 7 | BEL ETB 7 G W g w 1000 8 8 | BS CAN ( 8 H X h x 1001 9 9 | T AB EM ) 9 I Y i y 1010 10 A | LF SUB * : J Z j z 1011 11 B | VT ESC + ; K [ k { 1100 12 C | FF FS , < L \ l | 1101 13 D | CR GS = M ] m } 1110 14 E | SO HO E . M > N n 1111 15 F | SI NL / ? O _ o DEL NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI SP Null DLE Start of Heading DC1 Start of Text DC2 End of Text DC3 End of transmission DC4 Enquiry NAK Acknowledge SYN Bell ETB Back Space CAN Horizontal Tab EM Line Feed SUB Ver tical Tab ESC Form Feed FS Carriage Return GS Shift Out RS Shift In US Space DEL Data Link Escape Device Control 1 Device Control 2 Device Control 3 Device Control 4 Negative Acknowledge Synchronization character End of Transmitted Block Cancel End of Medium Substitute Escape File Separator Group Separator Record Separator Unit Separator Delete

http://www.unicode.org

ASCII code table

CSA Rob Williams Pearson Education (c) 2006

CSA ch 02 - p 15

#include <stdio.h> void main() { putchar(7); }

Ring the bell


char letter; short count; unsigned int uk_population; long world_population; float body_weight; double building_weight; long double world_weight;

Data types

AIX CICS CP/M George ISIS MINIX MSDOS Multics

OS/2 PRIMOS RSX/11 TDS UNIX VERSADOS VMS XENIX

CDOS CMS MSDOS IDRIS LYNXOS MOP MVS OS-9

PICK RSTOS RTL/11 THE Ultrix VM MS WINDOWS Linux

Operating Systems
1. Command line interpreter (CLI), shell script or desktop selections 2. Function calls from within user programs (API)

Access to O/S facilities


CSA Rob Williams Pearson Education (c) 2006

CSA ch 02 - p 16

rob[66] stty -icanon min 1 time 0 ; menu_prog Are you ready to proceed? [ Y / N ] :

Unix unbuffered, nonblocked keyboard


#include <errno.h> #include <stdio.h> #include <sys/termios.h> #include <unistd.h> #define TIMEOUT -1 extern int errno; int sys_nerr; extern char * sys_errlist[]; void setterm(void) { struct termios tty; int status; status = ioctl(0,TCGETS, &tty); tty.c_lflag &= ICANON; tty.c_cc[VTIME] = 0; tty.c_cc[VMIN] = 1; status = ioctl(0,TCSETS, &tty); if ( status == -1 ) { printf("ioctl error \n"); perror(sys_errlist[errno]); exit(); } }

CSA Rob Williams Pearson Education (c) 2006

CSA ch 02 - p 17

User Applications CLI kernel hardware drivers

Onion layered model for Operating Systems

sh - the original Bourne shell, still popular with administrators for scripts csh - the C shell, more C-like syntax, and is better for interactive sessions tcsh - Tenex shell, perhaps the most used interactive shell, emacs keying ksh - Korn shell, normal issue with Hewlett Packard workstations bash - bourne-again-shell, a free-ware rework of several shells

Unix command shells

CSA Rob Williams Pearson Education (c) 2006

CSA ch 02 - p 18

Screen Server

Print Ser ver

File Server

Client-ser ver computing


Client
Request Message Reply Request Replies Request

Ser ver time

Xterm
atari@pong [50] xterm & atari@pong [51] rlogin milly -l rwilliam Last login: Tue Jul 1 09:22:21 sister rwilliam@milly >

CSA Rob Williams Pearson Education (c) 2006

CSA ch 02 - p 19

CSA Ch 03
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 03 - p 20

3. CSA - the Fetch-execute Cycle


Computer

Computer subsystems
I/O Units
Mouse socket Printer Connector Keyboard socket

CPU

Main Memory
USB sockets

MODEM socket

LAN socket

Slots for I/O Expansion Cards

Sound

I/O

ATX Power Connector Hard Disk IDE Connectors Floppy disk Connector PCI Slots
ChipSet

VGA

ISA Slot Lithium Batter y


BIOS

AGP Slot

ChipSet

Slots for Memory Modules

Socket 462

Crystal

Fig 3.2 PC ATX Motherboard, showing the locations of the CPU, memor y and I/O card sockets

CPU Fan Connector Pentium CPU and Heatsink

Motherboard from a PC

CSA Rob Williams Pearson Education (c) 2006

CSA ch 03 - p 21

System Clock

CPU Interrupt Request System Bus

Main Memory

I/O Subsystem

Subsystems joined by a bus highway

Bus

Point-to-point vs. bus interconnect schemes

CPU

ALU

Control Unit

CPU has two main component parts


CSA Rob Williams Pearson Education (c) 2006

CSA ch 03 - p 22

1 1 000 000 000 fetch-execute 10 ns logic gate delay 5 ns SRAM access 15 ns

ns

s 1 1 000 000
light 300 m/s tv line scan 60 s interrupt 2-20 s engine spark 10 s

1 1 000 human reaction 300 ms tv frame 20 ms hard disk access 10 ms car engine (3000 rpm) 20 ms

ms

Comparative speeds

CSA Rob Williams Pearson Education (c) 2006

CSA ch 03 - p 23

CPU
AX IP IR

System Clock

System Bus

MAR
10111000 00000000 00000001

Main Memory CPU


AX IP IR AX IP ++

CPU
IR

Instruction Address

Instruction Code

Address bus

Data bus

MAR
10111000 00000000 00000001

MAR
10111000 00000000 00000001

Main Memory

Main Memory

The Fetch part of the Fetch-Execute Cycle


CSA Rob Williams Pearson Education (c) 2006

CSA ch 03 - p 24

CPU
AX IP IR AX

CPU
IR IP ++

Data Address

Operand Data: 256

MAR
10111000 00000000 00000001

MAR
10111000 00000000 00000001

Main Memory

Main Memory

The execute part of the Fetch-Execute Cycle

CPU activity for a Sun workstation

CSA Rob Williams Pearson Education (c) 2006

CSA ch 03 - p 25

Data bus - typically 32 bits wide, but will be increased to 64 bits, Address bus - 32 bits wide, but will require more very soon, Control bus - about 15 lines for starting and stopping activities.

System bus has three parts

A
System Clock Address R/W Addr1

Addr2

Addr3

Read

Read

Write

Data

Instr Fetch 10 ns

Data Execute time-base

Result

Timing of synchronous bus activity

CSA Rob Williams Pearson Education (c) 2006

CSA ch 03 - p 26

Addr1 Address ALE R/W

Addr2

Addr3

A
valid Fetch

valid

valid

Read

Write

Data

Instr

Data

Result

DTA

ok

ok 10 ns

ok time-base

Timing of asynchronous bus activity

Read instruction

Decode instruction

Read operand

Execute op

Write result

A Single Instruction Cycle

Timing of multi-phase instructions cycle

CSA Rob Williams Pearson Education (c) 2006

CSA ch 03 - p 27

1011011
Robert

Musical interference on FM receivers

ideal pulse

real pulse

Clock speed limitation

CSA Rob Williams Pearson Education (c) 2006

CSA ch 03 - p 28

IP

Pre fetcher unit queue

Execution unit

Prefetching instructions
fetch 1 execute 1 fetch 2 execute 2 fetch 3 execute 3 fetch 4 execute 4

Winning margin

fetch 1

fetch 2

fetch 3

fetch 4

fetch 5

fetch 6

fetch 7

fetch 8 execute 5

fetch 9 execute 6

execute 1

execute 2

execute 3

execute 4

Time

Overlapped operations gives greater throughput


Address Width
1111 1111 1111 1111 1111 1111

Top

16 MByte

memor y length

0000 0000 0000 0000 0000 0000

Bottom

memor y width

Address width determines memory length


CSA Rob Williams Pearson Education (c) 2006

CSA ch 03 - p 29

16 bit addresses can access 216, 20 bit addresses can access 220, 24 bit addresses can access 224, 32 bit addresses can access 232, 64 bit addresses can access 264,

65536, 64K locations 1048576, 1M locations 16777216, 16M locations 4294967296, 4G locations 4398046511104, 4E locations

dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 bin 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1 hex 0 1 2 3 4 5 6 7 8 9 A B C D

CSA Rob Williams Pearson Education (c) 2006

CSA ch 03 - p 30

Motorola 68030 b1[0] b2[0]


Address
0FE032 0FE042 0FE052 0FE062 0FE072 0FE082 0FE092

Memory Contents In Hex

0102 0304 0506 0708 090A FBFC FDFE FF00 0001 0002 0003 0004 0005 00FE 00FF 0100 0101 FFFC FFFD FFFE FFFF 0000 0001 0000 0002 0000 0003 0000 0004 0000 0005 0000 00FE 0000 00FF 0000 0100 0000 0FFF 0000 1000 0000 1001 FFFF FFFF 0000 0A00 0000 0000 0020 0000 0000 0000 0000 000F E0C0

b4[0]

Intel Pentium
Compare these

Byte ordering: big endian, little endian


unsigned char b1[ ] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 251, 252, 253, 254, 255}; unsigned short b2[ ] = {1, 2, 3, 4, 5, 254, 255, 256, 257, 65532, 65533, 65534, 65535}; unsigned int b4[ ] = {1, 2, 3, 4, 5, 254, 255, 256, 4095, 4096, 4097, 4294967295};

CSA Rob Williams Pearson Education (c) 2006

CSA ch 03 - p 31

Data Bus

R/W

Address bus

Address Decoder

Chip Select

Data Bus

R/W

Address bus

Address Decoder

Chip Select

Parallel data input & output ports

CSA Rob Williams Pearson Education (c) 2006

CSA ch 03 - p 32

CSA Ch 04
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 04 - p 33

4. CSA - the Control Unit (CU)


5v 14 13 12 11 10 9 8

7 0v

Inputs C A B A AND B 00 0 01 0 10 0 11 1 A B AND C

Inputs A B A OR B 00 0 01 1 10 1 11 1

Inputs A B A XOR B 00 0 01 1 10 1 11 0

Input A NOT A 0 1 1 0

OR

XOR

NOT

Basic logic gates with truth tables


1 1 1 1 0 1 0 1 0

Detect: 111

Detect: 101

Detect: 010

Using AND for pattern recognition


DX 00 01 10 11 Out 0 0 0 1 D Data in

X Off/On control line

Data Out

DX d0 d1

Out 0 d

Using AND as a data valve


CSA ch 04 - p 34

CSA Rob Williams Pearson Education (c) 2006

Control WXYZ 0001 0010 0100 1000

Data ABCD abcd abcd abcd abcd

Out a b c d

Data lines A B C D W X Output

Control Y lines Z
O = (A AND Z ) OR (B AND Y ) OR (C AND X ) OR (D AND W )

Data selector, 1 from 4


Selector YX 00 01 10 11 Line dcba 0001 0010 0100 1000

O = (A AND (X AND Y ) ) OR (B AND (X AND Y ) ) OR (C AND (X AND Y ) ) OR (D AND (X AND Y

2-to-4 line decoder, 1-out-of-4 line selector


CSA Rob Williams Pearson Education (c) 2006

CSA ch 04 - p 35

Input Y X 2 Line Decoder A1 a Data lines D C B A

A2

b Data c Output

A3

A4

a b c d A B C D

Output

O1 = (i 3 AND i 2 AND i 1) OR (i 4 AND i 3 AND i 2) OR (i 4 AND i 3 AND i 2 AND i 1)

Data multiplexor, 1 from 4


CSA Rob Williams Pearson Education (c) 2006

CSA ch 04 - p 36

inputs 1234 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

O 0 0 1 0 0 1 0 0 0 0 1 0 1 1 0 0 i
1 2 3 4

O1

O1 = (i 3 i 2 i 1) + (i 4 i 3 i 2) + (i 4 i 3 i 2 i 1)

Sum of Products solution


XY 00 01 10 11 NAND 1 1 1 0

The 2 input NAND gate

CSA Rob Williams Pearson Education (c) 2006

CSA ch 04 - p 37

i1

i2

i3

O1 O2 O3 O4 O5 O6 O7 O
8

Programmable Logic Array (PLA)

CSA Rob Williams Pearson Education (c) 2006

CSA ch 04 - p 38

Level Crossing Inputs XY 00 01 10 11 Lights RAG 100 110 001 010 Inputs XYZ
N W E W S E

000 001 010 011 100 101 110 111

Cross Roads Lights RAG rag W-E N-S 100 100 110 100 001 100 010 100 100 100 100 110 100 001 100 010

Y R A G

Z R A G r a
N-S W-E

R=X A =Y G = X AND Y

R = (X AND Y ) A = (X AND Z ) G = (X AND Y AND Z )

r = (X AND Y ) a = (X AND Z ) g = (X AND Y AND Z )

Trafc light controllers

CSA Rob Williams Pearson Education (c) 2006

CSA ch 04 - p 39

Inputs Enable Select


G1 G2 X1 0X 10 10 10 10 10 10 10 10 CBA XXX XXX 000 001 010 011 100 101 110 111

Outputs Y
01234567 11111111 11111111 01111111 10111111 11011111 11101111 11110111 11111011 11111101 11111110 A B C 3 to 8 line decoder Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

G1 G2 G3

Y0 Y1 Y2 Y3 Y4

A B C

Y5 Y6 Y7

3 to 8 line decoder

CSA Rob Williams Pearson Education (c) 2006

CSA ch 04 - p 40

Inputs WXYZ 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

LEDs abcdefg 1111110 0110000 1101101 1111001 0110011 1011011 0011111 1110000 1111111 1111011

a f b

a = (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) b = (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) c = W AND X AND Y AND Z d = (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) e = (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) f = (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) g = (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) Z Y X W

Binar y to 7-segment decoder


CSA Rob Williams Pearson Education (c) 2006

CSA ch 04 - p 41

READY SPIN FILL

DRAIN

HEAT

RINSE DRAIN

WASH

1 rev per

1 2 1 1000 hr 2rph rps Hz mHz 0. 55mHz 2 3600 1800 1800

Washing machine Finite State Diagram (FSD)

CSA Rob Williams Pearson Education (c) 2006

CSA ch 04 - p 42

from micro-switch 0 micro-switch 1 micro-switch 2 Micro switch

Control Lines 0 1 0 1 0
0.55 mHz

1 0 1 000 READY 001 010 011 100 101 110 111 FILL HEAT WASH DRAIN RINSE DRAIN SPIN

Valve Heat Motor Pump Open On F S

0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1

On

IR

Washing machine sequence controller (FSM)


CSA ch 04 - p 43

CSA Rob Williams Pearson Education (c) 2006

Control Store 111 00101 110 00001 101 10010 100 00001 011 00010 Program Counter 3 bit code from micro-switches 010 01000 001 10000 000 00000
Valve Heat Open On F S Pump On Motor

5 bit control word

Control Lines

Control 111 110 101 100 011 010 001 Store 00101 00001 10010 00001 00010 01000 10000 00000

JMP

ag

addr select 000 00 000 000 000 000 000 000 000 00 00 00 00 00 00 00

Clock Reset

Counter

000

decoder

JMP addr
JMP load temperature water level high water level low

Washing machine controller with conditional branching

CSA Rob Williams Pearson Education (c) 2006

CSA ch 04 - p 44

internal data bus Instruction Register Addr Gen

Pre-Decode

System Clock

Binar y Counter 000 001 010 011

Decoder 00001 00010 00100 01000 10000

Control Logic Gate Array

Status Bits Condn Flags

reset

dedicated control signals

Hardware logic Control Unit (RISC)

CSA Rob Williams Pearson Education (c) 2006

CSA ch 04 - p 45

internal data bus IR

Binar y System Clock Counter 000 001 010 011

Address Generator Logic

Condn Flags

Microaddr Reg

reset

Control Store PROM

Micro IR

dedicated control signals

Microcoded Control Unit (CISC)

CSA Rob Williams Pearson Education (c) 2006

CSA ch 04 - p 46

CSA Ch 05
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 05 - p 47

5. CSA - the Arithmetic & Logic Unit (ALU)


(X AND Y ) (X OR Y )

(X OR Y ) (X AND Y )

while ( ! dog && ! cat ) { plant_flowers( ) ;} while (! (dog || cat )) { plant_flowers( ) ;}

De Morgans equivalences
X XY 00 01 10 11 ADD CS 00 01 01 10 X Y Carr y Y Carr y Sum

Sum

Alternative Half Adder (2 inputs) circuits


CSA Rob Williams Pearson Education (c) 2006

CSA ch 05 - p 48

Y Carr y

Sum

Y Carr y

Sum

More Half Adder circuits

XYZ 000 001 010 011 100 101 110 111

CS 00 01 01 10 01 10 10 11

X Y Z

1/2 Adder Full-adder

Carry 1/2 Adder C


2

Sum

Full Adder (3 inputs) circuit


CSA Rob Williams Pearson Education (c) 2006

CSA ch 05 - p 49

A
3 2 1 0 3 2

B
1 0

Cin Add0

Add1

Add2

C=A+B
Cout

Add3 S3 S2 S1 S0

4 bit parallel adder circuit

CSA Rob Williams Pearson Education (c) 2006

CSA ch 05 - p 50

0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000
31 0

+7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8
31

positive

Negative integers using Twos Compliment format

negative
0

To form a twos compliment negative: Take the positive number, invert all the bits, add 1.

B 1 - subtract
31 0

0 - add

Carr y in 32 bit ALU (Parallel Adder) C


31 0

IR

control lines CU

ALU with positive and negative capability


CSA Rob Williams Pearson Education (c) 2006

CSA ch 05 - p 51

Input, x x7 . . . . . x0 Diagonal closed switch pattern controlled by the CU No shift in this position x7 . . . . . . . x0 Output Input, x x7 . . . . . x0 Input, x x7 . . . . . . x0 Input, x x7 . . . . . x0

Output, x <<= 1

x6 . . . . . x0 0

Output, x <<= 2

x5 . . . x0 0 0

Output, x >>= 3

0 0 0 x7 . . x3

Input, x x7 . . . . . x0

Input, x x7 . . . . . x0

x2 1 0 7 6 5 4x3 Output, ROL x,5

x4 3 2 1 0 7 6x5 Output, ROR x,5

Barrel Shifter circuit for Shifts & Rotates


CSA Rob Williams Pearson Education (c) 2006

CSA ch 05 - p 52

173 57x -------1211 8650 -------9861

10101101 00111001x -------------------10101101 00000000 00000000 10101101 10101101 10101101 00000000 00000000 -----------------------------------1001101000001

Integer multiplication by Shift and Add

/* function to multiply two 16 bit positive integers returning a 32 bit result, using only integer addition and shift operators */ int multiply(int a, int c) { int i; c = c << 16; for (i=0; i<16; i++) { if (a & 1) { a += c }; a = a >>1; } return a;

CSA Rob Williams Pearson Education (c) 2006

CSA ch 05 - p 53

Test LS bit A

1
00101101 00111001 00010110 10011100 00101101

00000000 00111001 00101101 00000000 C 00010110 10011100 00101101 Test LS bit

+
00101101

shift right

00010110 10011100 00101101

00001011 01001110 00101101

shift right

00001011 01001110 00101101 Test LS bit

00001011 01001110 00101101

00000101 10100111 00101101

shift right

00000101 10100111 00101101

00110010 10100111

00011001 01010011 00101101

if (A & 1)

A += C 1
00101101

A = A >>1

00011001 01010011 00101101 Test LS bit

01000 110 01010011

00100011 00101001 00101101

+ 1
00101101

shift right

00100011 00101001 00101101 Test LS bit

01010000 00101001

00101000 00010100 00101101

+ 1
00101101

shift right

00010100 00001010 00101101 Test LS bit

00001011 01001110 00101101

00000101 10100111 00101101

shift right

Result
00010100 00001010 00101101 Test LS bit 00010100 00001010 00101101 00001010 00000101 00101101

shift right

8 x 8 multiply using two 16 bit registers


CSA Rob Williams Pearson Education (c) 2006

CSA ch 05 - p 54

D7 D6 D5 D4 D3 D2 D1 D0

Data Registers

Register select

Internal CPU Data Bus


A B Carr y in control lines CU

ALU

CPU Flags

ALU with data registers

CSA Rob Williams Pearson Education (c) 2006

CSA ch 05 - p 55

Output Values, F
S3 - S0

M=1 Logic Cin = 0

M=0 Arithmetic Cin = 1 F =A+1 F = (A OR B) + 1 F = (A OR A) + 1 F =0 F = A + (B AND A) + 1 F = (A OR B) + (B AND A) + 1 F =AB F = (B + A) F = A + (A AND B) + 1 F =A+B +1 F = (B OR A) + (A AND B) + 1 F = (A AND B) F = (A << 1) + 1 F = (A OR B) + A + 1 F = (B OR A) + A + 1 F =A

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

F =A F = A OR B F = A AND B F =0 F = A AND B F =B F = A XOR B F = B AND A F = A OR B F = A XOR B F =B F = A AND B F =1 F = B OR A F = A OR B F =A

F =A F = A OR B F = B OR A F = 1 F = A + (B AND A) F = (A OR B) + (B AND A) F =AB 1 F = B AND A 1 F = A + (B AND B) F =A+B F = (B OR A) + (A AND B) F = (A AND B) 1 F = A << 1 F = (A OR B) + A F = A + (B OR A) + A F =A1

Data in
A0 A1 A2 A3 B0 B1 B2 B3 Cin S3 S2 S1 S0 M

Data out
F0 F1 F2 F3 Cout

74xx181

A=B

Control

Example integer ALU component


CSA Rob Williams Pearson Education (c) 2006

CSA ch 05 - p 56

float net_cost, tot_cost, price; float vat = 0.175; int items; net_cost = price * items; tot_cost = net_cost + net_cost * vat;

Floats & integers in HLL programming

CSA Rob Williams Pearson Education (c) 2006

CSA ch 05 - p 57

Normal 1234.5625 -3.3125 0.065625 1234.5625

Exponential 1.2345625 x 10 -3.3125 x 10 6.5625 x 10


0 -2 3

Exponent Mantissa

10011010010.1001
unnormalized

1.00110100101001 x 21010
normalized format

-3.3125 0.065625

-11.0101 0.00011

-1.10101 x 21 1.1 x 2-4

Floating-point numbers, in IEEE 754 32 bit format, appear in memory as: 31 30 23 22 0

S 0 1 0

exponent 10001001 10000000 01111011

mantissa 00110100101001000000000 10101000000000000000000 10000000000000000000000

To manually converting a decimal oat into a IEEE binary oat:


1. Convert the integer part into binary. 2. Convert the fractional part into binary, noting the 1/2, 1/4, 1/8, 1/16 pattern! ... 128 64 32 16 8 4 2 1 0.5 0.25 0.125 0.0625 0.03125 ... 3. Normalize by moving the binary point to produce the format: 1.something with a positive or negative shift number. 4. Delete the leading 1, and extend the left bits with 0s to give a 23 bit mantissa. 5. Add 127 to the shift number to give the 8 bit exponent.
CSA Rob Williams Pearson Education (c) 2006

CSA ch 05 - p 58

/* floatit.c - to write a real number into a file for viewing */ #include <stdio.h> int main( ) { FILE *fp; float f = 231.125; if (fp = fopen ("float_data", "w")) { fwrite(&f, 4, 1, fp); }; return 0; }

rob@olveston [78] cc oatit.c -o oatit rob@olveston [79] oatit rob@olveston [80] od -x oat_data 0000000 0000004 rob@olveston [129] od -f oat_data 0000000 2.3112500e+02 0000004 rob@olveston [130] 4367 2000

CSA Rob Williams Pearson Education (c) 2006

CSA ch 05 - p 59

The hex value 43 67 20 00 is the 32 bit oating-point number : 0 100 0011 0110 0111 0010 0000 0000 0000 || sign bit 8 bit exponent in 127 offset format The range and precision of the various oating-point formats are as follows: | 23 bits of the 24bit mantissa

32 bit 64 bit 128 bit

8 bit 11 bit 15 bit

Range Precision 24 bit, (1 in 16 x 106) 53 bit, (1 in 8 x 1015) 64 bit, (1 in 16 x 1018)

CSA Rob Williams Pearson Education (c) 2006

CSA ch 05 - p 60

CSA Ch 06
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 06 - p 61

6. CSA - the Memory


1 0 1 0 1 bit data out 1 bit data in Stored data out

Write-once, Read-many memor y cell

Qt St Rt 000 001 010 011 100 101 110 111

Q t+1 Q t+1 1 0 1 0 0 1 illegal 0 1 1 0 0 1 illegal

_ Q

S S R Q _ Q R S-R Latch

_ Q Q

S-R Latch, 1 bit static memory

CSA Rob Williams Pearson Education (c) 2006

CSA ch 06 - p 62

5v
0V Cat ap swipe switch 10 kOhm

5v

200 Ohm

LED
OUT IN

Cat IN-OUT indicator using an S-R latch


10ns DRAM, Dynamic Random Access Memory - read & write, random access 1ns SRAM, Static Random Access Memory ROM Read Only Memory, factor y written - random access PROM Programmable ROM, writable, but only once. EPROM 150ns UV erasable PROM, with a window in the package to admit the UV photons EEPROM electrically erasable PROM, useful for semi-permanent programming FLASH similar to EEPROM, reprogrammable, non-volatile ROM RAM

5v A14 A13 A0 A9 A1 OE A10 CS D7 D6 D5 D4 D3

3v D0 3v D1 0 D2 3v D3 0 3v WE CAS RAS CS B0 B1 A10 A0 A1 A2 A3 3v

MT46V128M8TG-6T

M5L27512K-2
A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 Gnd D7 0 D6 3v D5 0 D4 3v 0 DQ Clk Cke A11 A9 A8 A7 A6 A5 A4 0

Mitsubishi, M5L27512K-2 64 kbytes EPROM 200 nsec access time

Micron, MT46V128M8TG-6T 128 Mbyte Dynamic RAM 167 MHz operation, 6 ns access

Different types of memory


CSA Rob Williams Pearson Education (c) 2006

CSA ch 06 - p 63

Clock, f

FlipFlop

f/2

FlipFlop

f/4

FlipFlop

f/8

FlipFlop

Clock f f/2 f/4 f/8

Flip-ops used for frequency division

CSA Rob Williams Pearson Education (c) 2006

CSA ch 06 - p 64

Word line Transistor switch 1 bit storage capacitor ~ 20 fF Bit line

CAS RAS Write Enable


Row Address latch

Bit line drivers

Row decoder

Address

64Mbit Memor y Cell array

Multiplexor Column decoder

31

Address
15 015 0

Row number
RAS cycle

Column number
CAS cycle

Row Access RAS Column Access CAS Row Addr Data 60 ns access time

C0 D0

C1 D1

C2 D2

C3 D3

Dynamic ram (DRAM) single cell and memory array


CSA Rob Williams Pearson Education (c) 2006

CSA ch 06 - p 65

16 MByte, 50ns access, 32 bit, 72 pin SIMM card

64 MByte, 100 MHz clock, 64 bit, 168 pin DIMM card

72 pin SIMM and 168 pin DIMM, DRAM Modules


22 Remember : 220 = 1M, so: 2 = 4M

CSA Rob Williams Pearson Education (c) 2006

CSA ch 06 - p 66

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Vss DQO DQ1 D02 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 D012 DQ13 VCC DQ14 DQ15 NC NC Vss NC NC Vcc WE DQM0 DQM1 CSO NC Vss AO A2 A4 A6 A8 A10/AP BA1 Vcc Vcc CLKO

43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Vss NC CS2 DQM2 DQM3 NC Vcc NC NC NC NC Vss DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC NC NC Vss DQ21 DQ22 D023 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss CLK2 NC NC SDA SCL Vcc

85 Vss 86 DQ32 87 DQ33 88 DQ34 89 DQ35 90 Vcc 91 DQ36 92 DQ37 93 DQ38 94 DQ39 95 DQ40 96 Vss 97 DQ41 98 DQ42 99 DQ43 100 DQ44 101 DQ45 102 Vcc 103 DQ46 104 DQ47 105 NC 106 NC 107 VSS 108 NC 109 NC 110 VCC 111CAS 112 DQM4 113 DQM5 114 NC 115RAS 116 VSS 117 Al 118 A3 119 A5 120 A7 121 A9 122 BAO 123 All 124 VCC 125 CLK1 126 NC

127 Vss 128 CKEO 129 NC 130 DQM6 131 DQM7 132 NC 133 Vcc 134 NC 135 NC 136 NC 137 NC 138 Vss 139 DQ48 140 DQ49 141 DQ50 142 DQ51 143 Vcc 144 DQ52 145 NC 146 NC 147 NC 148 Vss 149 DQ53 150 D054 151 DQ55 152 Vss 153 DQ56 154 DQ57 155 DQ58 156 D059 157 Vcc 158 DQ60 159 DQ61 160 DQ62 161 DQ63 162 Vss 163 CLK3 164 NC 165 SAO 166 SA1 167 SA2 168 Vcc

Pin assignments for a 168 pin SDRAM DIMM

CSA Rob Williams Pearson Education (c) 2006

CSA ch 06 - p 67

CPU A0-31

A0-31 4 GB SRAM

Ideal memory conguration

Device

Size

Pins

32 bit address bus

Address range

PROM1 RAM1 RAM2 RAM3 RAM4 + x 0 1

1MB 16MB 16MB 16MB 16MB

20 24 24 24 24

0000 0000 xxxx ++++ ++++ ++++ ++++ ++++ 0000 0001 ++++ ++++ ++++ ++++ ++++ ++++ 0000 0010 ++++ ++++ ++++ ++++ ++++ ++++ 0000 0011 ++++ ++++ ++++ ++++ ++++ ++++ 0000 0100 ++++ ++++ ++++ ++++ ++++ ++++

0000 0000 - 000F FFFF 0100 0000 - 01FF FFFF 0200 0000 - 02FF FFFF 0300 0000 - 03FF FFFF 0400 0000 - 04FF FFFF

address line used directly for internal selection line ignored, indicates partial (degenerate) addressimg must be 0 for chip selection must be 1 for chip selection

Memor y map for a small computer system


CPU A0-31 System Bus A24 A25 A26
A27 A28 A29 A30 A31 100 011 010 001 000

A0 - A31, D0 - D7 A0-23 A0-23 A0-23 A0-23 A0-19

RAM4 16MB

c/s

RAM3 16MB

c/s

RAM2 16MB

c/s

RAM1 16MB

c/s

PROM1 1MB
c/s

3 line Decoder (1 out of 8 selector)

Memory Schematic showing the Decoding Circuit


CSA Rob Williams Pearson Education (c) 2006

CSA ch 06 - p 68

Page 255 16MB

A31 - A24 address lines for memor y decoder

RAM4 16MB RAM3 16MB RAM2 16MB RAM1 16MB PROM1 1MB

0000 0100 1111 1111 1111 1111 1111 1111 0000 0100 0000 0000 0000 0000 0000 0000 0000 0011 1111 1111 1111 1111 1111 1111 0000 0011 0000 0000 0000 0000 0000 0000 0000 0010 1111 1111 1111 1111 1111 1111 0000 0010 0000 0000 0000 0000 0000 0000 0000 0001 1111 1111 1111 1111 1111 1111 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 Binar y

04 FF FF FF 04 00 00 00 03 FF FF FF 03 00 00 00 02 FF FF FF 02 00 00 00 01 FF FF FF 01 00 00 00 00 0F FF FF 00 00 00 00 Hexadecimal

4 Gbyte Memory Organisation

CSA Rob Williams Pearson Education (c) 2006

CSA ch 06 - p 69

I/O Dev1 CPU I/O Dev2

I/O Dev3

RAM2

80 0000 80 002F

RAM1

ROM Motherboard

10 0000 2F FFFF

00 0000 01 FFFF

MEMORY MAP

Memory layout for a Memory-mapped I/O Scheme


ori.b #bmask,OP_reg andi.b #$f7,OP_reg asl.b (a5) not.b OP_reg bclr #1,OP_reg bset #2, (a2) ; logical OR a mask to set a port bit ; logical AND a mask to clear a port bit ; shift port bits left for display purposes ; shift port bits right for display pur poses ; test a port bit and leave it 0 ; test a port bit and leave it 1

CSA Rob Williams Pearson Education (c) 2006

CSA ch 06 - p 70

I/O Dev1

I/O Dev2

I/O Dev3

RAM2

RAM1

ROM

10 0000 2F FFFF 380 400

00 0000 01 FFFF

MEMORY MAP

I/O PORT MAP

Memory and I/O layout for an I/O-mapped scheme

CSA Rob Williams Pearson Education (c) 2006

CSA ch 06 - p 71

CSA Ch 07
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 72

7. CSA - the Intel Pentium


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

FG13054 USA HF

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA BB CC DD EE FF GG HH II JJ KK

Socket 478 for the Pentium 4

Slot A processor card with a Pentium II

CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 73

Bus Interface Level I D cache TLB 8kBytes MMU Addr Trans Level I Code cache TLB 8kbytes MMU Addr Trans BTB BPL

Control Unit
Microcode ROM

Prefetch buffers vpipe upipe decode decode


CPU Registers

Floating point pipeline

Pentium subsystems schematic

CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 74

Name
P24T P54C P55C P54CTB Tillomook P6 Klamath Deschutes Covington Mendocino Dixon Katmai Willamette Tanner Cascades Merced McKinley Foster Madison

Processor
486 Pentium OverDrive, 63 or 83MHz, Socket 3 Clossic Pentium 75-200MHz, Socket 517, 3.3v Pentium NWX 166-266MHz, Socket 7, 2.8v Pentium MMX OverDrive 125+, Socket 517, 3.3v Mobile Pentium MMX 0.25 m, 166-266MHz, 1.8v Pentium Pro, Socket 8 Original Pentium II, 0.35 m, Slot-I Pentium 11, 0.25 m, Slot 1, 256 Kbyte LII cache Celeron PII, Slot-I, with no L2 cache Celeron, PII with 28 Kbyte L2 cache on die Mobile Pentium IIPE, 256 Kbyte on-die L2 cache Pentium III, PII with SSE instructions Pentium III, on-die L2 Pentium 111 Xeon PIll, 0.18 m, on-die L2 P7, First IA-64 processor, on-die 12, 0.18 m 1 GHz, Improved Merced, IA-64, 0.18 m, copper interconnects Improved PIII, IA-32 Improved McKinley, IA-64, 0.13 m

CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 75

31

15

AH BH CH DH SI DI BP IP SP

AL BL CL DL

EAX EBX ECX EDX ESI EDI EBP EIP ESP EFlags Base Address Limit CSDCR SSDCR DSDCR ESDCR FSDCR GSDCR
0

Flags CS SS DS ES FS GS
15 0 31

Access

63

52 51 019

20 19

TSS selector LDT selector

TSS base address LDT base address IDT base address GDT base address

TSS limit LDT limit IDT limit GDT limit CR0

TR LDTR IDTR GDTR

CR1 Page Fault Service Routine CR2 Page Dir Base Reg CR3
31 12 0

i80x86/Pentium CPU Register Set

CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 76

MOV EAX,1234H INC EAX CMP AL,Q MOV maxval,EAX DIV DX

; load constant value 4660 into 32 bit accumulator ; add 1 to accumulator value ; compare the ASCII Q with the LS byte value in EAX ; store accumulator value to memory variable "maxval" ; divide accumulator by value in 16 bit D register

EBX: Base registers hold addresses pointing to data structures, such as arrays in memory. LEA EBX,marks ; initialize EBX with address of the variable "marks" MOV AL,[EBX] ; get byte value into AL using EBX as a memory pointer ADD EAX,EBX ; add 32 bits from EBX into accumulator MOV EAX,table[BX] ; take 32 bit value from the "table" array using the value in BX as the array index ECX: The Count register has a special role as a counter in loops or bit shifting operations. MOV ECX,100 ..... for1: ..... LOOP for1 ; initialize ECX as the FOR loop index ;symbolic address label ; decrement ECX, test for zero, JMP back if non-zero

EDX: The Data register can be involved during input/output data transfers or when executing integer multiplication and division. Otherwise it is generally available for holding variables. IN AL,DX MUL DX ; input byte value from port, with 16 bit port address in DX ; multiply A by value in D

ESI: Source Index register is a pointer for string or array operations within the Data Segment. LEA ESI,dtable ; initialize SI with memory address of variable "dtable" MOV AX,[EBX+ESI] ; get word using Base address and Index register EDI: Destination Index register is a pointer for string or array operations within the Data Segment. MOV [EDI],[ESI]
CSA Rob Williams Pearson Education (c) 2006

; moves a 32 bit word from source to destination locations in memory CSA ch 07 - p 77

EBP: The Stack Base Pointer register is used as the stack frame pointer to support HLL procedure operations. It is taken as an offset within the Stack Segment. ENTER 16

; saves EBP on stack, copies ESP into EBP, and subtracts 16 from ESP

EIP: The Instruction Pointer (Program Counter) holds the offset address of the next instruction within the current Code Segment. JMP errors ; forces a new address into EIP

ESP: The Stack Pointer holds the offset address of the next item available on the stack within the current Stack Segment. CALL subdo PUSH EAX ; call a subroutine (subdo), storing return address on stack ; save 32bit value in accumulator on stack

EFLAG: Flag Register contains CPU status ags, implicated in all conditional instructions. JGE back1 LOOP backagin ; tests sign ag for conditional jump ; tests zero ag for loop exit condition

CS - GS: These 16 bit Segment Selector registers were originally introduced to expand the addressing range of the i8086 processor while maintaining a 16 bit IP. The Segment Register is added to the EIP register to form a 32 bit address. CSDCR - GSDCR: 64 bit Code Segment Descriptor Cache Register holds the current Code Segment Descriptor, which includes: Base address, size Limit and Access permissions. The Segment Descriptor is obtained from either the Global or Local Descriptor Tables. TR: The Task Register holds the 16 bit segment selector, the 32 bit base address, the 16 bit size limit and the descriptor attributes for the current task. It references a TSS descriptor in the Global Descriptor Table (GDT). When a task switch occurs, the Task Register is automatically reloaded. IDTR: The 48bit Interrupt Descriptor Table Register holds the base address and size limit of the current Interrupt Vector Table (IVT). GDTR: The Global Descriptor Table Register holds the segment descriptors which point to universally available segments and to the tables holding the Local Descriptors. LDTR: Each task can use a Local Descriptor Table in addition to the Global CSA Rob Williams CSA ch 07 - p 78
Pearson Education (c) 2006

Descriptor Table. This register indicates which entry in the Local Segment Descriptor Table to use. CR3: This Control Register points to the directory table for the Paging Unit. CR2: This Control Register points to the routine which handles page faults which occur when the CPU attempts to access an item at an address which is located on a non-resident memory page. The service routine will instigate the disk operation to bring the page back into main memory from disk.

CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 79

15

Flags B D H SP PC

A C E L

i8080 CPU Register Set from 1975


1. data movement (copying) 2. data input/output operations 3. data manipulation 4. transfer of control 5. machine supervision

Classes of CPU instructions


MOV LEA CALL RET PUSH POP copies data from location to location, register or memory load effective address calls to a subroutine return from a subroutine push an item onto the stack, possibly as a subroutine parameter pop an item off the stack

INC/DEC increment or decrement ADD SUB CMP TEST JZ LOOP ENTER LEAVE JMP INT CSA Rob Williams Pearson Education (c) 2006 arithmetic integer addition arithmetic subtraction for 2s complement integers compare 2 values, a subtract with no result, only setting ags bit testing conditional jump implements a FOR loop by decrementing the CX register sets up a subroutine (procedure) stack frame cleans up a stack frame on exit from a subroutine a dreaded jump instruction software interrupt to get into an operating system routine

AND/OR/XOR logical operators

CSA ch 07 - p 80

1. the action or operation of the instruction, 2. the "victims" or operands involved, 3. where the result is to go.

0 - 3 bytes

1 - 2 bytes

0 - 1 bytes

0 - 1 bytes

0, 1, 2 or 8 bytes

Prex

Opcode D W

Operand MOD REG R/M

S I B

Displacement / Immediate Data

EAX ECX EDX EBX ESP 2EH 3EH 36H 26H 64H 65H 66H B8H F0H F3H CSEG DSEG SSEG ESEG FSEG GSEG 32bit mode 16bit mode Lock REP W=0 W=1 0 REG is source 1 REG is destination 000 001 010 011 100 101 110 111 AL CL DL BL AH CH DH BH AX CX DX BX SP BP SI DI R/M 000 001 010 011 100 101 110 111 MOD=00 (BX+SI) (BX+DI) (BP+SI) (BP+DI) (SI) (DI) direct (BX) MOD=01 [ESI] [EDI] 00 01 10 11 Memor y Memory+d8 Mem+d32/d16 Register [EAX] 00 [ECX] 08 [EDX] 10 [EBX] 18 20 [EBP] 28 30 38 01 09 11 19 21 29 31 39 02 0A 12 1A 22 2A 32 3A 03 0B 13 1B 23 2B 33 3B 04 0C 14 1C 24 2C 34 3C 05 0D 15 1D 25 2D 35 3D

ESI EDI 06 0E 16 1E 26 2E 36 3E 07 0F 17 1F 27 2F 37 3F

MOD=10

(BX+SI+d8) (BX+SI+d16) (BX+DI+d8) (BX+DI+d16) (BP+SI+d8) (BP+SI+d16) (BP+DI+d8) (BP+DI+d16) (SI+d8) (DI+d8) (BP+d8) (BX+d8) (SI+d16) (DI+d16) (BP+d16) (BX+d16)

d8 - a byte of data d16 - a 2 byte word

Pentium instruction code elds


CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 81

03 C3 ADD AX,BX _____________________________________ 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 ------------ | | --- ----- ----ADD op | W rd | o AX BX Des t | | | Reg -Reg | | mode | | des t i na t i on sou r ce

66 B8 00 00 00 00 00 00 12 00 MOV EAX,12H ____________________________________________________________________________ 0 1 1 0 0 1 1 0 1 0 1 1 1 0 0 0 0000 0000 0000 0000 0000 0000 0001 0010 --------------- ------- | ------------------------------------------32b i t p r ex M V op W r d AX O o im ed i a t e da t a m

3C 71 CMP AL,q __________________________________ 0 0 1 1 1 1 0 0 0 1 1 1 0 0 0 1 ------------- | ---------------C P A op M By t e Im ed i a t e da t a m


31 0

ID VIP VI AC VM R

N IOP O

ID VIP VI AC VM RFR NT IOPL O D IE T S Z A P C

identication ag for CPUID availability vir tual interrupt pending vir tual interrupt active alignment check vir tual 8086 mode active resume task after breakpoint interrupt nested task i/o privilege level arithmetic overow error direction of accessing string arrays external interrupt enable trap, single step debugging, generates an INT #1 after each instruction sign, MS bit value zero, result being zero auxiliar y carr y, used by BCD arithmetic on 4 LS bits parity, operand status carr y, indicates an arithmetic carry or borrow result

CPU status ag register


CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 82

CMP AL,q

. . . . . . . . .

CMP sets the Z ag

CPU EFLAG Register

JZ end
Data Register Direct

JZ tests the Z ag

MOV EAX,EBX +++ +++


Immediate Operand (IP indirect)

MOV EAX,1234 ++++


Memory Direct

MOV EAX,[var1] ++++++


Address Register Direct

The assembler distinguishes 1234 from [1234]

LEA EBX,var1 ++++


Register Indirect

MOV EAX,[EBX] +++++


Indexed Register Indirect with displacement

MOV EAX,[table+EBP+ESI] +++++++++++++++ MOV EAX,table[ESI] ++++++++++


CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 83

prefetch buffer Pre fetcher unit


PC

decoderoperand store execute stage 1 read result

Control Instructions

Branch Detector

Decoder logic

Data

Integer ALU

Fetch

Decode1 Readin Execute Writeback

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 System Clock

JMP NOP NOP NOP NOP AND

ADD JMP NOP NOP NOP NOP

ADD JMP NOP NOP NOP

ADD JMP NOP NOP

ADD JMP NOP

Parallelization by pipelined operation


CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 84

From Main Memory

8kB Data Cache

LI

8kB Code Cache

F/Point V-pipe U-pipe decoder

CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 85

Debugger tool-bar

RMB click here

Output Window Editor Window with source code breakpoint mark and IP index mark CPU Registers Memor y Window with hex dump of memory

MS VC++ Developer Studio debugger screen

CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 86

/* demo of assembler within a C prog*/ #include <stdio.h> #include <stdlib.h> int main (void) { char format[] = "Hello World\n" __asm { mov ecx,10 Lj: push ecx lea eax,format push eax call printf add esp,4 pop ecx loop Lj } return 0; }

//declare variables in C

;switch to inline assembler ;initialize loop counter ;loop count index saved on stack ;address of string, stack parameter ;use library code subroutine ;clean 4 byte parameter off stack ;restore loop counter ready for test ;dec ECX, jmp back IF NZ ;back to C

[F1] [F4] [ F5] [F7] [ F7] [F9] [F10] [F11] [ALT][TAB]

HELP go to next error run the program build executable code compile only set breakpoint single step (over funtions) single step into functions toggled windows backwards/forwards

CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 87

1. CPU registers 2. Program memor y with labels and disassembled mnemonics 3. Data memory with ASCII decode table 4. Output screen for your program under test 5. Stack, but only for the return addresses.

Debug

Restar t debugger Stop Disassembly Display Stack Display Memory Display Registers Display Variables Watch Quick Watch

debugger Break execution Show instruction Step into Step over Step out of Run to cursor

Debug Toolbar in VC++ Dev Studio

CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 88

open the Start Menu on the Taskbar. You can the nopen applications on the desktop, this switches between desktop, Taskbar and Start menu If you already have the Start menu, [Tab] switches between Applications. Alt [F4] terminate current application This can also terminate Windows if you are on the desktop! Alt [Tab] switch to next window Shift Alt [Tab]switch to preceding window [ESC] this sometimes cancels the previous action [F1] display the On-line Help for applicatioons Shift [F1] context sensitive help [F2] If an icon is highlighted you can change its name [F3] get Find

[ESC] [Tab]

Keyboard Shortcuts for Windows

CSA Rob Williams Pearson Education (c) 2006

CSA ch 07 - p 89

CSA Ch 8
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 8 - p 90

8. CSA - Subroutines
. . . average(&maths); . . . . . .
Main Program

1 2
return 1 return 2

average( ) {

. . .

average(&english);

Subroutine

average(&english);

. . . average(&maths); . . . . . .

1 2
return 1 return 2

average( ) {

. . .

3
return 3 return 4

average(&taxes);

. . . average(&ages); . . . . . .

DLL Subroutine

Program A

Program B

The "where to return to?" problem


. . . average(&m); . . . . . . Main Program

call

average( ) {

Stack area

. . . . . .

ret addr
call

return

ret

EIP
}

Subroutine

The Stack solution


CSA Rob Williams Pearson Education (c) 2006

CSA ch 8 - p 91

ESP EIP

EAX

CPU

System Bus

Stack Main Memor y

System stack in main memory, SP register in CPU

CSA Rob Williams Pearson Education (c) 2006

CSA ch 8 - p 92

#include <stdio.h> #define NCLASS 10 int maths_scores[NCLASS]; int tech_scores[NCLASS]; oat average(int x, int * y) { int i; oat av; for (i=0; i<x; i++) { av += *y++ ; } return av /= x; } void main( void) { int i; ..... printf("Average of maths = %3.1f\n", average( NCLASS, maths_scores)); ..... printf("Average of technology = %3.1f\n", average( NCLASS, tech_scores)); ...... }

Stack growing Stack downwards in memory


ESP PUSH EAX POP EBX

PUSH EAX ;push 32bit word in A onto stack CALL printf ;do something POP EBX ;pop the 32bit word from stack

Stack operation

CSA Rob Williams Pearson Education (c) 2006

CSA ch 8 - p 93

ADD ESP,4 SUB ESP,256

;scrub a longword off the stack ;open up 256 bytes of space on stack

1. to save the return address during PROCEDURE calls 2. to pass parameters into PROCEDURES 3. to allocate Local Variable storage space (stack frame) 4. as temporary scratch-pad storage for register values

Uses of the system stack

CSA Rob Williams Pearson Education (c) 2006

CSA ch 8 - p 94

setting up the stack frame

<-- clearing down the stack frame

Disassembled C program with stack operations

CSA Rob Williams Pearson Education (c) 2006

CSA ch 8 - p 95

Stack growing

73 10 40 00 0A 00 00 00 30 5A 41 00

return address NCLASS maths_scores

stack area

Stack Growing

CSA Rob Williams Pearson Education (c) 2006

CSA ch 8 - p 96

EBP stack frame 1 params 1 ESP ret add 1 EBP ESP params 1 ret add 1 EBP 1 loc vars params 1 ret add 1 EBP 1 loc vars params 2 EBP ESP ret add 2 EBP 2 loc vars ESP stack frame 2 EBP params 1 ret add 1 EBP 1 loc vars ESP params 1

FFFF FFFF

Stack grows

0000 0000 Main program sets up calls parameters and return address subr tn 1 installs local variables calls subr tn 2 returns subr tn 1 Main program returns

02 00 00 00 80 31 41 00 80 FF 12 00

space for av - current Head of Stack space for i Stack Growing old EBP value

Subroutine calls with stack frame data

CSA Rob Williams Pearson Education (c) 2006

CSA ch 8 - p 97

#include <stdio.h> char* getname(void) { char nstring[25]; printf("Please type your name: "); gets( nstring); putchar(\n); return nstring; //SERIOUS ERROR IN THIS PROGRAM } int main(void) { char* myname; myname = getname(); printf("%s\n", myname); return 0; }

Spot the error here!


Interrupt arrives
serial_isr:

mov eax,10;

. . . add EAX,3); . . . . . .

return

. . .

IRET

Interrupt Service Routine

Main Program

Interrupt Ser vice Routines (ISR) as h/w triggered subroutines


call filter1 lea esi,filter1 call [esi]

Late binding
CSA Rob Williams Pearson Education (c) 2006

CSA ch 8 - p 98

CSA Ch 09
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 99

9. CSA - Simple I/O


System Clock CPU Interrupt Request System Bus

I/O Subsystem Main Memory

I/O subsystem

1. Dedicated and Periodic polling 2. Interrupt driven 3. Direct Memory Access (DMA)

Different Input/Output Techniques

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 100

User Code HLL librar y O/S Routines HAL Hardware

Software Access to Hardware

1. Command Registers 2. Status Registers 3. Data Registers

Categories of Peripheral chip register

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 101

82C55A Functional Description


Data Bus Buffer This three-state bi-directional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. (CS) Chip Select. A low on this input pin enables the communcation between the 82C55A and the CPU. (RD) Read. A low on this input pin enables 82C55A to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to read from the 82C55A. (WR) Write. A low on this input pin enables the CPU to write data or control words into the 82C55A. (A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least signicant bits of the address bus (A0 and A1).
82C55A BASIC OPERATION INPUT OPERATION (READ) Port A Data Bus Port B Data Bus Port C Data Bus Control Word Data Bus OUTPUT OPERATION (WRITE) 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 Data Bus Port A Data Bus Port B Data Bus Port C Data Bus Control DISABLE FUNCTION X X X X X 1 X 1 1 0 Data Bus Three-State Data Bus Three-State
POWER SUPPLIES +5V GND GROUP A CONTROL GROUP A PORT A (8) I/O PA7PA0

BI-DIRECTIONAL DATA BUS DATA BUS D7-D0 BUFFER

GROUP A PORT C UPPER (4) 8-BIT INTERNAL DATA BUS GROUP B CONTROL GROUP B PORT C LOWER (4)

I/O PC7PC4 I/O PC3PC0

RD WR A1 A0 RESET

READ WRITE CONTROL LOGIC

GROUP B PORT B (8)

I/O PB7PB0

CS

FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER, READ/WRITE, GROUP A & B CONTROL LOGIC FUNCTIONS

(RESET) Reset. A high on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the input mode. Bus hold devices internal to the 82C55A will hold the I/O port inputs to a logic 1 state with a maximum hold current of 400A. Group A and Group B Controls The functional conguration of each port is programmed by the systems software. In essence, the CPU outputs a control word to the 82C55A. The control word contains information such as mode, bit set, bit reset, etc., that initializes the functional conguration of the 82C55A. Each of the Control blocks (Group A and Group B) accepts commands from the Read/Write Control logic, receives control words from the internal data bus and issues the proper commands to its associated ports. Control Group A - Port A and Port C upper (C7 - C4) Control Group B - Port B and Port C lower (C3 - C0) The control word register can be both written and read as shown in the Basic Operation table. Figure 4 shows the control word format for both Read and Write operations. When the control word is read, bit D7 will always be a logic 1, as this implies control word mode information.

A1 0 0 1 1

A0 0 1 0 1

RD 0 0 0 0

WR 1 1 1 1

CS 0 0 0 0

Data Sheet (page 3) for a Harris 82C55A Parallel Por t I/O Chip

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 102

Mode 0 - basic byte-wide input and output ports Mode 1 - bytes passed by strobed (asynchronous) handshake Mode 2 - tri-state bus action

D7 D6 D5 D4 D3 D2 D1 D0

Control Register
C0 - C3: 1 - input, 0 - output B0 - B7: 1 - input, 0 - output Mode: 0 - basic, 1 - strobed C4 - C7: 1 - input, 0 - output A0 - A7: 1 - input, 0 - output Mode: 00 - basic, 01 - strobed, 10 - bus 1 - set port modes

Control Register for the 8255 PIO

Alternative I/O or Memory mapping

// Win-98. Initializes 8255 at 0x1f3: Port A IN; B OUT; C OUT outp((short)0x1F3, 0x90); // init 8255 cmnd reg

Initialization using C

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 103

CPU Interrupt Request

System Bus A21A23 A0-A19 D0-D7 A0-A1 status reg command reg data regs I/O Subsystem

PROM Memory
0

C/S RAM

I/O C/S

Memor y decoder

Accessing Registers in Memory-mapped I/O


Device
PROM1 RAM1 RAM2 RAM3 I/O

Size
1MB 2MB 2MB 2MB 4B

Address Pins
20 21 21 21 2

Address bus
000x ++++ ++++ ++++ ++++ ++++ 001+ ++++ ++++ ++++ ++++ ++++ 010+ ++++ ++++ ++++ ++++ ++++ 011+ ++++ ++++ ++++ ++++ ++++ 111x xxxx xxxx xxxx xxxx xx++ aliases

Address range
00 0000 - 0F FFFF 20 0000 - 3F FFFF 40 0000 - 5F FFFF 60 0000 - 7F FFFF E0 0000 - E0 0003 E0 0004 - E0 0007 E0 0008 - E0 000B E0 000C - E0 000F

. . .

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 104

LOOP:

IN AX,RXSTATUS TEST AL,RXRDY JZ LOOP

;read status port Polling Loop ;test device status ;if no data go back again ;get Rx data & clear RXRDY flag ;test for end marker ;jmp out if finished ;save character in data buffer ;back for more input ;character string input complete

RxRDY

DATIN: IN AX,RXDATA OR AL,AL JZ COMPLETE MOV [DI],AL INC DI JMP LOOP COMPLETE: ....

do { while (!(*(BYTE*)RXSTATUS & RXRDY)) { } ;/* wait for data */ } while (*pch++ = *(BYTE*)RXDATA) ; /* check for a NULL */

Polled I/O in ASM & C

Intermittant timed polling

Dedicated spin polling

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 105

System buses operate at 500 Mbyte/sec Blocks of characters can be moved at100 Mbyte/sec Ethernet transfers data at 10 Mbytes/sec Telephone call needs 8 Kbyte/sec Serial lines frequently run at 1 Kbyte/sec Epson printers operate at 100 byte/sec Keyboards send at 4 byte/sec

Relative device speeds

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 106

/* io.h

68k header file with h/w definitions */


-1 -2 0 -1 0

/* messages */ #define PAPER_OUT #define DE_SELECT #define YES #define NO #define OK

/* address, offsets and setting for M68681 DUART */ #define DUART 0XFFFF80 /*base address*/ #define ACR 9 /*aux control reg */ #define CRA 5 /*command reg A */ #define MRA 1 /*mode reg A */ #define CSRA 3 /*clock select A */ #define SRA 3 /*status reg A */ #define RBA 7 /*rx reg A*/ #define TBA 7 /*tx reg A */ #define RXRDY 1 /*bit mask for rx ready bit */ #define TXRDY 4 /*bit mask for tx ready bit */ /*Settings for the Motorola M68230 Parallel Interface Timer These only deal with mode 0.0, and for ports B and C No details about the timer. */ /* PI/T offsets and adresses, PIT registers are all on odd addresses */ #define PIT 0Xffff40 /*address of PI/T */ #define BCR 0Xf /*offset for port B cntrl Reg*/ #define BDDR 7 /*offset for B data direction*/ #define BDR 0X13 /*offset port B data reg */ #define CDR 0X19 /*offset port C data reg */ /* Parallel port settings masks and modes */ #define MODE0 0X20 /* mode 0.0, 2X buff i/p, single buff o/p */ #define MODE01X 0X80 /* mode 0.1X, unlatch i/p, 1X buff o/p */ #define OUT 0XFF /* all bits output: 0 - i/p, 1 - o/p*/ #define STROBE_MINUS 0X28 /* strobe printer -ve */ #define STROBE_PLUS 0x20 /* strobe printer +ve */ #define PRINT_ST 1 /* paper out pin 00000001 */ #define PAPER_ST 2 /* paper out pin 00000010 */ #define SELECT_ST 4 /* selected pin 00000100 */

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 107

/*Initialization and data transfer for 68k SBC */


#include "io.h" /* set up Mc68681 DUART serial port A only */ void dinit() { register char *p; register int i; p = (char *)DUART; *(p+ACR) = 128; /* *(p+CRA) = 16; /* *(p+MRA) = 19; /* *(p+MRA) = 7; /* *(p+CRA) = 5; /* *(p+CSRA)= 187; /* set baud rate */ reset Rx */ no modem, no PARITY, 8 bits */ no ECHO, no modem cntrl, 1 STOP */ enable Rx & Tx */ Rx & Tx at 9600 */ /* set to base address of PI/T */ /* mode 0.0 */

p = ( char *) PIT; *(p + BCR ) = MODE0; *(p + BDDR ) = OUT; }

for(i=0; i != 1000;i++) ;/* init delay*/ /* set up 68230 PIT for print out on port B */ void pinit() { char *p; p = ( char *) PIT; /* set to base address of PI/T */ *(p + BCR ) = MODE0; /* mode 0.0 */ *(p + BDDR ) = OUT; } /* get char from serial port A char get() { register char *p; returns character */

p = (char *)DUART; while ( !( *(p+SRA) & RXRDY )) { }; return *(p+RBA); } /* put character c to serial port A */ void put( char c) { register char *p; p = (char *)DUART; while ( !( *(p+SRA) & TXRDY )) { }; *(p+TBA) = c; }

/* block here */

/* block here */

/* put string to serial port A using put routine */ void puts(char* p) { while( *p ) put(*p++); put(\n); }

Continues

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 108

/*put character to parallel port */ int print(int c) { register char * p ; p = ( char *) PIT; while ( *(p + CDR) & PRINT_ST ) { if ( !( *(p + CDR) & PAPER_ST) ) return (PAPER_OUT) ; if ( !( *(p + CDR) & SELECT_ST) ) return ( DE_SELECT); } *(p + BDR) = c; /*send data */ *(p + BCR) = STROBE_MINUS;/* strobe positive */ *(p + BCR) = STROBE_PLUS;/* strobe negative */ return OK ;

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 109

Brr Brr! Brr Brr

Telephonic Interruptions
CPU

Interrupt Request

System Bus

Main Memory

I/O A

I/O B

I/O C

PIC CPU

Interrupt Request

System Bus

Main Memory

I/O A

I/O B

I/O C

Alternative interrupt arrangements


CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 110

Int Function Number 77 Hard Disk2 76 Hard Disk1 75 8087 74 PS/2 Mouse 73 Soundcard 72 Network 71 Redirected 70 RTC ........... 18 17 16 15 14 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 BIOS/TOD BIOS/softboot BIOS/print BIOS/KBD BIOS/comms BIOS/disk BIOS/msize BIOS/check BIOS/Video LPT1: FDC SoundCard COM1: COM2: ---KBD: System Timer

Source IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 IRQ2 IRQ8 INT INT INT INT INT INT INT INT INT IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 PIC 1

IRQ0 IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15

to CPU interrupt

PIC 2

Screen dump to printer Numeric Overow Breakpoint NMI, Power fail Single Step Trace Integer Divide Error

Part of the PC Interrupt Vector Table (IVT)

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 111

Displaying PC IRQs using Windows NT

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 112

PIC IVR table

CPU Interrupt request

IVR main() isr I/O chip

IVT Memor y

Locating the Interrupt Service Routine

1. I/O data transfer request 2. Software TRAP (SVC) 3. Machine Failure 4. Real-time Tick 5. Run-time Software Error 6. System Reset or Watchdog

Possible Sources of Interrupts


CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 113

System Privileged facilities

User Privilege Interrupt request

Imposing access controls using interrupts

mouse activity

Interrupts per second


CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 114

ISR
msecs++ ? msecs=0 secs++ ? secs = 0 mins++ ? mins = 0 hrs++ ? hrs = 0

Interrupt request msecs secs mins hrs

Data Variables in Memory


990 59

Display Routines
Display secs

Display mins 59 01 Display hrs

Hours

Mins

Secs

Shared data corruption problem


rte

1.disable interrupts 2. serialise the access 3. use a semaphore

Critical region protection


CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 115

Tick Flag tickF++ ISR Interrupt request ? tickF=0 msecs++ ? N No tick

Data Variables in Memory msecs secs mins hrs 990 59 59 01

msecs=0 secs++ ? N

secs = 0 mins++ ? N

mins = 0 hrs++ ? hrs = 0 N Display secs Display mins Display hrs N

Serialized access to shared data

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 116

Transmit Data Buffer putc( ) Tx Dev Driver Receive Data Buffer Rx Dev Driver Rx ISR Tx Interrupt request Tx ISR UART Tx data

User Application

getc( )

Rx Interrupt Rx data request

Operating system managed I/O


CPU

System Bus data I/O Subsystem Main Memory source destination count DMA Controller

Using DMA to Transfer Data


Channel 0 1 2 3 4 5 6 7 CSA Rob Williams Pearson Education (c) 2006 Function DRAM refresh SoundBlaster Floppy Drive Width 8 bits 8 bits

cascaded to second DMA controller SoundBlaster 16 bits

CSA ch 09 - p 117

Designation of the PC DMA channels

Input Process Output Input Process Output

1 1 1 1 1 1 2 3 2 3 2 3

2 2 2

3 3 3

time

The importance of overlapping operations


#include <stdio.h> int main(void) { int answer; do { printf("please enter a single letter: "); answer = getchar(); putchar(\n); printf("%c\n",answer); } while (answer != E); return 0; }

Problems with keyboard input

CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 118

please enter a single letter: A A please enter a single letter: please enter a single letter: B B please enter a single letter: please enter a single letter:

? ?

Key codes in hex

A CR B CR

please enter a single letter: A 41 please enter a single letter: 0a please enter a single letter: B 42 please enter a single letter: 0a please enter a single letter:

#include <stdio.h> int main(void) { int answer; do { printf("please enter a single letter: "); answer = getchar(); getchar( ); putchar(\n); printf("%c\n",answer); } while (answer != E); return 0; }

scanf("%c%*c", &answer);
CSA Rob Williams Pearson Education (c) 2006

CSA ch 09 - p 119

CSA Ch 10
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 120

10. CSA - Serial Communications

data - compression and coding schemes, quantity timing - synchronization of rx with tx: frequency and phase signaling- error handling, ow control, and routing

Three key issues for communication

100s

50s

Tx

Rx

Receiver must sample near the middle of an incoming bit

CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 121

Tx Clock write data bit to line Data Rx Clock sample data now

Clock drift problems for asynchronous receivers


SYN - special ag Byte to assist receiver with Byte-level synching. only used when the channel is operating in Synchronous mode SOH - Start of a message header STX - Start of message text block ETX - End of message text block. Messages can be split into multiple blocks. EOT - End of message transmission

Parity Bits - simple to apply, not ver y secure Block Checksums- simple to apply, not ver y helpful Polynomial Division- more complex, better security

Error Detection and Correction Techiques

CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 122

1 1 Data word 0 1 0 1 0 1 Parity bit

XOR 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 00001011 00001100 etc 0 1 1 0 1 0 0 1 1 0 0 1 0

Using XOR gates to compute parity

Data to be sent

Parity is Computed and appended to make EVEN for transmission 0110_0111 1

Transmit

New Parity value computed and compared 0110_0111 1 no error detected 0111_1110 0 error detected 0110_0101 0 no error detected !

0110_0111

No errors Error 0111_1110 1 Errors 0111_1101 0

0111_0110

0111_0110 1

0111_0100

0111_0100 0

Error detection using single appended parity bit

CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 123

p1
p1 = d 1 XOR d 3 XOR d 4 p2 = d 2 XOR d 3 XOR d 4 p3 = d 1 XOR d 2 XOR d 4

d3 d4 p3

p2 d2

d1

Triple Parity Bit Assignment


8
p4

7
d4

6
d3

5
d2

4
p3

3
P d1

2
p2

1
p1

Assigning Parity Bits to Longer Words


Parity bits Data bits p 1 2 0 2 4 1 3 8 4 4 16 11 5 32 26 6 64 57 7 128 120 8 256 247

2p d

d = 2p (p + 1)

4d-3p

Data and parity bits to achieve single error correction


[1010100] x 1 1 7 6 5 4 3 21 d d d p d p p 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 = [001] So p3 = 0, p2 = 0, and p1 = 1 giving [ 1 0 1 0 1 0 1 ] for transmission

Calculating a 4d-3p Syndrome (Transmitter)


CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 124

error here [1000101] x 1 1 1 1 0 0 0

1 1 0 0 1 1 0

1 0 1 0 1 0 1

= [101]

The 4d-3p syndrome (receiver) with 1 bit error

No error p0 Syndrome agrees 0

Single error error nonzero -> error

Double error agrees nonzero confused

Single error correction, double error detection by multiple parity

CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 125

2 bytes Type

2 bytes Length

6 bytes Address

< 256 bytes Data

2 bytes Checksum

Motorola S-Record format with trailing checksum

S0 03 0000 FC S2 24 010400 46FC26002E7C000808006100005E610000826100033C46FC270023FC00010678 6B S2 24 010420 000C011023FC00010678000C011423FC00010678000C011823FC00010678000C 6D S2 24 010440 011C610003A4303C271053406600FFFC46FC21006100057A4E4B000000004E75 3B

.......
S2 24 012200 0968584F4878004C4EB900010928584F206EFFFC524810BC0004602248790001 7D S2 24 012220 21CA4EB900010968584F487800484EB900010928584F206EFFFC524842104E5E 84 S2 08 012240 4E750000 D1 S8 04 000000 FB

Example Fragment of a Motorola S Record Format File

08 + 01 + 22 + 40 + 4E + 75 + 00 + 00 = 12E forget the 1 as overow, leaving 2E ( 0010 1110 ) invert the bits 1101 0001 ( D1 ) THE CHECKSUM !

CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 126

1 1 1 0 0 ______________ 1 0 1 | 1 1 0 0 1 0 0 1 0 1 ----1 1 0 1 0 1 ----1 1 1 1 0 1 ----1 0 0 1 0 1 -----

1 1 1 1 0 _______________ 1 0 1 |1 1 0 0 1 1 0 1 0 1 ----1 1 0 1 0 1 ----1 1 1 1 0 1 ----1 0 1 1 0 1 ----0 0 0 -> indicates 1 0 = Remainder no errors to send

Sender

Receiver

Calc. of a CRC at sender and receiver for data item 11001


1. All error bursts of 16 bits or less, 2. All odd numbers of bits in error, 3. 99.998% of all error bursts of any length.

CRC Generation using Shift Registers and XOR gates

CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 127

Echo back Hardware Control lines, RTS/CTS Software Control Codes, S/Q Frame-based Handshake Codes, ACK/NAK

Flow control techniques

Rx and Tx data

Rx and Tx data Xon / Xoff

CTS RTS

RTS CTS

control

hardware handshake

software handshake

RS232 ow control techniques

Serial links dedicated route, no addressing needed LAN broadcast transmission, receiver does the identication WAN selective routing can be dynamically changed

Data routing methods for serial communications


space / logic 0 +9v Idle / mark logic 1 / -9v

Star t lsb

msb Parity Stop

RS232 voltages representing ASCII 1 (31H)


CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 128

DCE ( 9 pin D-type) IBM COM1 Modem Por t -- 2 Rx Data 3 Tx Data 4 DTR 5 Ear th 7 RTS 8 CTS Ready to Send Clear to Send Data Terminal Ready
5 9 6 1

Socket Numbering

RS232 9-way D-type Pin Functions (COM1 & COM2)

Setting COM1 port Parameters with Hyperterminal

CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 129

/* Transmitter.c */ #include <stdio.h> int main(void) { FILE *dp; int c; if ((dp = fopen("COM2", "w"))==NULL) { printf("fail to open COM port\n"); return 1; } while ((c=getch()) != EOF) { fputc( c, dp); fflush(dp); } return 0; =============================================== /* Receiver.c */ #include <stdio.h> int main(void) { FILE *dp; int c; if ((dp = fopen("COM2", "r"))==NULL) { printf("fail to open COM port\n"); return 1; } while ((c= fgetc(dp)) != EOF) { putch( c); } return 0;

Exchanging messages across an RS232 link on a PC

CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 130

Pentium CPU

PIC

IRQ 4

Receive Transmit RS232 Serial link

16550 UART

Attaching a UART, serial line interface

CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 131

/* Filetrans.c */ #include <stdio.h> #include <conio.h> #define CNTRLZ 0x1A int main(void) { FILE * fp FILE * dp; int c; if ((fp=fopen("C:\TEMP\text.dat", "rt"))==NULL) { printf("fail to open data file\n"); return 1; } if ((dp = fopen("COM2", "wt")) == NULL) { printf("fail to open COM port\n"); return 1; } while ((c = fgetc(fp )) != EOF) { fputc( c, dp); } fputc(CNTRLZ, dp); fflush(dp);} fclose(fp);

/* Filereceive.c */ #include <stdio.h> #include <conio.h> #define CNTRLZ 0x1A int main(void) { FILE *fp; FILE *dp; int c; if ((fp=fopen("C:\TEMP\text.dat", "w"))==NULL) { printf("fail to open data file\n"); return 1; } if ((dp = fopen("COM2", "r")) == NULL) { printf("fail to open COM port\n"); return 1; } while ((c= fgetc(dp)) != CNTRLZ) { fputc( c, fp); } fflush(fp); fclose(fp); return 0; }

Slow inter-PC le transfers vis COM2


CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 132

#include <stdio.h> #include <conio.h> #include <windows.h> #include <winbase.h> HANDLE hCom; char inpacket[16], outpacket[16]; BOOL fSuccess; //////////////////////////////////////////////////// // Initializes PC COM2 port to non-blocking mode // void initcomm(void) { COMMTIMEOUTS noblock; DCB dcb; hCom=CreateFile("COM2", GENERIC_READ | GENERIC_WRITE, 0, NULL, OPEN_EXISTING, 0, NULL ); if (hCom == INVALID_HANDLE_VALUE) { dwError = GetLastError(); printf("INVALID_HANDLE_VALUE()"); } fSuccess = GetCommTimeouts(hCom, &noblock); noblock.ReadTotalTimeoutConstant = 1; noblock.ReadTotalTimeoutMultiplier = MAXDWORD; noblock.ReadIntervalTimeout = MAXDWORD; fSuccess = SetCommTimeouts(hCom, &noblock); fSuccess = GetCommState(hCom, &dcb); if(!fSuccess) printf("GetCommState Error!"); dcb.BaudRate = 9600; dcb.ByteSize = 7; dcb.fParity = TRUE; dcb.Parity = EVENPARITY; dcb.StopBits = TWOSTOPBITS; dcb.fRtsControl = RTS_CONTROL_HANDSHAKE; dcb.fOutxCtsFlow = TRUE; fSuccess = SetCommState(hCom, &dcb); if(!fSuccess) printf("SetCommState Error!"); else printf("Comm port set OK!0); } Continues

CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 133

////////////////////////////////////////////////// // Reads COM2, single character // IF !char on COM2 return 0, ELSE return ASCII char // char readcomm() { char item; int ni; fSuccess = ReadFile( hCom, &item, 1, &ni, NULL ); if (ni >0 ) return item; else return 0; } ////////////////////////////////////////////////// // tests and reads keyboard // IF !char on kbd return 0, ELSE return ASCII char // char readkbd() { if (kbhit() ) return _getch(); else return 0; }

Using COM2 in Non-blocking Mode

CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 134

Y roller

X roller IR emitter and sensor Mouse ball Optical disk sensors

Optical disk direction and speed sensing


-6v, Txdata +6v, RTS Rxdata

Mouse UART
X Y

1200kHz Crystal

Mouse Buttons

X & Y wheels

Arrangement for a PC Serial Mouse with UART


Sdio Serial por t Sclk Quadrature output XA XB YA YB Oscillator

Sensor & DSP

LED drive

Voltage regulator

Power on reset

Sensor array & DSP

LED light source

Desk top

Optical mouse image sensor DSP


CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 135

hardware issues plugs & sockets dont t: 25/9 pin, sockets/pins Tx and Rx pins confused - crossed vs uncrossed lead different plug congurations incorrect wiring of h/w ow controls (CTS/RTS) reversed internal IDC ribbon cables incorrectly assembled IDC ribbon cables incorrectly installed interface card (IRQ, dma, port no.) serial por t hardware not initialized incompatible transmission formats ASCII vs EBCDIC or Unicode line speed setting: 1200, 2400, 9600 bps error checks: odd/even/none parity ASCII char length: 7 vs 8 bits number of stop bits user dened packet lengths CR-LF line terminator differences in les tab vs multiple SP differences Word Processor control characters (Word) EOF problems ow control failure CTS input uncontrolled by receiver RTS/CTS talking to XON/XOFF intermediate buffers on end-to-end ow control unread echo characters on serial lines RAM buffer threshold problems software problems sending/receiving data through wrong channel incorrect device driver installed uninstalled device driver

Tips and hints on serial connection failure

CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 136

Control Isochronous Bulk Interrupt -

used by the root hub to pass on conguration instructions and data to the devices, especially used during the initialization period. timed data transfers for devices with real-time data streams. simple non-time sensitive USB is not an interrupt system, it depends on timed polling from the hub to pick up data, such as keyboard input. downstream Hub 1

upstream

Hub 3

host Hub 2

Hub 4

Hub 5 USB devices

Universal Serial Bus Connectivity


RAM ROM IP upstream port

Hub 6

USB interface

CU

ALU

SP downstream ports

DP Periphs

Intel 8x931 USB Peripheral Microcontroller


CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 137

direct digital connection

External modem

Local analogue line

Digital trunk lines

Local Internal analogue modem line

Using modems to transfer data on the telephone network


0 0 0 1 1 0 1 1 0 1 Data . . ... .. . .. .. . .. .. .. . .. .. .. . . .. . . . .. . .. . . . . .. .. .. .. .. .. .. .. . . ... ... . ..

... .. .. .. .. ... .. .... . .. .. .. .. .. .. .. . .. .. .. .. .. .. . .. . .. . . .. . . .. .. . . . . . . .. . .. . . . .. . .. .. .. .. . . . . .. . . . . . . . .. . . . . . .. . . . . . . . .. . . ... . . . . ... ... . ... . .

. .. .. ... ... .. .. .. . .. . .. .. .. .. .. . .. . . . .. . .. . .. .. .. .. . .. . . . . . . . . . . . . . . . . . . . .. . .. . .. . .. . . . . .. .. .. .. .. .. .. .. .. . .. . .. . .. . . .. .. . . ... .. ... .. . .. . .. . . .

ON / OFF Carrier

. . . . ... ... ... . . . . . .... ... ... ... ..... .... ... ... ... ...... .. ... .. .. .... ... .. .. . .. .. . . . . . . . . . . . .. .. .. . . . . . . . . . .. FSK . . . .. .. ... ... ... ... ... .. .. .. .. .. .. .. .. ... ... .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. . . . . . . . . .. . .. . . . .. . .. . . . .. . . . . . . . . . . .. .. . . . . . . . .. . . . . . .. .. .. .. .. .. .. .. .. . .. . .. . . . .. .. . . . . . . . . .. .. . . . . Frequency . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . . .. . . . .. .. . . .. .. .. . .. . .. . . . . . . . . . .. . .. . . . . . . . .. . . . . . . . . . .. .. .. .. .. .. . . . . . . . . .. .. . . . . . . . . .. . . . . . Shift Keying . . .. . .. . .. . . . .. . .. . .. . ... .. . .. . . . . . .. .. .... .... .... .... .. . .. .. ... ... .. ... ..... .. .. ... ... ..... .. .. .. .. ... . .... ... .. ... . . . .. .. . .

Frequency Modulation Technique


ITU Cat V.21 V.22 V.22bis V.29 V.32 V.32bis V.17 V.34 Capacity 300/600 bps 1200 bps 2400 bps 9600 bps 9600 bps 14.4 kbps 14.4 bps Fax 28.8 kbps Amplitude & Phase shift Type Frequency shift Phase shift Amplitude & Phase shift Phase shift Amplitude & Phase shift Amplitude & Phase shift

Modem Standards and Coding Schemes


CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 138

Command
ATA ATDnnn-nnnn ATL ATPDnnn-nnnn ATW ATH0 ATM0 ATM1 ATM2 ATO0 ATO1 ATY0 ATY1

Function
Answer incoming call Tone dials the phone number nnn-nnnn Redials last number dialed Pulse dial nnn-nnnn Wait for dial tone Hang up Speaker off Speaker is on until a carrier is detected Speaker is always on Puts modem in data mode Takes modem out of data mode Disable disconnection on pause Enable disconnection on pause

Some of the Hayes Modem AT Command Set

1 Data

. .. ..... ...... ..... ..... ..... ...... . .. ....... ....... .. .. ...... ..... .. ... ... . . . . .. .. .. .. ... .... ... .. .. ... .... ... .. ... .. ... .. ... . . . . . . . . ... . .. .. ... .. .. .. . .. .. .. .. .. .. .. .. .. .. .. . . . . .. . . . .. ... . .. . .. ... . .. ... . . . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..... . . . .... ..... . ..... ... ... .... ..... ... ... .......... ............ ........... .......... ........... ... .. ... .. .. .. ..... ... ..... .. .... ... ... ... ... .. .. .. .. .. . ... ... ... ... ..... ... ... .. .. .. .... ... .... ... ...... .... .... ... .. ..... ...... ...... ...... ..... ..... .. 01 10 11 00

1B1B

2B1Q

............ ............ .. ..... .. ..... ..... ........ .. .. ... ... .... . ...... .... ... .. .. .. .... ... .... ... . . . .. .... 3B1O . .... ... ... ... .. .. .. ..... ...... ..... ... ... ... .. .. . ............. . . ..... ... ... .... .... .... .... ....... ....... 000 011 011 010

Phase Modulation Increases the Bit Signalling Rate


CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 139

/2

r 0

- Phase

r - Amplitude - /2

Phase shift modem with a single carrier frequency signalling 0 or 1 with 0 or phase shift

Quad Phase, Single Amplitude /4, -/4, 3/4, -3/4 4 level QAM, 2B1Q

Oct Phase, Dual Amplitude 0, /4, /2, -/4, -/2, 3/4, -3/4, 8 level QAM, 3B1O

Oct Phase, Quad Amplitude, 32 level QAM V32 modems

Amplitude Phase Diagrams Illustrating some Modulation Schemes

CSA Rob Williams Pearson Education (c) 2006

CSA ch 10 - p 140

CSA Ch 11
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 11 - p 141

11. CSA - Parallel connections


SPP EPP ECP Standard Parallel Por t Enhanced Parallel Por t Extended Capability Por t 100 kbytes/sec 1 Mbytes/sec 5 MBytes/sec Output Input/Ouput Input/Ouput software operated h/w handshake circuits DMA with FIFO

PC Parallel Por t (Centronics) Standards


Pin D-25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18-25 SPP Strobe data bit 0 data bit 1 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 ACK BUSY PE Paper Out SLCT auto LF Error INIT SLCT IN GRND Host Printer Printer Busy Data lines Strobe
>0.1s >4s

ACK

1 14

The Centronics Standard Interface (SPP)


Computer Ready set Data byte Strobe Busy set Acknowledge Ready set Printer

Sequence of Events within a Centronics Data Transfer


CSA Rob Williams Pearson Education (c) 2006

CSA ch 11 - p 142

Bus free

Arbit

Device select

Transfer

Sequence of Phases within a SCSI Transfer


Pin D-25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18-25 EPP Write data bit 0 data bit 1 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 Interrupt Wait user def user def Strobe user def Reset Addr Strobe GRND Computer Printer

The Centronics Enhanced Interface (EPP / ECP)

1. tting a large memory buffer inside the printer 2. run a background print spooler 3. use a full multi-tasking system

How to prevent delays caused by a slow printer


CSA Rob Williams Pearson Education (c) 2006

CSA ch 11 - p 143

Pin 2 4 6 8 10 12 14 16 18 32 36 38 40 42 44 46 48 50

data bit 0 data bit 1 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 PARITY ATN BSY ACK RST MSG SEL C /D REQ I /O

Master Slave

7 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Vendor Group LUN Command (MSB) 0

Disk Logical block addr (LSB) No of blocks reserved FlagLnk

50

Small Computer Systems Interface (SCSI) and Command Packet


BSY - Busy indicates that someone is currently using the bus. SEL - Select allows the initiator to select a target and by the target to resume an interrupted session. C /D - Control / Data is controlled by the target to indicate whether control or data items are being transferrred on the data bus. I /O - Input / Output allows the target to denethe direction of the data transfer. ATN - Attention is used by the master to tell the slave that data is available on the bus. MSG - Message, activated by the target during the message phase of transfer. REQ - Request, used by the target device, signals to the master that data can be transmitted. It is part of the REQ / ACK handshake pair. ACK - Acknowledge, controlled by the initiator to conrm a transfer. RST - Reset bus, forces all attached devices to stop activity and reset the hardware.
CSA Rob Williams Pearson Education (c) 2006

CSA ch 11 - p 144

00 01 03 04 05 07 08 0A 0B 0F 10 11 12 25 26 2A 2E 2F

Group 1 Test unit ready Rezero unit Request sense Format unit Read block limits Reassign blocks Read Write Seek Read reverse Write le mark Space Inquiry Group2 Read capacity Extend addr rd Extend addr wr Write 7 verify Verify

13 14 15 16 17 18 19 1A 1B 1C 1D 1E

Verify Recover buffer Mode select Reser ved unit Release unit Copy Erase Mode sense Start / stop Receive diagnostic Send diagnostic Lock media

30 31 32 33 39 3A

Search data high Search data equal Search data low Set limits Compare Copy & verify

SCSI Message Codes

7400 7400 7400 HM82C11

PC 8 bit Bus Edge Connector

An 8 bit PC/ISA-bus Printer Interface Card


CSA Rob Williams Pearson Education (c) 2006

CSA ch 11 - p 145

i8253

i8255

i8255

An extended 16 bit PC/ISA-bus Parallel I/O Card


A
GND Reset DRV +5V IRQ2 -5v DQQ2 -12v OWS +12v GND SMEMW SMEMR IOW IOR DAK 3 DRQ3 DAK 1 DRQ1 DAK 0 CLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DAK 2 T/C ALE +5v 14.3MHz GND MEMCS16 IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DAK 0 DRQ0 DAK 5 DRQ5 DAK 6 DRQ6 DAK 7 DRQ7 +5v MASTER GND I /OCHCK D7 D6 D5 D4 D3 D2 D1 D0 I/O Ch Rdy AEN A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR MEMW SD08 SD09 SD10 SD11 SD12 SD13 SD14 SD15 GND RESET +5V IRQ2 -5v DQQ2 -12v SRDY +12v KEY SMEMW SMEMR IOW IOR DAK 3 DRQ3 DAK 1 DRQ1 REFRESH BCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DAK 2 TC BALE +5v OSC GND GND

Manual Port address set up switches

ISA 16 bit Bus Edge Connector

B
I /OCHCK SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOCHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 GND

D C
GND MEMCS16 IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DAK 0 DRQ0 DAK 5 DRQ5 DAK 6 DRQ6 DAK 7 DRQ7 +5v MASTER GND GND GND SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR MEMW SD08 SD09 SD10 SD11 SD12 SD13 SD14 SD15 KEY

D CA B

Stacking three 96x90mm PC/104 cards

EISA

A comparison of ISA Bus and PC/104 connectors

The PCI bus can operate in two modes: Multiplexed Mode A single 32 bit bus is shared by address and data information. This increases the effective bus width, but reduces the data rate. Burst Mode This is the same trick that EDO DRAM employs. After an address has been sent, several data items will follow in quick succession. The bridge is capable of assembling "packets" of data and bursting it through to the PCI bus when ready.
Pentium CPU System bus, 66MHz, 64bits PCI Nor th Bridge PCI Bus, 33MHz, 32bits Disk Controller ISA South Bridge ISA bus, 8.33MHz, 16bits

Graphics

Relationship of the PCI Bridge to Main Bus


Prefetch buffer

CPU

System Bus

Posting buffer

Prefetch buffer Posting buffer

PCI Bus

The PCI Bridge


CSA Rob Williams Pearson Education (c) 2006

CSA ch 11 - p 147

12V TCK GND TDO +5v +5V INTB INTD PRSTN 1 res PRSTN 2 GND GND res GND CLK GND REQ 5v I/O AD31 AD29 GND AD27 AD25 +3.3v C/BE 3 AD23 GND AD21 AD19 +3.3v AD17 C/BE 2 GND IRDY +3.3V DEVSEL GND LOCK PERR +3.3v SERR +3.3v C/BE 1 AD14 GND AD12 ADIO GND AD8 A07 +3.3v AD5 AD3 GND AD1 +5v I/O ACK 64 +5V +5v

TRST +12v TMS TDI +5v INTA INTC +5v res +5v I/O res GND GNO res RST +5v I/O GNT GND res AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3v AD22 AD20 GND AD18 AD16 +3.3v FRAME GND TRDY GND STOP +3.3v SDONE SBO GND PAR AD15 +3.3v AD13 AD11 GND AD9 C/BE 0 +3.3V AD6 AD4 GND AD2 ADO +5v I/O REQ64 +5v +5v

PCI Socket

Card 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Serial Number 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 00001011 00001100 00001101 00001011 00001111
ABCDEFGH

Plug n Play Sequence

Manufacturer Adaptec Compaq Creative Cyrix Epson HP Intel Matsushita Mitsubishi Motorola NCR Toshiba Tseng Labs

MID 9004 1032 10F6 1078 1008 103C 8086 10F7 1067 1057 1000 102F 100C

PID 36868 4146 4342 4216 4104 4156 32902 4343 4199 4183 4096 4143 4108

Example Plug and Play Identity Numbers


CSA Rob Williams Pearson Education (c) 2006

CSA ch 11 - p 149

GND D3 D4 D5 D6 D7 CD EN 1 A10 OUT EN A11 A9 A8 A13 A14 WE /PRG READY /BUSY +5v V 1 pp A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16 GND

PCMCIA Interface

GND CD DET 1 D11 D12 D13 D14 D15 CD EN 2 REFRESH IOR IOW A17 A18 A19 A20 A21 +5v V 2 pp A22 A23 A24 A25 RFU RESET WAIT INPACK REG SEL SPKR STSCHG D8 D9 D10 CD DET 2 GND

CSA Rob Williams Pearson Education (c) 2006

CSA ch 11 - p 150

CSA Ch 12
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 151

12. CSA - Memory hierarchy


CPU

A0-A31

4 Gbyte Memor y

Fully populated main memory


256 bytes

CPU registers - 0.5 ns


CPU Control Unit

words - 2 / 4 bytes lines - 32 bytes lines - 32 bytes pages - 4 Kbytes blocks - 4 Kbytes les - Mbytes

16 Kbytes

LI Cache Memory - 1 ns
Primary Cache Controller

256 Kbytes

LII Cache Memory - 2.5 ns


Secondary Cache Controller

512 Mbytes

Main Memory - 10 ns
Memory Management Unit

16 Mbyte

Disk Cache - 10 ns
Device Controller

80 Gbytes

Disk Storage - 10 ms
Administrative staff

20 Tbytes

Tape Backup - 10 min

Memor y Performance Hierarchy

CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 152

Facility DRAM SRAM SCSI Hard Disk CD-ROM CD-RW Jazz Zip DAT Floppy

Size 64 MB 32 MB 256 KB/10ns PCI card 10GB 10GB 650 MB 650 MB WORM RW 1 GB 1 GB 100 MB 100 MB 4 GB 4 GB 1.4 MB 1.4 MB

device SDRAM 168 pin DIMM EDO 72 pin SIMM SRAM chip IDE SCSI 32x IDE 2x IDE disk disk drive disk drive disk SCSI drive tape drive disk

Unit cost, 40 50 2 180 110 250 60 200 0.75 2.50 200 65 60 15 350 2.5 15 0.5

/ Mbyte 0.6 1.6 64 0.01 0.025 0.12 R 0.3 R

0.25 R 0.75 R 0.09 R 11 R

Memor y costs

Memor y location

CPU time

Memory access plot, showing locality effects


CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 153

Column index 0 1 2 3 4 5 6 7 8 9 10 . . . . 0 1 2 3 4 5 6 7 8 9 10 . . .

Row index

row 0

row 1

row 2

row 3

row 4

Array indexing with memory layout of array data

CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 154

#include <stdio.h> #include <sys/times.h> #include <limits.h> #define MAX 1000 clock_t times(struct tms* b); main () { int i, j; int big[MAX][MAX]; int sum, start, middle, end; struct tms tbuff; times( &tbuff); start = tbuff.tms_utime; for(i=0; i<MAX; i++) { for(j=0; j<MAX; j++) { sum += big[i][j]; /* <------------ i, j here */ }; }; times( &tbuff); middle = tbuff.tms_utime; for(i=0; i<MAX; i++) { for(j=0; j<MAX; j++) { sum += big[j][i]; /* <------------ j, i here */ }; }; times( &tbuff); end = tbuff.tms_utime; printf("First run time is %d \n",(middle - start)*1000/CLK_TCK); printf("Second run time is %d \n",(end - middle)*1000/CLK_TCK); }

Demonstrating cache action

rob [80] cc cache.c -o cache rob [81] cache First run time is 150 Second run time is 310 rob [82]

Results from the Cache Test


Estimate: 21 x 5ns x 106 + 13 x 5ns x 103 = 105ms
CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 155

Accessing along each row [i][j]

Accessing along each column [j][i]

Alternative access patterns (strides) for a 2-D array

CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 156

! 19

for(i=0; i<MAX; i++) {


mov0,%l0 st%l0,[%fp-8] ld[%fp-8],%l0 cmp%l0,1000 bge.L118 nop ! block 2

.L119: .L116: ! 20

for(j=0; j<MAX; j++) {


mov0,%l0 st%l0,[%fp-12] ld[%fp-12],%l0 cmp%l0,1000 bge.L122 nop ! block 3

.L123: .L120: ! 21

sum += big[i][j];

! 22

};

sethi%hi(-4000016),%l0 or%l0,%lo(-4000016),%l0 ld[%fp+%l0],%l4 sethi%hi(-4000012),%l0 or%l0,%lo(-4000012),%l0 add%fp,%l0,%l3 ld[%fp-8],%l0 sll%l0,12,%l2 sll%l0,5,%l1 sub%l2,%l1,%l2 sll%l0,6,%l1 sub%l2,%l1,%l1 add%l3,%l1,%l2 ld[%fp-12],%l0 sll%l0,2,%l1 add%l2,%l1,%l0 ld[%l0+0],%l1 add%l4,%l1,%l1 sethi%hi(-4000016),%l0 or%l0,%lo(-4000016),%l0 st%l1,[%fp+%l0] ld[%fp-12],%l0 add%l0,1,%l0 st%l0,[%fp-12] ld[%fp-12],%l0 cmp%l0,1000 bl.L120 nop ! block 4

A Fragment of asm output from SPARC compiler

.L124: .L122: ! 23

};

ld[%fp-8],%l0 add%l0,1,%l0 st%l0,[%fp-8] ld[%fp-8],%l0 cmp%l0,1000 bl.L116 nop ! block 5

.L125: .L118:

CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 157

CPU

Cache Control Unit

256 Kbyte 2ns SRAM Cache System Bus

512Mbyte 15ns DRAM Main Memory

I/O Subsystem

Cache Memory and Controller Unit

1. Folded address space, also known as Direct Mapping 2. Associative (content addressable) memory 3. Hashed mapping

Mapping Addresses from Main to Cache Memory

CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 158

TAG Memor y 111 110 101 100 011 010 001 000 4 0 11

Cache Memory

Main Memory 11111 111 11 11111 111 10 11111 111 01 11111 111 00 11111 110 11 11111 110 10 11111 110 01 11111 110 00 10100 101 11 10100 101 10 10100 101 01 10100 101 00 10100 100 11 10100 100 10 10100 100 01 10100 100 00 00000 111 00 00000 001 11 00000 001 10 00000 001 01 00000 001 00 00000 000 11 00000 000 10 00000 000 01 00000 000 00 Address

10

01

00

Address Folding for Direct Mapped Cache

CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 159

Status

TAG Memor y

Cache Memory

Main Memory 11111 111 11 11111 111 10 11111 111 01 11111 111 00 11111 110 11 11111 110 10 11111 110 01 11111 110 00 10100 111 11 10100 110 10 10100 101 01 10100 100 00 10100 011 11 10100 010 10 10100 001 01 10100 000 00 00000 111 00 00000 001 11 00000 001 10 00000 001 01 00000 001 00 00000 000 11 00000 000 10 00000 000 01 00000 000 00 Address

11

10

01

00

Associative Cache
A31-A24 TAG 01

Checking the Address in Associative Memor y

CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 160

1. on start-up of a new program 2. when the cache is too small to hold the active execution set 3. cache line conict in a direct mapped cache.

Causes of Cache Misses

CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 161

Overow pages Frames Swap Area Retrieval

Main Memor y

of pages

Disk

Vir tual memor y scheme for main memory overow


User Code Page# Offset logical addr Page Table
31 0

Page Table Register User Data

31

Memor y

Frame# Offset physical addr

Vir tual memory logical page into physical frame address translation

CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 162

CPU
vir tual address

CPU SRAM Cache MMU


physical address

MMU
physical address

SRAM Cache System Bus

vir tual address

System Bus

DRAM Main Memory

I/O Subsystem

DRAM Main Memory

I/O Subsystem

Physical addressing cache (Pentium)

Vir tual addressing cache (ARM)

Alternative positions for the memory management unit


FFFF FFFF FFF FFFF

4 Gbyte Code Segment

Data Segment SS Base

Stack Segment

Data Segment Stack Segment DS Base Code Segment Logical Addressing Programmers View page CS Base Vir tual Addressing O/S View
0000 0000

frame
000 0000

Physical Addressing Hardware View

The relation between different address designations

CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 163

Read/write head Flying height 0.5m Human Hair about 50m

100km/hr

Smoke Par ticle 5 m

Finger print Smear 3m

Oxide Layer 2.5m

Environmental obstacles with R/W disk heads

Voice Coil actuator

Data sectors along a track

Read/write head

Schematic Diagram of Hard Disk Unit


drive_capacity = no_of_surfaces x no_of_tracks x no_of_sectors x size_of_sector

CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 164

A computer system having 2 Mbytes of RAM has hard disks with the following characteristics: Rotational speed: 3600 rpm Track capacity: 16384 bytes Heads/cylinder : 10 Head movement time, track to track:20 ms Average seek time: 50 ms How long does it take to dump memory onto disk? Assume the disk is empty. 3600rpm = 60 rps rotational period = 1/60 secs = 1000/60 msec = 16.66 msec = 17 msec latency = 8.5 msec data rate = 16 Kbytes / 17 msec = 1 Mbyte/sec ow time for 2 Mbyte = 2000 msec = 2 sec 2 Mbyte needs 128 tracks or 12.8 cylinders ie 13 head movements tot time = head movement (seeks) + rotnl delays (latencies) + data ow time = 1 x 50 + 12 X 20 + 13 X 8.5 + 2000 = 2314 msec

Estimating Hard Disk Data Retrieval Time


Disk Performance Specication Track to Track Seek Average Seek Maximum Seek Average Latency Rotation Controller overhead Star t time Computer interface rate Media read/write rate Sectors per track Cylinders (tracks per surface) Bytes per sector Data zones per surface Integrated buffer size Memor y type 1 ms < 9 ms 20 ms 5.77 ms 5400 rpm < 0.3 ms 7.3 sec < 66.7 Mbytes/sec < 27.8 Mbytes/sec 266 - 462 17549 512 16 2 Mbytes SDRAM

Model Capacity (Gbytes) Heads Disks

90650U2 6.5 2 1

90845U 8.45 3 2

91020U3 10.21 3 2

91360U4 13.61 4 2

92040U6 20.42 6 3

92040U8 27.23 8 4

A Specication Table for Maxtor Hard Disks


CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 165

Queue 97 179 35 80 12 190 50 51 121 122

200 180 160 140 Track 120 Number100 80 60 40 20

SCAN

FCFS

SSTF Time

Disk Access Scheduling Techniques


81 Average inter-track seek distances

34 29

FCFS

SSTF

SCAN

Comparison of Disk Scheduling Techniques


........................................ .......... .............................. .. ........... ............................................................................. ... .... . .... .... ..... ....... ............................................... ...... ..... ............................................................................................... . .. .. .. .... .... ....................... ..... ... ... .. . . . . . . .... .. ..... . . . .. . . .. ... ... .... .............................................................. ..... .... ... .... .. . ... .... ............... .... .. .. .. .. .. . . . . . .. . . .. .. .. .. .. ... ... . .. .. . . . . . . .. .. .. .. .. .... .................. ... .. .. . . . . . . . . . . . . . . . . . . . . . ..... ... .. . . . . . . . . . ... . . . . . . . . . . . . . . . . . ..... . . . . . . . . . .. . . . . . . . .. ... .... .. . . . . . . . . . . . . . .. .. ............. . . .. .. . . .. . . . . . . .. . .. .. . . . .. . .. ... .. . . . . .. .. ..... .......... .... ... .. .. .. . . . . .. .. .. .... .... .... ..... ......... ......... ......... ..... .... .. .. . . .. .. . . . .. ................. .. . . . . ... ... .... ..... ...... ............. ............ ..... ..... .. ... ... ... .... .... ...... ............ ............ ............ ...... ..... .... .... .... ..... ...... ......... ..................... ....... ..... ... ... .... ...... ......... ............................... ........ ..... .... ...... ....... .......................................... ........ ..... ........ ............. .. . .......... .............................................. .....................................

CD data Spiral and Magnetic Disk Concentric Tracks


CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 166

bit pit (0.12m)

lacquer coating (30m) metalic layer rotating (1000r pm) Polycarbonate disk (1.2mm)

beam splitter

light detector

Laser emitter tracking

focusing

Optical disk read head

Paper Label 1.6 m Lacquer Reective coating Upper dielectric Recording layer Lower dielectric

1.2 mm

Track grooves

Polycarbonate Disk

Hard Coating Laser beam

CD-RW disk structure

CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 167

Discrete Cosine Transform (DCT) base functions as used with MPEG image compression

CSA Rob Williams Pearson Education (c) 2006

CSA ch 12 - p 168

CSA Ch 13
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 13 - p 169

13. CSA - Programmers Viewpoint


Application User Systems Admin HLL Programmer Systems Programmer H/W Engineer

Different jobs, different viewpoints

the switch is closed can the valve open

FABWrite(num, B_8255); printf("switch move EAX, 04H lea EBX,string call pr

92 E6 EA 0F C2 66 3F A1 92 E6 EA 0F C2 1001 0010 1110 0110 1110 1010 0000 1111

.. .. .. . .. .. .. .. .. .. . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. . .. .. .. . .. .. .. . .. . . . . . . . ... ... ....... .... ... .... .... ... ....... .... ... .... .... .... ....... .... .... .... .... .... ... .... ... ...... ... .... ...... .... ... .... .. . .. .... .. .. .. . .. .. .... .. .. .. . .. .. .... .. .. .. .. .. . .. .. .. .... . .. .. .... .. .. .. . . . .. . . . . . .. . . . . . .. . . . . . . . . .. . . .. . . . .... . ... . . . . . ... ... . . . ... . . . . . ... ... . . . . . . . . . . ... . . ... ... . . . . . ... . . . . . . . . . . . . . ... ... .... .. .. .. .. .... .. .. .. .. .. .... .. .. .. .. .. .. .. .... .. .. .. .... .. .. .. .. .. .. .... .. .. ... .. .... .. .. ... .. .. .... ... ... ... ... .. .. .. .... .. ... .. ..... ... .. ... .. .. .. .. . . . . .. . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. .. . . .. .. .. .. .. .. .. . . .. .. ..

Same device, many different viewpoints

CSA Rob Williams Pearson Education (c) 2006

CSA ch 13 - p 170

Graphical representation of a directory designed for application users

rob@milly [80] total 6702 drwx--x--x 76 drwx--x--x 3 -rwx-----1 -rwx-----1 -rwx-----1 -rwx-----1 -rwx-----1 -rwx-----1 -rwx-----1 -rwx-----1 rob@milly [81]

ls -alt rob rob rob rob rob rob rob rob rob rob csstaff csstaff csstaff csstaff csstaff csstaff csstaff csstaff csstaff csstaff 7168 3072 42544 42545 9503 9525 5144 17851 17890 21180 Aug Aug Aug Aug Aug Aug Aug Aug Aug Aug 7 7 6 5 5 5 3 3 3 2 17:57 15:55 14:57 14:55 14:35 14:31 14:31 14:31 14:30 17:28 .. . #testparam.c# sort.c jeffsm.c jeffsm.c a.out ch_9c.txt ch_9c.asc ntime.c

Traditional text-only Unix directory listing using ls


CSA Rob Williams Pearson Education (c) 2006

CSA ch 13 - p 171

Chapt 7

cat

eqn

pic

troff

lpr

Printer

Header cat header ch_13c|geqn|gpic|groff -fH|lp -dps -oduplex

A Unix process pipeline to format and print text used by systems administrators

rob@milly rob@milly rob@milly rob@milly prw------prw------prw-------

[80] [80] [80] [81]

/etc/mknod pipe1 p /etc/mknod pipe2 p /etc/mknod pipe3 p ls -al pipe*

1 rob csstaff 0 Oct 14 18:39 pipe1 1 rob csstaff 0 Oct 14 18:39 pipe2 1 rob csstaff 0 Oct 14 18:39 pipe3

rob@milly [82] cat letter.tmp >! pipe1 & rob@milly [82] cat pipe1 >! pipe2 & rob@milly [82] cat pipe2 >! pipe3 &

Demonstrating Unix named pipes

CSA Rob Williams Pearson Education (c) 2006

CSA ch 13 - p 172

#!/bin/sh # # Script converts sar data into graphs - PJN 20/10/1998 # # Extend the PATH to include gnuplot PATH=${PATH}:/usr/local/bin ; export PATH # Procedure to remove non-data lines from log file. remclutter() { grep : |grep -v free |grep -v % |grep -v / |grep -v restarts } # Procedure to pad numbers with zeroes to 2 digits. padnum() { NUM=$1 while [ `/bin/echo "${NUM}\c" | wc -c` -lt 2 ]; do NUM="0${NUM}" done echo $NUM } # Procedure to convert time of day timestamps to decimal days. parsetimes() { DAY=0 OLDHOUR=23 while read TIME DATA; do if [ "$DATA" = "" ]; then DATA="0 0 0 0 0 0 0 0 0 0 0 0" fi HOUR=`echo $TIME | cut -f1 -d:` MIN=`echo $TIME | cut -f2 -d:` if [ $HOUR -lt $OLDHOUR -a "$MIN" = "00" ]; then DAY=`expr $DAY + 1` fi PTIME=`expr \( \( \( $HOUR \* 60 \) + $MIN \) \* 100 \)/1440` PTIME=${DAY}.`padnum $PTIME` echo "$PTIME $DATA" OLDHOUR=$HOUR done } # Procedure to get data from a named column. getcol() { tr -s | cut -f1,${1} -d\ | tr }

Continues

CSA Rob Williams Pearson Education (c) 2006

CSA ch 13 - p 173

# Determine the i/p and o/p files (for last weeks data). WEEK=`date +%W` WEEK=`expr $WEEK - 1` if [ $WEEK -eq -1 ]; then WEEK=52 fi WEEK=`padnum $WEEK` DATAFILE=/var/adm/sa/sa$WEEK OUTFILE=/tmp/$$.graphs # Process virtual memory data from sar log. echo "VM usage" sar -f $DATAFILE -r > /tmp/$$.sar cat /tmp/$$.sar | remclutter | parsetimes > /tmp/$$.sar-f rm /tmp/$$.sar cat /tmp/$$.sar-f | getcol 2 > /tmp/$$.freemem cat /tmp/$$.sar-f | getcol 3 > /tmp/$$.freeswap (cat << EOF set term postscript set time set xtic 0,0.5 set title "`hostname` virtual memory usage" f(x) = (x * 512 ) / 1048576 g(x) = (x * `pagesize` ) / 1048576 plot [0:7] []\ "/tmp/$$.freemem" thru g(x) title "Free RAM MB" with lines,\ "/tmp/$$.freeswap" thru f(x) title "Free Swap MB" with lines EOF ) | gnuplot > $OUTFILE rm /tmp/$$.freemem /tmp/$$.freeswap /tmp/$$.sar-f lp -d ps $OUTFILE sleep 60; rm $OUTFILE exit

A Unix administration script for performance statistics

CSA Rob Williams Pearson Education (c) 2006

CSA ch 13 - p 174

#include <stdio.h> int bsort(char* pc[ ], int n ) { int gap, i, j; char* pctemp; for (gap = n/2; gap > 0; gap /= 2) for (i = gap; i < n; i++) for(j = i-gap; j>= 0; j -= gap) { if (strcmp(pc[j], pc[j+gap]) <= 0) break; pctemp = pc[j]; pc[j] = pc[j+gap]; pc[j+gap] = pctemp; } } void main(void) { int i; char* names[ ] = { "Monday", "Tuesday", "Wednesday", "Thursday", "Friday", "Saturday","Sunday"}; i = bsort(names, 7); for(i=0; i<7; i++) { printf("%s0, names[i] ); }; }

Example HLL algorithm - Bubble Sor t for the software engineer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 13 - p 175

SEQ
void doitall(void) { doA( ); doB( ); doC( ); }

do A

do B

do C

IT

for( i=0; i<10; i++ ) { doD( ); }

do D

* 10

x = 0; while (x < 10) { doD( ); x++; }

SEL
X>0

do F

do E

if (x > 0) { doE( ); } else { doF( ); }

Structure Char t representations of SEQ, IT & SEL


BOOL char WCHAR BYTE shor t WORD int LONG unsigned DWORD oat double unsigned 1 bit value unsigned 8 bit value unsigned 16 bit value unsigned 8 bit integer signed 16 bit integer unsigned 16 bit integer signed 32 bit integer signed 32 bit integer unsigned 32bit integer unsigned 32 bit integer IEEE 32 bit real IEEE 64 bit real

Data types for C/C++, popular languages with systems programmers

CSA Rob Williams Pearson Education (c) 2006

CSA ch 13 - p 176

SEQ

do A do B do C
L1: CALL doA CALL doB CALL doC --------------------------JZ L2 .... CALL doD JMP L1

IT

? n do D

L2: --------------MOV CX,10 L3: .... CALL doD LOOP L3 ---------------------------

SEL

y do E

n do F

CMP EAX,12 JGE L4 CALL doE JMP L5 L4 L5 CALL doF

Flow Char t representation of SEQ, IT & SEL

CSA Rob Williams Pearson Education (c) 2006

CSA ch 13 - p 177

Circuit schematic diagram for the electronic engineer


User Program

HLL Librar y Routines

Operating System Procedures

Microcode Interpreter

Co-processor Units

Digital Logic Circuits

Electronic Devices

A multi-level computer functional interaction

CSA Rob Williams Pearson Education (c) 2006

CSA ch 13 - p 178

1. instruction mnemonics into binary codes 2. user dened symbols into constant numbers 3. numbers from base to base, normally decimal to binary 4. symbolic position labels into physical addresses

Translation activities of an assembler

Symbol ADD ADDA SUB MOVE

Type opcode opcode opcode opcode

Value $FF

star t exit loop1 spx sprite

dened unden dened dened dened

Symbol Table Entries

CSA Rob Williams Pearson Education (c) 2006

CSA ch 13 - p 179

Source le

Preprocessor Error repor t Source le Lexical analysis Error repor t Token list

Symbol table

Syntactic analysis Error repor t

Intermediate code

Code Gen

Machine code

Stages of Compilation
Code Optim

Better Machine code

CSA Rob Williams Pearson Education (c) 2006

CSA ch 13 - p 180

CSA Ch 14
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 181

14. CSA - Local Area Networks


IBM
Cold Water Front-end processor

DEC

Mainframe computer

Mini computer

Personal computer

Local Area Network

Evolution of computing provision

email

le transfer using ftp

CSA Rob Williams Pearson Education (c) 2006

Displaying LAN trafc using Suns perfmeter

CSA ch 14 - p 182

802.3 802.4 802.5 802.6 802.11 802.12

CSMA/CD Token Bus Token Ring MAN Wireless LAN 100 Mbps LAN

Some of the IEEE 802 standards committees


Ser ver
Packet signal

70 Terminator

////////

\\\\\\\\

70 Terminator

10Mbps Ethernet

Workstations

Traditional ofce bus LAN facility


Ser ver workstation Switching Hub

Star topology, switched hub, ethernet


Central Hub

Switching Hub

Switching Hub

workstations

Star topology with hierarchical hubs


CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 183

Cat 5 twisted pair cable


12345678

1 2 3 6 4 5 7 8

Connections to an RJ45 LAN Plug

RJ45 socket 10BaseT

UltraChip

SMC

10Base5 socket BNC 10Base2 socket

Thin Ethernet 10Base2 cable

BNC Tee piece connector 70 stub terminator

A network interface card with 10Base2 & 10BaseT connectors

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 184

Application TCP/IP Device Driver Network Controller Serial Network interface Software

Hardware

H/w and s/w layers to manage the LAN Interface

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 185

20MHz Clock

Data

1 XOR

Data Out 10Mbps

+0.7v

-0.7v

Manchester Encoding for Data and Clock


rising edge - 0, dropping edge - 1

10101010 10101010 10101010 101010100 101010100 101010100 10101010 Flag Bytes

10101010 10101010 10101010 10101010 10101011 [Ethernet_packet_body....]

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 186

10Base5

10Base2

10BaseT

100BaseT

100BaseF

10Mbps, 500m segment length, minimum tap separation 2.5m, maximum of 4 repeaters, 50 coax cable vampire tap (Media Access Unit) 10 Mbps, 200m (165m) segment length, minimum tap separation 0.5m, maximum of 4 repeaters, 70 coax cable BNC T-piece bayonet connection 10 Mbps, 100m segment length, end-to-end, simplex 100 AWG24 twisted pairs cable RJ45 telecom jack 100 Mbps, 205m segment length, end-to-end, simplex 100 AWG24 twisted pairs cable 100 Mbps 2000m segment length end-to-end, simplex optic bres

Thick Ethernet

Thin Ethernet

Switched Ethernet

Fibre Ethernet

Various ethernet media standards

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 187

T packet =

500 x 5 x 2 = 50 s 1 x 108 50 = 500 bits 0. 1 500 = 62. 5 ~ = 64 Bytes 8 Transit Time


Star t End

t bit = 0. 1 s N packet = N Bytes =

S2

LAN Length metres

Received Collision

Collision warning

S1

Transmitted
Star t End

Time, sec

Collision Detection and Transit Times for Ethernet

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 188

Binar y 0000_0000 0000_0001 0000_0010 0000_0011 0000_0100 0000_0101 0000_0110 0000_0111 0000_1000 0000_1001 0000_1010 0000_1011 0000_1100 0000_1101 0000_1110 0000_1111 .... 1111_1111

Trinar y +-00+-T 0+-+-+T +-0+-0T -0++-0T -0+0+-T 0+--0+T +-0-0+T -0+-0+T -+00+-T 0-++-0T -+0+-0T +0-+-0T +0-0+-T 0-+-0+T -+0-0+T +0--0+T ... +0-+00T

8B6T Coding

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 189

15

Sync Preamble (56 bits) SFD Destination Address (48 bits) Source Address (48 bits) Length of Data Field Data 0-1500 Padding 0-46 CRC error detection

Internal Structure of an Ethernet Data Packet

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 190

31 Class A 0 Network Class B 1 0 Class C 1 1 0 Class D 1 1 1 0 Class E 1 1 1 1

23 Subnet 15 Network Subnet 7 Network Host Host Host

1000 127255255255 128000 191255255255 192000 223255255255 224000 239255255255 240000 247255255255 127000

Multicast Address Reser ved

Local 0 1 1 1 1 1 1 1 loopback

The 5 Forms of IP v4 numbers and their ranges


rob@milly [20]/usr/sbin/arp -a Net to Media Table Device IP Addr Mask Flags Phys Addr ---------------------------------------------------hme0 lentil 255.255.255.255 00:00:8e:06:07:cf hme1 pb4 255.255.255.255 00:80:5f:cc:5c:20 hme0 rice 255.255.255.255 00:00:8e:06:07:e9 hme0 beans 255.255.255.255 00:00:8e:06:07:c4 hme1 ivor 255.255.255.255 08:00:20:1a:9d:16 hme0 carrot 255.255.255.255 00:00:8e:06:07:e6 hme1 router8 255.255.255.255 08:00:20:19:1c:9a hme0 hops 255.255.255.255 00:00:8e:06:07:e3 rob@milly [21]

ARP table, translating IP addresses into MAC numbers

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 191

rob@olveston [20]cat /etc/hosts # Internet host table # 127.0.0.1 localhost 164.11.10.206 olveston 164.11.8.16 egg ns0 164.11.253.2 sister ns1 164.11.8.99 ada ns2 164.11.10.5 riff ns3 rob@olveston [21]

loghost

Host table, translating acronym into IP addresses


user data Appln

Appln header

user data

TCP

TCP header

Appln data

IP

IP header

TCP header

Appln data

Ether driver

Ether header

IP header

TCP header

Appln data

Ether trailer

Ethernet

A Layered description of networking software

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 192

rob@olveston [20]df / (/dev/dsk/c0t0d0s0 ): /usr /proc /dev/fd /var /tmp /cache /local /usr/misc /tutorials /home/staff/cs /var/mail /projects/staff /projects/rob /WWW/Documents /WWW/Servlets rob@olveston [21] (/dev/dsk/c0t0d0s3 ): (/proc (fd ): ):

751760 blocks 292766 blocks 0 blocks 0 blocks 264238 blocks 165454 blocks

216981 files 177111 files 915 files 0 files 97421 files 100191 files 48381 files 1264846 files 273054 files

(/dev/dsk/c0t0d0s4 ): (/dev/dsk/c0t0d0s5 ):

(/dev/dsk/c0t0d0s6 ): 53882 blocks (/dev/dsk/c0t0d0s7 ): 4730618 blocks (thalia:/usr/misc ): 938032 blocks

(milly:/tutorials ): 282752 blocks 93369 files (sister:/home/staff/csm/csstaff): 4942096 blocks 513071 (mailhub:/var/spool/mail): 3582944 blocks (ada:/projects/staff): 1408240 blocks (ada:/projects/rob ): 218704 blocks 974994 files 729518 files 95166 files

(www:/var/htdocs ): 2032720 blocks 582750 files (www:/opt/local/JSDK/servlets): 3539408 blocks 344000 files

remote hosts

local disk drive

Inspecting the state of a Unix le systems using df

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 193

Other computers on the network

Next available vir tual drive letter

Installing a virtual drive using Windows XP


Ser ver

LAN 1

Gateway Workstations LAN 2

Interconnecting LANs using a gateway


CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 194

Linux

Windows-XP

socket to socket communication

Socket communication between remote processes

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 195

Ser ver
socket( ) create a socket

Client

socket( ) create a socket

bind( ) name the socket connect( ) connect to server

listen( ) specify queue

accept( ) wait for call accept connection spawn new socket

send( )/recv( ) transfer data

send( )/recv( ) transfer data

closesocket( ) close socket

closesocket( ) close socket

Communication with Client-Server connection-based (STREAM) sockets

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 196

SOCKET socket(int af, int typesock, int protocol) int bind(SOCKET mysock, const struct sockaddr "psock, int nlength) int listen(SOCKET mysock, int qmax) int connect(SOCKET yoursock, const struct sockaddr *sname, int nlength) SOCKET accept(SOCKET mysock, struct sockaddr *psock, int *addrlen) int send(SOCKET yoursock, const char *pdbuff, int dblen, int flags) int recv(SOCKET mysock, char *pdbuff, int dblen) int closesocket(SOCKET mysock)

Win32 Socket Function Calls

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 197

Ser ver
socket( ) create a socket

Client
socket( ) create a socket

bind( ) name the socket

bind( ) name the server

recvfrom( ) waiting accept data

sendto( ) transfer data

sendto( ) return data

recvfrom( ) waiting accept data

closesocket( ) close socket

closesocket( ) close socket

Communication with Client - Server connection-less (DGRAM) sockets

CSA Rob Williams Pearson Education (c) 2006

CSA ch 14 - p 198

CSA Ch 15
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 199

15. CSA - Wide Area Networks

LAN

5 1 6 WAN WAN

LAN

LAN

WANs give long distance interconnection for LANs

TCP/IP - are the essential protocols for the Internet

CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 200

biff
517

talk
512

telnet ftp
23 20/21

smtp
25

http
80

Hosts Table (cat /etc/hosts) user

UDP

TCP

por t

Port map (cat /etc/services) ICMP

02

06

IP 0800

17 protocol payload type

Routing Table /usr/sbin/netstat -rn

ARP 0806

Ether Driver

ARP Table (/usr/sbin/arp -a)

Network Interface

The TCP/IP Stack at Work


Number 02 06 17 Protocol ICMP TCP UDP

IP Protocol Field Values


CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 201

> cat /etc/services tcpmux 1/tcp echo 7/tcp echo 7/udp discard 9/tcp discard 9/udp systat 11/tcp ftp-data 20/tcp ftp 21/tcp telnet 23/tcp smtp 25/tcp time 37/udp name 42/udp whois 43/tcp gopher 70/tcp finger 79/tcp www 80/tcp www 80/udp hostnames 101/tcp sunrpc 111/udp sunrpc 111/tcp

sink null sink null users

mail timserver nameserver nicname # usually to sri-nic #Internet Gopher http hostname rpcbind rpcbind # World Wide Web # usually to sri-nic

TCP port numbers and their services from /etc/services

CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 202

15

0 15 7 0

15

Sync Preamble SFD Destination Address (48 bits) Source Address (48 bits) Length of Data Field

Source port Destination Por t Transmitted Sequence number Acknowledged Sequence number
Header length

Header Version length

TOS

Length (Bytes) Sequence count (Identity)


Flags

TTL max hops Protocol Header checksum IP Source address (32 bits) IP Destination address (32 bits)

Flags

Tx window size TCP checksum Urgent pointer Optional facilities

Payload Type

TCP Frame (Data Payload)

User Payload

IP Frame (Data Payload)

IP Header Structure

TCP Header Structure

CRC error detection

Ethernet header

IP header

TCP header User Data

Ethernet Packet

Ethernet, IP, TCP encapsulation


CSA ch 15 - p 203

CSA Rob Williams Pearson Education (c) 2006

Data packet

single data packet sent immediately ACK ACKed multiple data packets sent all ACKed

data sent no ACKs so Tx pauses

Flow control using a four packet buffer

ACKs received so Tx resumes Transmitter Receiver

Router

Network 1

Network 5

Bridge

Differentiating Repeaters, Bridges, and Routers


Network 2

Network 1

Network 1

Repeater

Network 2

CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 204

rob@olveston [20] cat /etc/hosts # Internet host table # 127.0.0.1 localhost 164.11.253.47 olveston loghost 164.11.8.16 egg ns0 164.11.253.2 sister ns1 164.11.8.99 ada ns2 164.11.10.5 riff ns3 rob@olveston [21] rob@olveston [21] netstat -rn Routing Table: Destination Gateway Flags Ref Use Interf ----------------------------------------------------127.0.0.1 127.0.0.1 UH 0 503 lo0 164.11.253.0 164.11.253.47 U 3 228 hme0 224.0.0.0 164.11.253.47 U 3 0 hme0 default 164.11.253.1 UG 0 14297 rob@olveston [22]

Destination host or network

Recommended rst hop

Status Flags U - up and OK G - gateway / direct connection H - host / network address

Local Ethernet por t

Unix netstat utility showing the routing table

CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 205

Trafc ooding without routing decisions


RIP Operation IP Number # router hops 1st hop # ticks (56ms) IP Number # router hops 2nd hop # ticks

RIP packet elds


Region Europe N America S America Pacic Asia IP Numbers Reserved 194000000000 - 195255255255 198000000000 - 199255255255 200000000000 - 201255255255 202000000000 - 203255255255

CIDR IP number allocations


address book DNS arp table

User name Rober t Williams UWE, Bristol, UK

user host id rob.williams olveston.uwe.ac.uk

IP number 164.11.253.47

MAC number 08:00:20:8E:86:5F

Identier translation required for transmitters

CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 206

rob@milly [10] ypcat hosts | more 164.11.13.5 gecko 164.11.9.89 TT89 164.11.235.52 saar 164.11.243.225 valdoonican 164.11.10.56 StaffPC56 164.11.11.73 blackwell 164.11.253.47 olveston 164.11.8.203 dialin63 164.11.8.200 dialin60 164.11.13.15 wallaby 164.11.235.87 shannon 164.11.253.158 new_pb2 164.11.243.249 naqqara 164.11.194.4 linux04 164.11.10.45 drjones 164.11.11.71 wesley 164.11.235.122 siphon --more--

Inspecting the local hosts le

org

net

com

edu

gov

mil

fr

de

uk

us

gov

ac

co

uwe

csm

Hierarchical Domain Naming Structure (DNS)


CSA ch 15 - p 207

CSA Rob Williams Pearson Education (c) 2006

rob@milly [33] cat /etc/resolv.conf domain csm.uwe.ac.uk search csm.uwe.ac.uk uwe.ac.uk nameserver 164.11.8.16 nameserver 164.11.253.2 nameserver 164.11.253.11 nameserver 164.11.8.99 rob@milly [34] /usr/sbin/nslookup Default Server: egg.csm.uwe.ac.uk Address: 164.11.8.16 > smilodon.cs.wisc.edu Server: egg.csm.uwe.ac.uk Address: 164.11.8.16 Non-authoritative answer: Name: smilodon.cs.wisc.edu Address: 128.105.11.80 > D rob@milly [35]

Using the DNS name look-up facility

CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 208

Netscape Navigator Web Browser


URL = Protocol identifier/Machine name/file path

CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 209

Introducing world.html to Netscape on Unix


Tags <HTML>. . . </HTML> <HEAD>. . . </HEAD> <TITLE>. . .</TITLE> <BODY> . . .</BODY> <BASEFONT FACE = "Helvetica" SIZE = 12> <FONT SIZE = +2>. .</FONT> <Hx> . . . </Hx> <B> . . . </B> <I> . . . </I> <UL> . . . </UL> <OL> . . . </OL> <MENU> . . .</MENU> <LI> <BR> <P> <HR> <PRE> . . .</PRE> <IMG SRC = ". . . "> <A HREF = "http://www.." > [Press] </A> Functions Page delimiters Page heading http title (invis) Main text delimiters Body text font selection Font type, size & colour Subheading at level x Embolden font Italicize font Unordered list Ordered list Menu List star t Break text, \n New paragraph Horizontal line Noll, preformatted Inser t image le here set up a Hyperlink

Star ter set of HTML tags


CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 210

http proxy [URL] - The proxy command allows a proxy HTTP server to be dened which will be used in subsequent client commands. Providing a URL argument sets the proxy server. Setting the proxy to an empty string turns the proxy feature off. http head url - The head command retrieves the HTTP header for the document located at URL. http get url le - The get command retrieves the document located at URL. The body of the document is written to le. The command returns the HTTP header as described for the http head command above. http post url lename_1 lename_2 - The post command posts the document in lename_1 to the location URL. The body of the returned document is written to lename_2. The command returns the HTTP header as described for the http head command above. http put URL le - The put command copies the le into the URL. The command returns the HTTP header as described for the http head command above. http delete URL - The delete command deletes the document at the URL. The command returns HTTP status information. The %X variables are substituted before a script is evaluated: %A - The network address of the client. %P - The URL path requested by the requestor. %S - The search path contained in the URL path.

Examples from Hypertext Transmission Protocol (http)

CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 211

rob@olveston [50] telnet www.altavista.com 80 Trying 204.152.190.69... Connected to altavista.com. Escape character is ]. GET / - - <img src="/av2/gifs/dart.gif" width=8 height=9 hspace=5 vspace=5 align=top><a <img src="/av2/gifs/dart.gif" width=8 height=9 hspace=5 vspace=5 align=top><a </font></td></tr></table> <br> <table width="100%" cellpadding=0 cellspacing=0 border=0><tr> <td align=center><font size=-2 face="arial,helvetica" color="#003399"> <a href="/av/content/about.htm">About AltaVista</a> | <a href="/av/content/help.htm">Help</a> | <a href="/av/content/questions.htm">Feedback</a> | <a href="http://www.doubleclick.net/advertisers/altavista/">Advertising Info</a> | <a href="/cgi-bin/query?pg=addurl">Add a Page</a><br> <a href="/av/content/disclaimer.htm">Disclaimer</a> | <a href="/av/content/privacy.htm">Privacy</a> | <a href="http://image.altavista.com/AV_CopyrightPolicy.htm">Copyright</a> | <a href="/av/content/av_network.html">International</a> | <a href="/cgi-bin/query?pg=tmpl&v=pref.html">Set your Preferences</a> </font></td></tr></table> </body></html> Connection closed by foreign host.

Attaching to a web server by telnet for an on-line session

rob@localhost> telnet www.cems.uwe.ac.uk 80 Trying 164.11.8.19... Connected to www.cems.uwe.ac.uk (164.11.8.19). Escape character is ]. GET /rwilliam/http_spook Hello, and welcome to the target file in this telnet/http file GET exercise. Connection closed by foreign host. rob@localhost>

Using http/GET in place of ftp/get


CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 212

DNS server

Multiple Google ser vers Client broswer

Index ser vers each with 80 dual Pentium cards with 2 GB DRAM & 80 GB IDE disks in cooled racking

Schematic of Google search engine

CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 213

Internet Fetched pages Crawlers

Internet Queries Parser

URL ser ver Anchors

Repositor y of web pages (compressed by zlib) Lexicon Indexer wordID converter Word index store inverted le Index sor ter

Document index store URL resolver Links Searchers hits PageRank Filter and sor ter

Quer y allocate

results list

Google data-ow activity diagram

CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 214

Application layer

Application program

Presentation layer

transformation data formatting

Session layer

computer dialogue control

Transpor t layer

message <=> packets

Network layer

Vir tual circuit routing control packet sequencing Flow control error/lost block detection

Link layer

Physical layer
Communication sub-net layers

Voltage levels plug pinouts

ISO Seven Layer OSI Model


Application Application Presention Session TCP or UDP IP Network Transpor t Network Link Physical
7 6 5 4 3 2 1

Comparison of TCP/IP with ISO seven layers


CSA Rob Williams Pearson Education (c) 2006

CSA ch 15 - p 215

CSA Ch 16
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 16 - p 216

16. CSA - Other Networks


IXC

IXC

Trunk lines

IXC Trunk Exch

LXC

LXC Local Exch

Brr Brr! Brr Brr

POTS, the traditional telephone network


1209 1336 1477 Hz 1 4 7 2 5 8 0 3 6 9 # 697 770 825 941

DTMF, touch-tone signalling key pad


. .. . .. .. .. .. .. .. . .. .. .. . . .. .... .. . . . . . .. . . . . . . . . ..... . .... . . . . . . . ...... . . . . . . . . . . .. . . . .. . . . . .. . . .. . . . .. .. .. . . .. . . .. . . . . .. . .. .. .. . . .. .. . . .. .. . . .. .. . . .. .. .. . . .. .. . . .. .. . . . . .. .. . . . . . . . . . ... ... . .. .. .. . ... .... . . . . . . . ... ... . . . . . . . . . . .. . .. .... ..... ..... . . . . . .. . .. . . . .... . . . . . . . ... . . . . . . . ... .. . . . . .. . . . . .. .. . . . . . .. ... . . . . .. .. . . . . .. . . . . . . . .. . .. .. .. . .. .. .. . . . .. .. Analogue .. .. . . . signal 8 bits every 125 s

01100101 00111100 11100101 00111101


Digital signal

Line .............................................................................. Interface ........................................................................ Card

Digitization of telephone speech signals


CSA Rob Williams Pearson Education (c) 2006

CSA ch 16 - p 217

128 112

Output value

96 80 64 48 32 16
V V /16 /8 V /4 V /2 V V /1

V out =

A V in 1 + log A where A = 87.6

Input Speech Signal

Non-linear voice compression for transmission


2 x 106 103 2. 048M = = = 32 channels 64 x 103 32 64k
0 1 2 3

discrete voice channels

0 1 2 3 30 channel TDM trunk line Demultplx 28 29 30 31

Multiplexor 28 29 30 31

1 frame 125 s 30 conversations


C1 1 2 3 4 5 6 7 C2 24 25 26 27 28 29 30 C1 2 3 4 5 6

1 slot

10110110

8 bit speech sample, 3.9 s

Time Divison Multiplexing (TDM) for trunk line sharing


CSA Rob Williams Pearson Education (c) 2006

CSA ch 16 - p 218

nput Voice Channels

0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9

Control Computer

Signal Channel

Ouput Voice Channels

Space division circuit switching with control processor


125 s frame 1
5 8 2 0 8 4

time frame 2
5 8 2 0 8 4

frame 3
5 8 2 0 8 4

frame 4
5 8 2 0 8 4

frame 5
5 8 2 0 8 4

TDM Bus

0 1 2 3 4 5 6 7 8 9

Input Voice channels

TDM Controller

Output Voice channels

0 1 2 3 4 5 6 7 8 9

Time Division Circuit Switching

CSA Rob Williams Pearson Education (c) 2006

CSA ch 16 - p 219

300 Hz

30 KHz LF

3 MHz MF coax cable

300 MHz gsm

30 GHz

3 THz 300 THz IR Vis optic bre UV

VLF

HF VHF UHF SHF EHF

twisted pair

Bands within the electromagnetic spectrum


.. .. . . .. . . .. . . .. . . .. . . .. .. . . .. . . .. . . .. . . .. ... .... .... ... .... .... .... .... .... .... .... .... .... .... ... ... .... .... .... .... .... .... .... .... .... .... .... .... .... .... . . . . . . . . ... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... . .. . .. . . .. .. . .. . .. . . . .. . . . . . .. . .. . . . . .. .. .. . . . . .. . .. . .. . .. . . . .. . .. . . . .. . .. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ............................................................. . . . .. . . . . . . . . . . . . . . . . . . . . . .. . . . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . .. .. .. .. .. .. .. .. .. .. . .. . . . . . . . . . . .. .. .. . . . . . . .. .. .. . . .. . . . . .. .. . . .. .. . . . . .. .. .. .. . . .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . .. . . . . .. .. . . . . . . . . .. .. .. .. .. . . . . .. .. . .. .. . .. .. . .. .. . .. .. . . .. . . .. .. . .. .. . .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ... ... .. .. ... ... . .. .... ... .. . .... ... .. .. . . .. .. . .. .... .... .... ... . ... .... .... .... .. .. .. .. .. .... .... .... ... . . .. . . . . . . . .. . . ... . . . . . . . .. . . . . ... ... . . . . . . . . .. . . . . . . . . . . . .. ... .. . . . . .. . .. .. ... ... . . . . . . . . .. . . .. . .. .. . . . .. . .. ..... .... .. .. .. .. . . . . .. . . ... . . .. .. . .. . . . . . .. .. .. ..... .... .. .. .. .. . . . . .. .. .. ... . .. .. . .. . . . . . . . . . . . . . . .. .. ................ .. .. . . . . . .. . .. .. ... .............. .. .. . .. . . . . . .. .. .. .. ................ .. .. . . . . . .. . .. .. ... ............... .. .. . . .. . . . . . . . . . . . . . . .. . . .. . . . . . . . .. . . . . . . .. . . .. . . . . . . . . . .. . . . . ... .. .. . . . . . . . . .. . . . .. . . . .. . . . . . . . . . . .. . . . . . . . . . .. .. ... . .. . . . . .. ... . . . . . . ... . . . . . . . ... . . . .. . .. . . . . .. .. ... . .. . . . .. .. . . .. .. .. . . . . .. . . .. .. .. .. .. .. . . . .. ... ... .. .. . . . . . .. ... ... .. .. . ... . .. . . . . . . ... .. . . . .. ... .. .. ... . . . . .. . . . . .. . .. . . . .. .. . . . .. . . . . . ..... ... ... ... .. ... .... ... .... ... ... ... .. ... ... ... .... ... .. .. . .. . . .. .... .... .. .. .. .... .. .. .. .. .... .... .. .. .. .... .. .. .. .. .... .... .. . . . .. . . . . . . . . .. . .. . . . . . . . . .. . .. . . .. .. .. . . .. .. .. . . .. .. .. .. .. .. . . .. .. .. .. . .. .. .. .. .. .. ... .. . . . . . . . . .. . . . . .. .. . . . . . . . . . . . . .. .. . . . . . . . . . . . . .. . . .. . . . . . ... . . . .. . .. . .. . . . . . ... . . . . . .. . .. . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . .. .. . . .. . . . . . . . . . .. .. . . .. . . . . . . . . . . . . . . .. .. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . .. .. . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . . . . .. . .. . . . . . . .. . . . . . .. .. .. .. . . . . . . . . .. .. .. . . . . . . . . . . .. . . . .. . . . . . . . .. .. . .. .. . . . . . . .. . . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . . . .. . . . . . . . .. . . . .. . .. .. . . . . . . . .. . . . . . . . . . . . . . .. . Carr er requency

Amp ude Modu a ed

Frequency Modu a ed

Phase Modu a ed

1 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0

Radio wave modulation using amplitude, frequency and phase techniques

CSA Rob W ams Pearson Educa on (c) 2006

CSA ch 16 - p 220

Radio mast

Base station

Switch

Switch

Switch

Radio cell equipment and interconnection

0.1 - 0.3 GHz 0.3 - 1.0 GHz 1.0 - 2.0 GHz 2.4 - 2.5 GHz 3.4 - 3.5 GHz

VHF UHF

Terrestrial television & radio Television, GSM mobile (0.9 GHz), packet radio, pagers Navigation aids, GSM mobile (1.8 GHz) Shor t range radio control (Bluetooth) Neighbourhood antennae

Utilization of radio frequency bands

CSA Rob Williams Pearson Education (c) 2006

CSA ch 16 - p 221

7 6 1 5 4 7 6 1 5 4 6 1 5 4 3 3 7 2 5 4 2 5 4 6 1 3 6 1 3 7 2 3 7 2 5 4 6 1 3 7 2 2

Cells with a repeat 7 pattern of radio frequencies

4 2 1 3 4 2 3

A cell arrangement with only repeat 4 pattern


CSA Rob Williams Pearson Education (c) 2006

CSA ch 16 - p 222

Sound switch ADC Speech Encoder Listener Noise Speech Encoder Extra polation Speech Processing

Class 1 CRC Convl Coding Re-ordering Interleaving Ciphering Burst assem GMSK_mod

DAC

PA MXR Filter

DAC

Equalizer Burst Disass De-cipher De-interleave Decoding Class 1 CRC

ADC

LNA MXR Filter Radio Unit

Voice Codec

Sig Proc

Radio Modem

gsm handset signal processing schematic


Control Processor Protocol Stack User Interface Peripherals Control

Voice Codec ADC DAC

TDMA timer

LCD display Memory : RAM FLASH ROM Keypad

DSP Speech Encoder Radio Modem DAC ADC

Analog Baseband

PLL

Equalizer Burst Disass De-cipher De-interleave Decoding Class 1 CRC

SIM card

Radio Transceiver Unit

gsm handset functional modules

CSA Rob Williams Pearson Education (c) 2006

CSA ch 16 - p 223

0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425 120 ms TCh Multiframe 0 1 2 3 4 5 6 7 4.616 ms TDM frame T 3 Voice 57 C 1 TS 26 C 1 Voice 57 T Gd 577 s time slot 3 8.25bits

Packet structure for gsm voice transmissions


Circuit Switching Circuit Set up Path Arranged Packets Sent Vir tual Circuit Switching Datagram Packet Switching

Voice data

Packets Transfer

Circuit Closed

Message Complete

Switch: 1

Path Closed

Circuit switched vs. packet switched message timing

CSA Rob Williams Pearson Education (c) 2006

CSA ch 16 - p 224

Header 5 bytes

Payload 48 bytes

VPI VCI ECC

The ATM frame structure


0 1 2 3 ATM Switch 28 29 30 31 0 1 2 3 155 Mbps ATM trunk line 28 29 30 31 ATM Switch

Schematic ATM router switch


data payload 10101000111000 ATM data cell 0 1 155 Mbps 2 3 addr 111 111
0 1

111
0 1

111
0 1

0 4 155 Mbps 1 5

0 1

0 1

0 1

4 5

0 1

0 1

0 1

2 6

6 7

0 1

0 1

0 1

3 7

Interconnection inside an ATM Banynan Switch

CSA Rob Williams Pearson Education (c) 2006

CSA ch 16 - p 225

ATM switch

LAN

ATM switch ATM 155 Mbps Trunk Line ATM switch Ser ver ATM switch

ATM WAN linking together diverse LANs to form par t of the Internet

1010101010 Synchronization 1.125 sec

8 frames Batch 1.0625 sec Next Batch

A/C

address

func

CRC

Digital Paging word format

CSA Rob Williams Pearson Education (c) 2006

CSA ch 16 - p 226

P
12 : 01
Enter car number rst Tariff 1hr 40p Sun free Sat free

Press for ticket

Coins

Application of packet radio data messaging


customer premises Digital phone

U
ISDN i/f card Domestic Control maximum 8 devices

NT1 Network terminator

ISDN Local Exchange

Narrow Band ISDN dened interfaces


Transmission Frame 48 bits in 250 secs D D D D

B chan-1

B chan-2

B chan-1

B chan-2

2B-1D Narrowband ISDN protocol timing

CSA Rob Williams Pearson Education (c) 2006

CSA ch 16 - p 227

1 Data

4B3T, Europe 0001 1011 0101 1010 2B1Q, USA 00 01 10 11 01 01 10

Multi-level baseband encoding


Binar y data 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 3-level codes +0-+0 0-+ +-0 ++0 0++ +0+ +++ ++-++ +-+ +00 0+0 00+ 0+-0+

--0 0--0----+ +--+-00 0-0 00-

Three-level 4B3T encoding table

CSA Rob Williams Pearson Education (c) 2006

CSA ch 16 - p 228

Local Exchange Ofce PTT Local Exchage Voice Splitter ATM Switch DSL Modem Data Subscriber line 2.5 Km

Subscriber premises

Voice Splitter Data DSL Modem

Digital Subscriber Line conguration

Guard bands .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
04

Voice band

25

..... . .. .. . .. . . . . . .. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .Data. . . . . . . . . . . up-link . . . . . . . . .band .. . . . . . . . . . . . . . . . . . . . . . . .

160 240

.... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data down-link . . . . . . . . . . . . band . . . . . . . . . . . . . . . . . . . . . . . . . . .

Amplitude

Frequency (kHz)

780

Subscriber line bandwidth allocation for ADSL

CSA Rob Williams Pearson Education (c) 2006

CSA ch 16 - p 229

15 Km Satellite receiver Kerb side Node Kerb side Node Optic Fibre Video Voice & data Kerb side Node

500 m

PSTN Trunk lines

Local Telephone Exchange

Headend

Set-top box Coax / Twisted Pair Twin cable

Cable TV and telephone distribution scheme


5 40 54

MHz 59 Analogue TV Channels

575 600

750

Digital Outward

Digital Inward

Telephones

Bandwidth allocation for a cable TV network

CSA Rob Williams Pearson Education (c) 2006

CSA ch 16 - p 230

CSA Ch 17
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 231

17. CSA - Introduction to Operating Systems, Unix


IBM
Ser ver

On-line

Batch Processing

Real-time
aw k ep gr

Types of computer operating systems

sed CSA ch 17 - p 232

CSA Rob Williams Pearson Education (c) 2006

BIOS boot h/w check

Primary Bootstrap from disk

Secondar y Bootstrap

Unix kernel loaded

init runs single user

Multi-user mode star ts

getty processes star ted

login runs on demand

Interactive user shell

Unix boot sequence

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 233

Tool awk cat diff echo nd grep lpr ls more ps sed sor t spell tr troff uniq users wc who

Function text processing language opens and concatenates les le comparison repeats argument to stdout le search utility string (reg expr) search print demon directory listing text viewer process listing stream editor string sor ter spell checker transpose strings text formatter repeated line detector network users list le sizer local user list

Example cat le | awk $0 ! /$/ {print} cat header ch_01 | groff -petfH > /tmp/tmp.ps diff ch_01.a ch_01.b echo $PATH nd -name "*rob*" -print grep "rob" /etc/passwd lpr -Pnts -#25 /Sheets/unix_intro ls -al more book.txt ps -af sed s/r-williams/rob.williams/g <le1 >le2 cat le | sort +1 -2 spell letter.txt tr -cs A-Za-z \012 groff -petfH sor t | uniq -c | sort -n users > checkle wc -w assignment.txt who

Some Unix tools

Tools API File manager Device drivers

Applications GUI or Shell Scheduler Task dispatcher

Graphic primitives Memor y allocation

Computer hardware

Typical operating system layered structure

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 234

PID - process id UID - owner Process State Semaphore ID Signal ID Memor y needs CODE SEG pointer STACK SEG pointer DATA SEG pointer Priority Accounting information File descriptors Current director y Task Queue pointers

Summary contents of a TCB

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 235

Task 1 Control Block Task stack area Task 2 Control Block Task stack area Task 4 Control Block Task stack area Task code Task code Task code

Task 3 Control Block Task stack area

Tasks specied by their control blocks

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 236

TCB 1 Task stack area Task code

TCB 2 Task stack area Task code

TCB 3 Task stack area Task code

TCB 4 Task stack area Task code

Task Control Block queue

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 237

data ready Timed out Process Forked Exit

Ready

Executing

i/o wait I/O Blocked Terminated

Dispatched

Freed

Waiting

Condition wait

Zombie

State Diagram showing the task lifecycle

rob@olveston [100] rlogin milly Last login: Wed Mar 29 19:22:33 from rob@milly [41] rob@milly [41] ps -A | wc -l 450 rob@milly [42] rob@milly [42] logout Connection closed. rob@olveston [101] rob@olveston [101] ps -A | wc -l 55 rob@olveston [102]

Using ps & wc to count running tasks


CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 238

UID PID PPID STIME

(f,l) (all) (f,l) (f)

The effective user ID number of the process (the login name is printed under the -f option). The process ID of the process (this number is used when killing a process). The process ID of the parent process. The star ting time of the process, given in hours, minutes, and seconds. (A process begun more than 24 hours before the ps inquir y is displayed in days and months) The controlling terminal for the process ("?" is shown when there is no controlling terminal as for background or daemon processes) The cumulative execution time for the process. The command name. (the full command name and its arguments, up to a limit of 80 chars, are printed with the -f option). The state of the process, (use the -f option): O Process is running on a processor. S Sleeping: process is waiting for an event to complete. R Runnable: process is on run queue. Z Zombie state: process terminated and parent is not waiting. T Process is stopped, either by a job control signal or because it is being traced. Processor utilization for scheduling. Not printed when the -c option is used.

TTY TIME CMD S

(all) (all) (all) (l)

(f,l)

Information in the ps display, from the man page

Time-slicing Demand preemption Cooperative Interrupt driven

Process scheduling techniques

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 239

rob@olveston [141] ps -Af UID PID PPID C STIME root 0 0 0 Mar 16 root 1 0 0 Mar 16 root 2 0 0 Mar 16 root 3 0 0 Mar 16 root 322 297 0 Mar 16 root 122 1 0 Mar 16 root 318 1 0 Mar 16 root 102 1 0 Mar 16 root 112 1 0 Mar 16 root 110 1 0 Mar 16 root 284 1 0 Mar 16 root 226 1 0 Mar 16 root 240 1 0 Mar 16 root 230 1 0 Mar 16 root 249 1 0 Mar 16 root 259 1 0 Mar 16 root 319 1 0 Mar 16 root 274 1 0 Mar 16 root 292 1 0 Mar 16 root 321 318 0 Mar 16 rwilliam 340 323 0 Mar 16 root 325 1 0 Mar 16 rwilliam 408 407 0 Mar 16 rwilliam 342 340 0 Mar 16 rwilliam 388 378 0 Mar 16 rwilliam 412 1 0 Mar 16 rwilliam 378 342 0 Mar 16 rwilliam 389 388 0 Mar 16 rwilliam 407 389 0 Mar 16 rwilliam 19576 407 0 10:07:01 rwilliam 415 412 0 Mar 16 rwilliam 19949 19577 0 14:04:16 rwilliam 469 407 0 Mar 16 rwilliam 1061 1050 0 Mar 16 rwilliam 553 407 0 Mar 16 rwilliam 11510 1 0 Mar 22 root 20818 19577 1 18:01:46 rwilliam 20304 19949 0 15:31:45 rwilliam 1050 407 0 Mar 16 rwilliam 12251 1 0 Mar 22 rwilliam 19577 19576 0 10:07:02

TTY TIME CMD ? 0:01 sched ? 0:02 /etc/init ? 0:00 pageout ? 3:39 fsflush ? 145:37 /usr/openwin/bin/Xsun :0 -noban ? 0:00 /usr/sbin/inetd -s ? 0:00 /usr/lib/saf/sac -t 300 ? 0:00 /usr/sbin/rpcbind ? 0:00 /usr/sbin/kerbd ? 0:00 /usr/lib/netsvc/yp/ypbind ? 0:02 /usr/sbin/vold ? 0:00 /usr/lib/autofs/automountd ? 0:01 /usr/sbin/cron ? 0:00 /usr/sbin/syslogd ? 0:01 /usr/sbin/nscd ? 0:01 /usr/lib/lpsched console 0:00 /usr/lib/saf/ttymon -g -h -p olves ? 0:00 /usr/lib/utmpd ? 0:00 /usr/lib/sendmail -q15m ? 0:00 /usr/lib/saf/ttymon ? 0:00 /bin/ksh /usr/dt/config/Xsession ? 0:00 /usr/openwin/bin/fbconsole -d :0 ? 0:00 olwmslave ? 0:00 /bin/ksh /usr/dt/bin/Xsession ? 0:00 /bin/ksh /usr/dt/config/Xsession ?? 0:00 /usr/openwin/bin/cmdtool -Wp 0 0 ? 0:00 /bin/tcsh -c unsetenv _ PWD; ? 0:00 /bin/ksh /home/staff/csm/csstaff/ ? 0:18 olwm -syncpid 406 ?? 0:02 /usr/openwin/bin/xterm pts/3 0:00 /bin/tcsh pts/5 0:05 ghostview /tmp/tmp.ps ? 10:35 /usr/local/bin/emacs ? 0:00 (dns helper) ? 0:21 /usr/openwin/bin/filemgr ? 4:08 /opt/simeon/bin/simeon.orig -u pts/5 0:00 ps -Af pts/5 0:06 gs -sDEVICE=x11 -dNOPAUSE -dQUIET ? 14:39 /usr/local/netscape/netscape ? 0:17 /usr/local/Acrobat4/Reader/sparcs pts/5 0:01 tcsh

Displaying Unix task list using ps

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 240

sched: init: pageout: fsush: Xsun: inetd: sac: rpcbind: kerbd: ypbind: vold: automountd: cron: syslogd: nscd: lpsched: ttymon: utmpd: sendmail: ttymon: ksh: fbconsole: olmslave: ksh: ksh: cmdtool: tcsh: ksh: olwm: xterm: tcsh: ghostview; emacs: dns: lemgr: simeon: ps: gs: netscape: acroread: tcsh:

the O/S scheduler, notice the PID value, an impor tant process, following boot startup process from boot time, gets all the other Unix processes started virtual memory page handler updates the super block and ushes data to disk X-window ser ver Internet server daemon, provides remote services such as ftp, telnet, rlogin, talk port ser vices access controller address mapper for remote procedure calls source of kerberos unique keys, used for network user authentication NIS distributed password system le system (volume) management for CDROMs and oppy disk drives daemon to handle remote le system mount/unmout requests schedules tasks to run at particular times system message handler and router name ser vice cache daemon printer service scheduler monitors terminal por ts for activity user accounting daemon Internet mail server monitors terminal por ts for activity Korn shell user interface console window Open Look X-window manager second korn shell user interface third Korn shell user interface command-tool window handler a tenex shell user interface four th Korn shell Open Look Window Manager X terminal window a tenex shell user interface PostScript screen viewer the best editor! domain naming service for Internet name to IP number conversions drag n drop le manager, useful for oppy disks mail client this produced the process listing! ghostscript translator Netscape Navigator Web browser Adobe Acrobat reader for viewing pdf documents another user interface shell

Common Unix processes

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 241

Task 1

Task 2

Task 3

Task 4

Piping data between tasks in Unix


rob> world > hello.txt rob> echo "Hello world!" > world.txt rob> tr "\r" < ch_10.asc > ch_10 rob> cat header ch_* > book rob> cat > letter << +++ ? Dear Craig, ? Here is the book that I promised to send ? Rob ? +++ rob>

Redirecting data from tasks and les in Unix


Stdin 0
Unix process

Stdout 1

Stderr 2

Standard I/O for Unix processes

WAIT(sem_buff) . . . . //critical region code . . . . SIGNAL(sem_buff);

Semaphore operators, WAIT and SIGNAL


CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 242

WRITER Task produce a new item for Consumer Task WAIT(sem_space) WAIT(sem_free) place item on buffer queue SIGNAL(sem_free) SIGNAL(sem_data) END_WRITER READER Task WAIT(sem_data) WAIT(sem_free) take item from buffer queue SIGNAL(sem_free) SIGNAL(sem_space) process the item END_READER

Semaphores protecting a cyclic data buffer


#include <stdio.h> #include <signal.h> #define MYSIG 44 /* Signal handler function, evoked by sig 44 reinstalls after each sig hit, prints number of hits */ void getsig(int s) { static int count = 0; printf("signal %d again, %dth time \n", s, ++count); signal(MYSIG, getsig); } /* Process to demonstrate signals, sets up a sig handler to count the number of sig hits received. Loops forever. Start using "kbdcnt &" and make note of pid value returned Recommend to use "kill -44 pid" to send signals Remove using "kill -9 pid" */ int main(void) { signal(MYSIG, getsig); printf("start counting kbd kills\n"); while(1) {}; return 0; }

Unix signal handler to count and display signal hits


CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 243

rob [262] rob [263] gcc kbdcnt.c rob [264] a.out & [1] 9539 rob [265] start counting kbd kills kill -44 9539 rob [266] signal 44 again, 1th time kill -44 9539 rob [267] signal 44 again, 2th time kill -44 9539 rob [268] signal 44 again, 3th time kill -44 9539 rob [269] signal 44 again, 4th time

compile the code run kbdcnt process

send signal 44

Kill

signal 44

kbdcnt

Using a signal to notify a Unix process

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 244

#include <stdio.h> #include <signal.h> #include <errno.h> #define PSIG 43 #define CSIG 42 /* check the value of NSIG in */ /* /usr/include/sys/signal.h */ /* before choosing the signal values */

int ccount = 0; int pcount = 0; char str[] = "error message "; void psigfunc(int s) { pcount++; signal(CSIG, psigfunc); } void csigfunc(int s) { ccount++; signal(PSIG, csigfunc); } main() { int ke, tpid, ppid, cpid; ppid = getpid(); cpid = fork(); /* spawn child process */ if ( cpid == -1) { printf("failed to fork\n"); exit(1); Continues }

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 245

if (cpid == 0 ) { /* Child process executes here */ signal(PSIG, csigfunc); printf("Child started\n"); while (1) { pause(); printf("Child hit! count = %d\n",ccount); sleep(rand()%10); if( (kill(ppid, CSIG)) ) perror(str); } } else { /* Parent process continues execution from here */ signal(CSIG, psigfunc); printf("Parent started\n"); while (1) { sleep(rand()%10); if( (kill(cpid, PSIG)) ) perror(str); pause(); printf("Parent hit! count = %d\n",pcount); } }

PSIG 43
Parent Child

CSIG 42

Demonstrating the use of Signals by Unix Processes


rob@olveston [52] a.out Child started Parent started Child hit! count = 1 Parent hit! count = 1 Child hit! count = 2 Parent hit! count = 2 Child hit! count = 3 Parent hit! count = 3 Child hit! count = 4 Parent hit! count = 4 Child hit! count = 5 C rob@olveston [53]

Signal demonstrator program running on Unix


CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 246

rob@olveston [40] trial & rob@olveston [41] ps PID TTY TIME CMD 451 pts/4 0:00 tcsh 469 pts/4 0:02 trial rob@olveston [42]

pid 469 Parent


main() { cpid = fork();

fork
rob@olveston [43] ps PID TTY TIME 451 pts/4 0:00 469 pts/4 0:02 472 pts/4 0:02 rob@olveston [44]

pid 469 Parent


CMD tcsh trial trial
main() { ...... ...... else { Parent continues .......

pid 472 Child


main() { ...... if (cpid == 0 ) { Child process star t executing ......

Unix process creation using fork( )


Vir tual Address Segment number Page number Displacement

Seg Table Reg Segment table Page table

Vir tual to physical address translation


sh csh bash tcsh ksh Original shell from Steve Bourne C shell from Bill Joy borne again shell Tenex shell, my favourite Korn shell, ver y popular

Interactive Unix Shells


CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 247

rob [52] grep "ofthe" ls | egrep "ch_.." ch_01: symbiosis established ofthe hardware and soft ch_11:as little as it is, the start ofthe applicatio rob [53] rob [53] mail cat mail_list < message rob [54] rob[54] echo "There are who | wc -l users logged in at date" There are 12 users logged in at Tue June 20 20:23:55 BST 2000 rob [55]

Examples of shell command substitution

echo "hello other window" > /dev/pts/0


value species which x-window to send to 0, 1, 2...

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 248

rob@olveston [154] ls /dev arp icmp audio ie audioctl ip bdoff ipd be ipdcm conslog ipdptp console isdn cua kbd diskette kmem diskette0 kstat dsk ksyms dtremote le dump llc1 ecpp0 log es logindmux fb m640 fb0 md fbs mem fd mouse fd0 null fd0a openprom fd0b partn fd0c printers hme profile rob@olveston [155] ptmajor ptmx pts ptyp0 ptyp1 ptyp2 ptyp3 ptyp4 ptyp5 ptyp6 ptyp7 ptyp8 ptyp9 ptypa ptypb ptypc ptypd ptype ptypf ptyq0 ptyq1 ptyq2 ptyq3 ptyq4 ptyq5 ptyq6 ptyq7 ptyq8 ptyq9 ptyqa ptyqb ptyqc ptyqd ptyqe ptyqf ptyr0 ptyr1 ptyr2 ptyr3 ptyr4 ptyr5 ptyr6 ptyr7 ptyr8 ptyr9 ptyra ptyrb ptyrc ptyrd ptyre ptyrf qe rawip rdiskette rdiskette0 rdsk rfd0 rfd0a rfd0b rfd0c rmt sad sehdlc sehdlc0 sehdlc1 sound sp spcic stderr stdin stdout swap syscon systty tcp term ticlts ticots ticotsord tnfctl tnfmap tty ttya ttyb ttyp0 ttyp1 ttyp2 ttyp3 ttyp4 ttyp5 ttyp6 ttyp7 ttyp8 ttyp9 ttypa ttypb ttypc ttypd ttype ttypf ttyq0 ttyq1 ttyq2 ttyq3 ttyq4 ttyq5 ttyq6 ttyq7 ttyq8 ttyq9 ttyqa ttyqb ttyqc ttyqd ttyqe ttyqf ttyr0 ttyr1 ttyr2 ttyr3 ttyr4 ttyr5 ttyr6 ttyr7 ttyr8 ttyr9 ttyra ttyrb ttyrc ttyrd ttyre ttyrf udp volctl winlock wscons zero

Unix device drivers in directory /dev

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 249

rob@olveston [101] more /etc/termcap . . . . . xterm|vs100|xterm terminal emulator (X Window System):\ :AL=\E[%dL:DC=\E[%dP:DL=\E[%dM:DO=\E[%dB:IC=\E[%d@:U :al=\E[L:am:\ :bs:cd=\E[J:ce=\E[K:cl=\E[H\E[2J:cm=\E[%i%d;%dH:co#8 :cs=\E[%i%d;%dr:ct=\E[3k:\ :dc=\E[P:dl=\E[M:\ :im=\E[4h:ei=\E[4l:mi:\ :ho=\E[H:\ :is=\E[r\E[m\E[2J\E[H\E[?7h\E[?1;3;4;6l\E[4l:\ :rs=\E[r\E[m\E[2J\E[H\E[?7h\E[?1;3;4;6l\E[4l\E<:\ :k1=\EOP:k2=\EOQ:k3=\EOR:k4=\EOS:kb=H:kd=\EOB:ke=\E :kl=\EOD:km:kn#4:kr=\EOC:ks=\E[?1h\E=:ku=\EOA:\ :li#65:md=\E[1m:me=\E[m:mr=\E[7m:ms:nd=\E[C:pt:\ :sc=\E7:rc=\E8:sf=\n:so=\E[7m:se=\E[m:sr=\EM:\ :te=\E[2J\E[?47l\E8:ti=\E7\E[?47h:\ :up=\E[A:us=\E[4m:ue=\E[m:xn:

Unix termcap entry for an Xterm

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 250

Code al am bs cd ce cl cm cs ct dc dl im ho %d %2 %3 %. %+v %>xy %r %i %% %n %B %D

Arg str bool bool str str str str str str str str str str

Padding (P*) (o) (P*) (P) (P*) (NP) (NP) (P) (P*) (P*) (P)

Function add new blank line terminal has automatic margins terminal can backspace with H clear to end of display clear to end of line clear screen and home cursor cursor move to row m, column n change scroll region to lines m thro n clear all tab stops delete character delete line enter insert mode home cursor

decimal number starting at 0 same as %2d same as %3d ASCII equiv adds x then taken as % if value is >x; then add y. no transmission reverse order of rows/columns origin is at 1,1 not 0,0 gives a single % XOR row and column (??) BCD format reverse coding

Some Unix termcap metacodes

CSA Rob Williams Pearson Education (c) 2006

CSA ch 17 - p 251

CSA Ch 18
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 18 - p 252

18. CSA - Windows XP


User Applications

User Mode

Win NT Subsystems Native API NT Executive

Kernel Mode
NT Kernel HAL Hardware Abstraction Layer Hardware

Windows-NT/XP structure
Applications Winr32 Subsys OS/2 Subsys Posix Subsys DOS Subsys

Native API NT Kernel

Win32 and the Kernel

CSA Rob Williams Pearson Education (c) 2006

CSA ch 18 - p 253

Displaying the PC task list using the Task Manager

CSA Rob Williams Pearson Education (c) 2006

CSA ch 18 - p 254

Registr y Editor windows displayed


HKEY_LOCAL_MACHINE holds the hardware conguration, installed device drivers, network protocols, software classes. Congconguration parameters for local computer Enum device conguration Hardwareserial por t conguration Networkuser login information Securityremote administration permissions Softwareinstalled software Systembooting information

HKEY_CURRENT_CONFIG holds the current hardware conguration, where options exist HKEY_CLASSES_ROOT HKEY_USERS HKEY_CURRENT_USER holds document types, le associations, shell interface holds login users software preferences and desktop conguration holds copies of the preferences of the curent user.

Registr y top level keys


CSA Rob Williams Pearson Education (c) 2006

CSA ch 18 - p 255

Setting network Shares and Permissions to a directory

User name Passwords Machine name Workgroup names Share names

20 char 14 char 15 char 15 char 12 char

Discrepency in effective string lengths

CSA Rob Williams Pearson Education (c) 2006

CSA ch 18 - p 256

Installing a shared directory as a local virtual drive

CSA Rob Williams Pearson Education (c) 2006

CSA ch 18 - p 257

CSA Ch 19
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 19 - p 258

19. CSA - Filing Systems


Data organization Sequential Indexedsequential Direct Database Application type batch processing batch processing on-line on-line Advantages Simple, efcient difcult Sequential and direct access no data sorting No data sorting fast access exible access Disadvantages Maintenance data needs sorting Index takes up space less efcient Space inefcient inconvenient to use Performance poor maintenance costs

Data ling and databases

Windows le browser showing the le hierarchy


CSA Rob Williams Pearson Education (c) 2006

CSA ch 19 - p 259

Sun File Manager display with oppy disk browser

Primary Par tition

Secondar y Partitions Master Par tition Boot Record

Hard Disk with Four Par titions

CSA Rob Williams Pearson Education (c) 2006

CSA ch 19 - p 260

Cylinder 0 0 5 3 1 6 7

Cylinder 1 5 7

Cylinder 22 Cylinder 53 Cylinder 120 3 1 4 2 Platter 0 Platter 1

2 Platter 2 4 Platter 3 Drive spindle

Alternative layouts for blocks 1, 2, 3, 4, 5 & 7 to reduce access times (Head Movement Delays)

CSA Rob Williams Pearson Education (c) 2006

CSA ch 19 - p 261

Signature

AA55H Partition 1 Partition 2 Partition 3 Partition 4 Program to check Partition Table and transfer to Boot Par tition Sector Size star t bytes 00H 01H 04H 05H 08H OCH Content Head, Cylinder, Sector
H7 H6 H5 H4 H3 H2 H1 H0 C9 C8 S6 S5 S4 S3 S2 S1 S0 C7 C6 C5 C4 C3 C2 C1 C0

Partition Table

Code

1 Boot ag 3 Star t of partition 1 System Flag 3 End of Par tition 4 Star t of Sector 4 # sectors

Disk Master Par tition Boot Record

Boot Flag - 00H Inactive (nonbootable), 80H Active (bootable) System Flag -01H FAT-12 04H FAT-16 05H Extended DOS partition 08H AIX 0AH OS/2 0BH FAT-32 DBH CP/M (!) 83H Linux

OS boot loader program # Hidden Sectors # Heads # Sectors / Track # sectors / FAT media byte (F8H) # logical Sectors # Root DIR entries # FATS # Boot Sectors # Sectors / Cluster # Bytes / sector OEM Name/ID jmp to loader 2 byte 2 byte 2 byte 2 byte 1 byte 2 byte 2 byte 1 byte 2 byte 1 byte 2 byte 8 byte 3 byte

A Par tition Boot Record (non Master)


CSA Rob Williams Pearson Education (c) 2006

CSA ch 19 - p 262

le name le type owner id permissions le size create date disk address disk block

Essential information for director y entries

rob@milly [20]/usr/sbin/mount / on /dev/dsk/c0t0d0s0 read/write/setuid on Mon Jul 19 08:12:44 2000 /usr on /dev/dsk/c0t0d0s3 read/write/setuid on Mon Jul 19 08:12:44 2000 /proc on /proc read/write/setuid on Mon Jul 19 08:12:44 2000 /dev/fd on fd read/write/setuid on Mon Jul 19 08:12:44 2000 /var on /dev/dsk/c0t0d0s4 read/write/setuid on Mon Jul 19 08:12:44 2000 /cache/cache1 on /dev/dsk/c0t0d0s7 setuid/read/write on Mon Jul 19 08:13:4 /cache/cache2 on /dev/dsk/c0t1d0s7 setuid/read/write on Mon Jul 19 08:13:4 /cache/cache3 on /dev/dsk/c0t2d0s7 setuid/read/write on Mon Jul 19 08:13:4 /cache/cache4 on /dev/dsk/c0t3d0s7 setuid/read/write on Mon Jul 19 08:13:4 /cache/cache5 on /dev/dsk/c0t10d0s7 setuid/read/write on Mon Jul 19 08:13: /opt on /dev/dsk/c0t0d0s6 setuid/read/write on Mon Jul 19 08:13:45 2000 /tmp on /dev/dsk/c0t0d0s5 setuid/read/write on Mon Jul 19 08:13:45 2000 /tftpboot on /dev/dsk/c0t1d0s0 setuid/read/write on Mon Jul 19 08:13:45 19 /home/student/csm/BSc/CRTS/2 on /dev/dsk/c0t1d0s3 nosuid/read/write/quota /home/student/csm/BSc/other on /dev/dsk/c0t1d0s4 nosuid/read/write/quota on /home/student/csm/BA/other on /dev/dsk/c0t1d0s5 nosuid/read/write/quota on /home/student/csm/PhD on /dev/dsk/c0t1d0s6 nosuid/read/write/quota on Mon /home/student/csm/BSc/CRTS/2p on /dev/dsk/c0t2d0s3 nosuid/read/write/quota . . .

Unix mount table

CSA Rob Williams Pearson Education (c) 2006

CSA ch 19 - p 263

le name TEST

le ext DAT

le attr

reser v

LBN create create 1st le time date cluster length

CHS BIOS LBN Disk

10 9 8

FFFFH

10

4 bytes

7 6 5 4 3

6 10

Disk Directory: 32 byte entries

FAT-16 Directory and File Allocation Table

Sector Size 512B 512B 512B 512B 512B

Sectors per Cluster 4 16 32 64 16

Cluster Size 2kB 8kB 16kB 32kB 8kB

Cluster Index Size 16bits 16bits 16bits 16bits 32bits

Nax Volume Capacity 128MB 512MB 1GB 2GB 32TB

2 1 0

FAT

FAT cluster size and volume capacity

CSA Rob Williams Pearson Education (c) 2006

CSA ch 19 - p 264

struct stat { dev_t long ino_t mode_t nlink_t uid_t gid_t dev_t long off_t long timestruc_t timestruc_t timestruc_t long long char long }; st_dev; st_pad1[3]; st_ino; st_mode; st_nlink; st_uid; st_gid; st_rdev; st_pad2[2]; st_size; st_pad3; st_atime; st_mtime; st_ctime; st_blksize; /* file size in bytes */ /* reserve for future off_t expansion */ /* last access time */ /* last write time (modification) */ /* last status change time */ /* device holding the relevant directory */ /* reserve for dev expansion, */ /* inode number */ /* number of active links to the file */ /* file owners ID */ /* designated group id */

st_blocks; st_fstype[_ST_FSTYPSZ]; st_pad4[8]; /* expansion area */

Unix le system inode structure

Boot Block

Super Block

owner uid gid of owner le type rwx access modes time of last access time modied time of inode change le size

inode Blocks

Data Blocks

direct 1 direct 2 direct 3 direct 4 direct 5 direct 6 direct 7 direct 8 direct 9 direct 10 indirect double indirect triple indirect

Unix inode le access records


CSA Rob Williams Pearson Education (c) 2006

CSA ch 19 - p 265

directory name test.c inodp


name name name name name name name name name inodp inodp inodp inodp inodp inodp inodp inodp inodp

principal le inode dir inode 0 inodp 1 inodp 2 inodp 3 inodp 4 inodp 5 inodp 6 inodp 7 inodp 8 inodp 9 inodp 10 inodp 11 inodp 12 Iinode 13 DIinode 14 TIinode

Data Block Data Block Data Block index block 0 dp 1 dp 2 dp 3 dp 4 dp 5 dp 994 995 996 997 998 999 dp dp dp dp dp dp

Data Block Data Block Data Block

Unix inode pointers indicating a les data blocks

CSA Rob Williams Pearson Education (c) 2006

CSA ch 19 - p 266

/ root directory name inodp bin name inodp etc name inodp usr name inodp dev name inodp lib name inodp tmp name inodp sbin name local inodp name home inodp name inodp pub

Cong dir inode 0 inodp 1 inodp 2 inodp 3 inodp 4 inodp 5 inodp 6 inodp 7 inodp 8 inodp 9 inodp 10 inodp 11 inodp 12 Iinode 13 DIinode 14 TIinode /stuff dir inode 0 inodp 1 inodp 2 inodp 3 inodp 4 inodp 5 inodp 6 inodp 7 inodp 8 inodp 9 inodp 10 inodp 11 inodp 12 Iinode 13 DIinode 14 TIinode rusers directory
name name name name name name name name name name inodp inodp inodp inodp inodp inodp inodp inodp inodp inodp

/etc dir inode 0 inodp 1 inodp 2 inodp 3 inodp 4 inodp 5 inodp 6 inodp 7 inodp 8 inodp 9 inodp 10 inodp 11 inodp 12 Iinode 13 DIinode 14 TIinode uucp director y
name name name name name name name name name name inodp inodp inodp inodp inodp inodp inodp inodp inodp inodp

Data Block Data Block Data Block

Relating Unix directories to the inode blocks

CSA Rob Williams Pearson Education (c) 2006

CSA ch 19 - p 267

MTF Header 1 2 3 4 5 6 7 8 9 10 fp fp fp fp fp fp fp fp fp fp

Info Director y Block

Name

DOS Security Name

Cluster Pointers

Data Block Data Block

Windows-NTFS Master File Table

Read owner groupees any user

Write/ delete

Execute/ attach

File and directory access control options

CSA Rob Williams Pearson Education (c) 2006

CSA ch 19 - p 268

strip 1 strip 2 strip 3 strip 4 strip 5 strip 6 strip 7 strip 8 strip 9 strip 10

RAID 0
1 2 3 4 5

Data Block RAID 1

Data Block
byte 1 byte 2 byte 3 byte 4 CRC

RAID 2/3

Data Block
strip 1 strip 2 strip 3 strip 4 chksum strip 5 strip 6 strip 7 strip 8 chksum

RAID 4
1 2 3 4 5

Data Block RAID 5


strip 1 strip 2 strip 3 strip 4 chksum strip 5 strip 6 strip 7 chksum strip 8 strip 9 strip 10 chksum strip 11 strip 12 strip 13 chksum strip 14 strip 15 strip 16 chksum strip 17 strip 18 strip 19 strip 20

RAID disk conguations

CSA Rob Williams Pearson Education (c) 2006

CSA ch 19 - p 269

rob@olveston [63] ls -al -rwx-----1 rob csstaff 280 -rwx-----1 rob csstaff 48 -rwx-----1 rob csstaff 229 -rwx-----1 rob csstaff 25007 -rwx-----1 rob csstaff 251 -rwx-----1 rob csstaff 243 rob@olveston [64] chmod 666 unzip rob@olveston [65] ls -al unzip -rw-rw-rw1 rob csstaff 25007 rob@olveston [66] chmod 000 unzipit rob@olveston [67] ./unzipit ./unziput: permission denied. rob@olveston [68] ls -al unzip ---------1 rob csstaff 25007 rob@olveston [69] chmod 100 unzipit rob@olveston [70] ./unzipit rob@olveston [71] rob@olveston [71] chmod 711 unzipit rob@olveston [72] ls -al unzipit -rwx--x--x 1 rob csstaff 25007 rob@olveston [73]

Sep 5 Sep 11 Jan 22 Apr 1 Sep 5 Sep 5 Apr 1

1998 1999 1999 1999 1998 1998

timezone tit to_arthur unzipit vorc vorcorn

1999 unzipit

Apr

1999 unzipit

Apr

1999 unzipit

Setting File Access Permissions in Unix

CSA Rob Williams Pearson Education (c) 2006

CSA ch 19 - p 270

CSA Ch 20
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 271

20. CSA - Visual Output

Display Full colour Reduced-range colour Grey-scale monochrome Black-white monochrome

Pixel data 24 bits 8 bits 8 bits 1 bit

Display size pixels 1024 x 768

Image size Bytes 2.25MB 0.75MB 0.75MB 96kB

Data requirements for different display types


Magnied view of pixels on the screen

Vertical Fly Back

Horizontal Fly Back

Bitmapped raster display

RGB electron guns Shadow mask BGR

Glass front screen with phosphor coating

Shadow mask inside a colour CRT


CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 272

Resolution 640 x 480 640 x 480 800 x 600 800 x 600 1024 x 768 1024 x 768 1152 x 864 1280 x 1024 1280 x 1024

Ver tical scan rate Hz 60 72 75 85 75 85 85 75 85

Horizontal scan rate kHz 31.5 37.8 46.9 53.7 60.0 68.8 77.6 80.0 91.2

Normal CRT horizontal and ver tical scan rates


The time period for writing a single pixel onto the screen can be estimated:
1 = 21 ns/pixel 60 x 1024 x 768

100Hz driver clock

light polarizing lter back plane electrode liquid crystal polarizing lter

0 1
Control signals

in phase OFF out of phase ON

Liquid crystal panels

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 273

Twisted nematic LCD panels, showing the polarized, ribbed panels

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 274

.PS define Driver { [line right 0.3 down 0.1 line left 0.3 down 0.1; line up 0.2]}

Base: box wid 6 ht 2 invis line up 2 from Base.sw line up 2 from Base.sw+0.4,0 line right 0.4 from Base.w+0,0.4 line right 0.4 from Base.w-0,0.4 """""image""data" below circle rad 0.02 at Base.w+0.2,0 line up 0.5 from last circle; arrow right 2 "color#""" above Palet: box wid 1.2 ht 1 ibox wid 1.2 ht 0.2 with .n at Palet.n "RGB Palette" ibox wid 1.2 ht 0.2 with .n at last box.s "table" ibox wid 1.2 ht 0.2 with .n at last box.s "R G B" {move up 0.1; line left 1.2} {move down 0.1 line left 0.4; {line up 0.2}; line left 0.4 {line up 0.2}; line left 0.4} line down 0.7 from Palet.s-0.3,0 arrow right 1.2 "8 bits" below; [Driver] line right 0.2 from last [].e then up 0.25 then right 0.2 box wid 0.6 ht 0.3 invis with .n at last [].s "DACs" line down 0.1 from Palet.s+0.3,0 arrow right 0.6 "8 bits" below; [Driver] line right 0.2 from last [].e; line down 0.25; line right 0.2 line down 0.4 from Palet.s arrow right 0.9 "8 bits" below; [Driver] line right 0.4 from last [].e then up 0.07 then right 0.4 then righ line down 0.6 "CRT " rjust line left 0.5 up 0.2; line left 0.4; line up 0.07 box wid 0.8 ht 0.2 at Base.w+1.1,0.2 "image base" box wid 0.8 ht 0.2 with .n at last box.s-0,0.1 "Y X" {arrow <- right 0.2 from last box.e move down 0.1 for i=1 to 2 do { line right 0.1 then up 0.2 then right 0.1 then down 0.2 } line right 0.1 } line from last box.n to last box.s arrow -> left 0.2 from last box.w box wid 0.6 ht 0.4 invis with .n at last box.s "image pointer" "23" at Palet.nw+0,0.2;"0" at Palet.ne+0,0.2 box wid 0.5 ht 0.3 invis "Memory" with .nw at Base.sw .PE

Example pic script

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 275

<?xml version="1.0" standalone="no"?> <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd"> <svg width="100%" height="100%" version="1.1" xmlns="http://www.w3.org/2000/svg"> <rect x="250" y="50" rx="20" ry="20" width="150" height="100" style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/> <rect x="250" y="200" rx="20" ry="20" width="150" height="100" style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/> <rect x="50" y="200" rx="20" ry="20" width="150" height="100" style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/> <rect x="450" y="200" rx="20" ry="20" width="150" height="100" style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/> <rect x="250" y="350" rx="20" ry="20" width="150" height="100" style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/> <rect x="250" y="500" rx="20" ry="20" width="150" height="100" style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/> <rect x="50" y="500" rx="20" ry="20" width="150" height="100" style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/> <rect x="450" y="500" rx="20" ry="20" width="150" height="100" style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/> <line <line <line <line <line <line <line x1="330" x1="330" x1="330" x1="330" x1="330" x1="330" x1="330" y1="150" y1="150" y1="150" y1="300" y1="450" y1="450" y1="450" x="280" x="290" x="100" x="460" x="410" x2="330" x2="125" x2="525" x2="330" x2="330" x2="525" x2="125" y2="200" y2="200" y2="200" y2="350" y2="500" y2="500" y2="500" stroke="#000000" stroke="#000000" stroke="#000000" stroke="#000000" stroke="#000000" stroke="#000000" stroke="#000000" stroke-width="2" stroke-width="2" stroke-width="2" stroke-width="2" stroke-width="2" stroke-width="2" stroke-width="2" /> /> /> /> /> /> />

<text id="S1" <text id="S2" <text id="S3" <text id="S4" <text id="S5" </svg>

y="100" y="250" y="250" y="250" y="375"

font-size="25"> System </text> font-size="25"> Body </text> font-size="25"> Init </text> font-size="25"> Closedown </text> font-size="50"> * </text>

An SVG script, rendered by Firefox

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 276

DB-15 VGA socket to monitor

HM64265/25

HM64265/25

Intel 740

Two tiered AGP connector

An SVGA graphics adapter card with AGP interface

Mono Hercules graphics CGA EGA VGA

1981 1983 1983 1984 1987

Text only mode offered by original 8088 PC First mono graphics card 720 x 348

rst colour (4) graphics card from IBM 320 x 200 double horizontal resolution if limited to mono 16 colour graphics EGA compatible 16 colour high resolution 256 colours 256k colours (18 bit/pixel) 256 colours (8 bits/pixel) 24 bit true colour (3 bytes/pixel) 32768 colours (15 bits) 640 x 350

640 x 480 320 x 200 (CGA) 1024 x 768 1280 x 1024

SVGA XGA

1990 1995 1997

Evolving range of standards for screen display

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 277

1 11

DVI-I dual standard monitor socket

DB-15 SVGA Monitor Socket

Pin # 1 2 3 4 5 6 7 8 C1 C2 C3 C4 C5

Signal Name TMDS Data2TMDS Data2+ TMDS Data2/4 Shield TMDS Data4TMDS Data4+ DDC Clock [SCL] DDC Data [SDA] Analog Ver t Sync Analog Red Analog Green Analog Blue Analog Horiz Sync Analog GND Return

Pin # 9 10 11 12 13 14 15 16

Signal Name TMDS Data1TMDS Data1+ TMDS Data1/3 Shield TMDS Data3TMDS Data3+ +5 V Power Ground Hot Plug Detect

Pin # 17 18 19 20 21 22 23 24

Signal Name TMDS Data0TMDS Data0+ TMDS Data0/5 Shield TMDS Data5TMDS Data5+ TMDS Clock Shield TMDS Clock + TMDS Clock -

29 pin DVI connector pinout and signal names


Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mon id H Sync V Sync ground RED rtn GREEN rtn BLUE rtn key-pin SYNC rtn SVGA RED GREEN BLUE

15 pin SVG connector pinout and signal names


CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 278

24bit colour value image pointer Y image data X

23

B
8 bits 8 bits 8 bits

CRT DACs

image base reg

Display Memor y

Driving a colour screen


23 0

8 bit colour # image pointer row column Y X image data image base reg

RGB Palette table R G B

04 03 02 01 00
8 bits

8 bits 8 bits

CRT

Display Memory

DACs

Driving a PC screen using a palette table

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 279

65s 14.31818 MHz Crystal Oscillator Pixel Clock


9 0

H Sync 1024 Line Clock


9

60
0

Field Clock

V Sync

row 3

Screen column position

Screen row position


0

60ms

Raster control

row 2

Display memor y

19

row 1

Display memory address Address to display memor y

Synchronization of screen raster with display memor y

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 280

electron spray Erase lamp Cleaner Scanning head Hopper Paper Tray Toner paper feed Motor
CPU IRQ

Motor laser source

PostScript Interpreter Memory

I/O

serial link from host computer

Laser Printer
For a page represented as a 600 dpi image: single A4 page image = 11x 7x 600x 600 = 3. 5Mbytes 8

The same page may be represented by far less data if it is ASCII coded: Maximum number of characters on an A4 page = 60x 100 = 6000char The number of characters on a WP page is about 2500, 2.5 Kbytes of ASCII data. Thus, the compressing ratio would be: compression ratio = 2500 = 0. 0007 3500000

Such a size reduction is certainly wor th achieving but OCR software has only recently been improved enough to give acceptably fast and accurate performance.

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 281

newpath 270 360 moveto 0 72 rlineto 72 0 rlineto 0 -72 rlineto closepath 4 setlinewidth stroke newpath 272 362 moveto 0 68 rlineto 68 0 rlineto 0 -68 rlineto closepath .8 setgray ll /Times-Roman ndfont 24 scalefont setfont 280 400 moveto 0 setgray (hello!) show showpage

Ghostview, version 1.1

hello!

**

emacs test1.ps

PostScript development, script edited by emacs, rendered by ghostview

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 282

newpath 1 0 0 setrgbcolor 200 200 moveto 0 160 rlineto 160 0 rlineto 0 -160 rlineto closepath ll newpath 360 280 moveto -80 0 rlineto 80 -40 rlineto closepath 1 setgray ll newpath 380 280 105 180 135 arcn 48 0 rlineto 0 -40 rlineto closepath 1 setgray ll /Helvetica ndfont 68 scalefont setfont 1 setgray 255 200 translate 90 rotate 0 0 moveto (UWE) show newpath 80 -130 120 0 180 arc 1 setgray 7 setlinewidth stroke 0 0 moveto -90 rotate /Helvetica ndfont 42 scalefont setfont 1 0 0 setrgbcolor -60 -40 rmoveto (BRISTOL) show showpage

Ghostview, version 1.1

**

emacs uwe_pacman.ps

More PostScript, but now in colour!

gs -dNOPAUSE -dBATCH -r1200 -sDEVICE=pdfwrite -sOutputFile=ch_16.pdf ch_16.

UWE

BRISTOL

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 283

rob [57] cat header ch_16 | groff -t -e -p -fH > ch_16.ps rob [58] gs -dNOPAUSE -dBATCH -r1200 -sDEVICE=pdfwrite -sOutputFile=ch_16.pdf ch_16.ps .... rob [57] ls -al ch_16* -rw------- 1 rwilliam csstaff -rwx------ 1 rwilliam csstaff 52114 Jul 1 08:42 ch_16 42253 Jun 28 13:26 ch_16.asc

-rw------- 1 rwilliam csstaff 840398 Jul 1 08:44 ch_16.pdf -rw------- 1 rwilliam csstaff 1212385 Jul 1 08:43 ch_16.ps -rw------- 1 rwilliam csstaff -rw------- 1 rwilliam csstaff -rw------- 1 rwilliam csstaff .... rob [58] acroread ch_l6.pdf & .... rob [59] ghostview ch_16.ps & .... rob [60] 22093 Feb 24 11:07 ch_16d 16437 Nov 5 1998 ch_16d 23975 Jun 16 16:42 ch_16

Comparing le sizes: ASCII, ps and pdf

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 284

%PDF-1.0 1 0 obj << /Type /Catalog /Pages 3 0 R /Outlines 2 0 R >> endobj 6 0 obj [/PDF /Text] endobj

7 0 obj << /Type /Font 2 0 obj /Subtype /Type1 << /Name /F1 /Type /Outlines /BaseFont /Helvetica Count 0 /Encoding /MacRomanEncoding >> >> endobj endobj xref 3 0 obj 0 8 << 0000000000 65535 f /Type /Pages 0000000009 00000 n /Count 1 0000000074 00000 n /Kids [4 0 R] 0000000120 00000 n >> 0000000179 00000 n endobj 0000000322 00000 n 0000000415 00000 n 4 0 obj 0000000445 00000 n << trailer /Type /Page << /Parent 3 0 R /Size 8 /Resources <</Font<</F1 7 0 R>>/ProcSet 6 0 /Root 1 0 R R>> /MediaBox [0 0 612 792] >> /Contents 5 0 R startxref >> 553 endobj %%EOF 5 0 obj << /Lengtb 44 >> stream BT /F1 72 Tf 100 50 Td (Hello World!) Tj ET endstream endobj

The "Hello World!" example in pdf code

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 285

Viewing the pdf File using Adobe Acrobat

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 286

File Edit View New Load Save Save As Quit

HyperBase

Layout of a typical window scheme

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 287

Vir tual Device Inferface (GDI) Bitmaps, Icons & Metales Creating Windows Operating Windows On-screen Menu handling Dealing with Mouse and Keyboard Events Handling Dialog Boxes Timer Events Threads and Process Scheduling Exception Messages Free Memory Management Device handling Printing and Text output File Management Data interchange through Clipboard OLE / DDE data interchange System Parameter Registry Management System Information DLL Management functions Network Access Routines Passing and processing Messages Audio data management

Win32 API facilities

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 288

#include <windows.h> int WINAPI WinMain(HINSTANCE a, HINSTANCE b, LPSTR c, int d) { MessageBox(NULL, "Hello Worle!", "WSM", MB_OK); return NULL; }

Your rst Windows application

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 289

Application Code Intrinsics Widgets X-Lib

X-Windows Programming
80 63 0 127 0

mm7 mm6 mm5 mm4 mm3 mm2 mm1 mm0 f/p mmx

xmm7 xmm6 xmm5 xmm4 xmm3 xmm2 xmm1 xmm0

MMX and SSE data registers

CSA Rob Williams Pearson Education (c) 2006

CSA ch 20 - p 290

CSA Ch 21
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 291

21. CSA - RISC Processors


Application code

Operating System

CU Microcode

H/w Logic Units

Functional hierarchy

Sun Microsystems UltraSparc II

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 292

1. Single length instruction codes 2. Single clock cycle execution period 3. Limited arithmetical complexity supported 4. Extensive supply of CPU registers 5. Limited repetoire of machine instructions 6. Only straightforward addressing modes supported 7. Hardware support for procedure handling 8. No structured data types recognised 9. Compiler supplied to support the architecture 10. Hardware CU, pipelined decoding 11. Simplied interrupt facilities

Principal features of RISC CPUs


MHz 1000
AMD Athlon AMD K7 Pentium II Pentium Pro Pentium i486

100

10
i8086

i386

1 1970

i8080

1980

1985

1990

1995

2000

Increasing clock speed of microprocessors

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 293

Stack passing Parameters are pushed up onto the stack before transferring control (jumping) to the subroutine. The subroutine code shares the same stack and can access the parameters through the stack or frame pointer. Copies of VALUE parameters are simply pushed onto the stack, while reference, VAR, parameters are 32 bit addresses pointing back at data. Stack frame setup overheads, and access times to non-local variables within scope are an issue.

system stack

Main Memor y

Register passing Using CPU registers to hold the parameters is the fastest method, but limited by the number and size of registers available. Compilers select this technique only if a couple of simple (integer, char) variables are to be passed IN, and for the single OUT return value from functions.

CPU registers

Register windows This is a specialised stack technique used by SPARC processors to reduce the amount of stack PUSHing and POPping. By physically overlapping the stack frames for adjacent procedures, some of the local variables can be visible as parameters with no data copying. To fur ther speed up the process, SPARC CPUs have fast stack caches. Parameter blocks For machines without stacks, the problem of where to save the return address is solved by the CALL instruction inserting the return address at the top of the procedure code before transferring control. The parameters are cunningly inserted in a block immediately after the CALL instruction, thus giving the procedure access by using the return address as a pointer. Global access Fortran and BASIC would rely on global data blocks visible to all code. This system of memor y parameter blocks has been reinstituted for graphics and Windows programming, where the number of parameters is so great that little else could be suggested.

CPU stack registers

Variety of parameter passing methods

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 294

Fetch

Decode

Readin Execute Writeback

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 System Clock

JMP NOP NOP NOP NOP AND

ADD JMP NOP NOP NOP NOP

ADD JMP NOP NOP NOP

ADD JMP NOP NOP

ADD JMP NOP

Multi-stage pipeline decoding - parallel processing

LD/ST

IF

ID

INT

RO

WB

FP

A 5 stage superscalar achitecture with 3 execution units

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 295

Dependency Type Data

Description RAW, read after write WAR, write after read WAW, write after write

Example MOV EAX,10 ADD EBX,EAX MOV EBX,EAX MOV EAX,10 MUL 100 ADD EAX,10 CMP AL,q JZ exit oating-point arithmetic

Blocked until... EAX is loaded EAX is read sequence correct Z ag set

Control

the outcome of a previous instruction is essential for an instruction to complete limited availability of hardware resources

Resource

unit free

Instruction pipeline dependencies

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 296

prefetchdecoderoperand execute store buffer stage 1 read result

Register File

Instructions from memor y

ALU A Pipeline A

Pre fetcher unit


PC

ALU B Pipeline B

ALU C Pipeline C

Use of Register File Store with superscalar processors

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 297

Mapping Table
Valid Flag 0 1 2 3 4 5 1 6 7 8 1 9 Index

Register File
r5 r6 r7 r8 r9 r10 r11 r12 r13 r14

8 3

Register renaming

Conditional Instruction address

Branch Target address

Prediction Condence Value

Control Unit Branch Prediction Table

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 298

Version v1 v2 v2a v3 v3M v4 v4T

Example core ARM1 ARM2 ARM3 ARM6 & ARM7DI ARM3M StrongArm ARM7TDMI ARM9TDMI

Description Original processor, 26 bit address, coprocessor for Beeb 32 bit multiplier, coprocessor included Acorn Archemedies/A3000 on-chip cache, semaphore support with swap instruction 32 bit address, CPSR/SPSR, MMU rst macro-cell product. enhanced multiply with 64 bit result LD/ST for 8/16 bit values, system mode iPAQ PDA, Compressed Thumb instruction set, MULA used for many mobile handsets

Pipeline 3 3 3 3 3 5 3 5 7

v5 v5TE v5TEJ v6

XScale ARM9E & ARM10E ARM7EJ & ARM926EJ ARM11 better MUL, extra DSP instcns Java option

5 5 8

Historic revisions of ARM architectures

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 299

User & system r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13/sp r14 /lr r15/pc cpsr spsr_q spsr_irq spsr_svc spsr_undef spsr_abt Fast interrupt request r8_q r9_q r10_q r11_q r12_q r13_q r14_q Interrupt request r13_irq r14_irq Super visor trap r13_svc r14_svc Undened exception r13_undef r14_undef Abor t error r13_abt r14_abt

ARM CPU registers, showing the alternate sets

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 300

11

7 6 5 4 3

shift-size sh/rot 0
11

Rindex
0

0 ldr/str
31 28 27 26 25 24 23 22 21 20 19 16 15

OR

12 bit displacement (unsigned)


12 11 0

condition

01 # P U B W L

Rn

Rd

offset eld

source/destination register base register load or store operation Rindex write back for auto indexing word or unsigned byte data backwards/forwards, sign bit for displacement pre/post index, bump pointer before or after data movement offset type, immediate or register predicate execution condition (Z, C, N, V)

Instruction formats for the ARM ldr & str instructions


Condition codes
31 27 24 23 8 4 0

N Z C V Q

F t

SVC

Jazelle Saturated Overow Carr y out Zero value Negative value, msb==1

Thumb mode enabled Fast interrupt enabled Interrupt enabled

ARM program status register

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 301

Opcode [31-28] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Mnm EQ NE CS CC MI PL VS VC HI LS GE LT GT LE AL NV

Meaning equal values not equal carr y set carr y clear negative value positive value overow no overow unsign higher unsign lower greater or equal less than greater than less or equal always never use

Flag Z=1 Z=0 C=1 C=0 N=1 N=0 V=1 V=0 C=1 && Z=0 C=0 || Z=1 N=V N!=V Z=0 && N=V Z=1 || N!=V

ARM condition codes


mov Rn, Rm ldr Rn, [Rm] str Rn, [Rm] add R0, R1, R2 cmp R0, R1 b addr bl addr mov R15, R14 ldmfd R13!, {Rm-Rn} stmfd R13!, {Rm-Rn} ldr Rn, =constant adr Rn, label copy data between registers get a variable from memory put a variable back in memory add two registers, result in third compare two registers jump to relative location (+ 32 MB) _ call subroutine (+ 32MB) _ return from subroutine pop registers from stack push registers onto stack

Basic "starter" instructions for the ARM processor

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 302

11

8 7

shift-size 8 bit immediate data


11

OR

7 6 5 4 3

shift-size sh/rot 0
11

Rindex
0

0 mov and/add/sub/cmp tst/and/orrrrr/eor/bic


31 28 27 26 25 24 21 20 19 16 15

OR Rshift

8 4 6 5 4 3

0 sh/rot 1

Rindex
0

12 11

condition

00 #

opcode

Rn

Rd

operand 2

destination register operand register set condition status ags arithmetic/logic function selector operand 2 type predicate execution condition (Z, C, N, V)
opcode opcode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Mnm and eor sub rsb add adc sbc rsc tst teq cmp cmn orr mov bic mvn

Meaning logical bit-wise AND logical bit-wise XOR subtract reverse sub arithmetic add add with carry in subtract with carry reverse sbc test test equal compare negated comp logical bit-wise OR copy register data bit clear negated mov

sh/rot Effect sh/rot Rd = Rn && Op2 00 Rd = Rn Op2 01 Rd = Rn - Op2 10 Rd = Op2- Rn 11 Rd = Rn + Op2 Rd = Rn+Op2+C Rd = Rn-Op2+C-1 Rd = Op2-Rn+C-1 Rn && Op2 RN Op2 Rn - Op2 Rn + Op2 Rd = Rn || Op2 Rd = Op2 Rd = Rn $$ Op2 Rd = Op2

Effect Rn, LSL #shift-size Rn, LSR #shift-size Rn, ASR #shift-size Rn, ASL #shift-size

Instruction formats for move, arithmetic & logical instructions

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 303

The HP iPAQ hx4700 Pocket PC, with XScale PXA 270 processor

HP iPAQ hx2400 PCB. The 420 MHz XScale CPU is shrouded by emission reduction foil
CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 304

Intel PXA270 624MHz processor 64 MB Mobile SDRAM 128 MB Flash: 2 x 64 Mbyte (Intel RD48F4400L0zb0) Up to 135 Mbyte of memory is available for user applications 100 mm transective TFT VGA 64K color display (480x640) Graphics controller (ATI Mobileon W3220) Touch screen (Texas Instruments TSC2046 /SPI) Touchpad (Synaptics NavPoint module /SPI), Removable & rechargeable Lithium-Ion battery (1800 mAh) Secure Digital (SDIO) slot Compact Flash I & II (CF) slot IrDA por t (Exar XR16L580IL 16550-compatible) WiFi LAN 802.11b capability (Texas Instruments TNETW1100B) Bluetooth (Texas Instruments BRF6150USB) RS232 port, 16550 compatible (PXA270) Integrated microphone, speaker and stereo headset jack Audio codec (AK4641) USB (PXA270) Weight: 186.7 g

HP iPAQ hx4700 series Pocket PC

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 305

Bank 3 3 3 3 3 2 2 2 2 1 1 0 0 0 0 0 0

Sel line

RAS/CAS3 RAS/CAS2 RAS/CAS1 RAS/CAS0

CS5 CS4 PSTSEL !PSTSEL CS3 CS2 CS1 CS0

MBytes 384 128 128 128 128 128 256 256 256 256 768 128 128 256 256 128 128 128 128

Physical Address Reserved zeros DRAM bank 3 DRAM bank 2 DRAM bank 1 DRAM bank 0 LCD & DMA registers Expansion & memor y SCM registers PM registers Reserved Flash/SRAM bank 5 Flash/SRAM bank 4 PCMIA socket 1 PCMIA socket 0 Flash/SRAM bank 3 Flash/SRAM bank 2 Flash/SRAM bank 1 Flash bank 0 FFFF_FFFFH

internal to SA1110 StrongARM

0000_0000H

SA1110 StrongARM 4 GByte memory map

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 306

next PC

Pipeline 16 KByte
incr PC op code

Stage 0 Fetch instr IR-0 from I-cache

+4

I-cache

branch offset R15/PC

reg write decoder

Stage 1 Decode, reg read, get branch addr.

branch addr

+disp

Register File

immediate elds

IR-1

decoder

+4

shifter

Stage 2 Execute ALU/shift, LD/ST mem addr.

ALU & multiply mux IR-2 B-repl

8 KByte
LD/ST address

0.5 KByte Minicache

D-cache

Stage 3 D-cache LD/ST

rotate

IR-3 Write Register

Stage 4 Result write-back

Block diagram for the StrongARM core

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 307

3.686 MHz 32.768 KHz

oscil oscil

PLL PLL

IMMU DMMU

Icache Dcache Minicache write buff

ARM SA-1 core

JTAG i/f

RTC OS timer GP I/O Intr Cntrl Pwr Mngt Rst Contrl

read buff

LCD control

Bridge

DMA control

Memory & PCMCIA control Serial channel 4 CODEC

Serial channel 0 USB

Serial channel 1 UART

Serial channel 2 IrDA

Serial channel 3 UART

A -A 0 25 D0-D31

Intel SA1110 StrongARM microcontroller

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 308

31 23

OUT
7

LOCAL OUT
0

GLOBAL

cwp

IN

LOCAL OUT

IN

LOCAL OUT

CPU registers

IN

LOCAL

Save

IN system stack

Restore

Main Memory

Operation of the Register File during procedure calls

CSA Rob Williams Pearson Education (c) 2006

CSA ch 21 - p 309

CSA Ch 22
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 22 - p 310

22. CSA - The EPIC Itanium processor

L1 Icache L1 Dcache L2 L3 main memory Clock System bus CPU power

16 kbyte, 64 byte line 16 kbyte, 64 byte line, write-through 256 kbyte, 128 byte line, write-back 3-9 Mbyte, 128 byte line, write-back <1 Pbyte (264) 1.66 GHz 400 MHz, 128 bits wide 100 watts

Itanium 2 processor parameters

CSA Rob Williams Pearson Education (c) 2006

CSA ch 22 - p 311

127

97 86

46 45

5 4

Instr 2

Instr 1

Instr 0

Templ

Op Field4 Field3 Field2 Field1 pred code 40 37 36 27 26 20 19 13 12 6 5 0

Instruction Bundle for the IA-64 Architecture

CSA Rob Williams Pearson Education (c) 2006

CSA ch 22 - p 312

63 gr0 gr1 gr2

General Regs NAT 0


0

81

Floating-Point Regs + 0.0 + 1.0

63

IP

Application Regs
63

KR0 KR7 RSC BSP BSPstore RNAT FCR EFLAG CSD SSD CFLG FSR FIR FDR CCV UNAT FPSR ITC PFS LC EC

0 ar0

Predicate Flags
63 0

63 br0 gr125 gr126 gr127 br1 br2 br3 br4 37 br5 0 br6 br7

Branch Regs

CFM

ar127

Intel IA-64 / Itanium Register Set

CSA Rob Williams Pearson Education (c) 2006

CSA ch 22 - p 313

Register Gr 0 Gr1 Gr2-Gr3 Gr4-Gr7 Gr -Gr 8 11 Gr 12 Gr13 Gr14-Gr31 Gr32-Gr39 Gr32-Gr127

name r0 r1 r2-r3 r4-r7 r8-r11 r12 r13 r14-r31 r32-r39 r32-r127

title gp

ret0-ret3 sp tp in0-in7 loc0-loc95 out0-out95

class constant special scratch preserved scratch special special scratch automatic automatic automatic automatic automatic

usage reads as zero global data pointer used with addl return values stack pointer thread pointer function params input registers local registers output registers rotating registers (groups of 8)

Asm programmers usage of Itanium registers

CSA Rob Williams Pearson Education (c) 2006

CSA ch 22 - p 314

Type A I M B F X

ALU operations, arithmetic on integers and logic multimedia, integer shifts, special register ops memory load/store operations branching, jumping and returning oating-point operations special instructions

Itanium instruction classes

CSA Rob Williams Pearson Education (c) 2006

CSA ch 22 - p 315

Template 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1F

Slot0 M-unit M-unit M-unit M-unit M-unit M-unit M-unit M-unit M-unit || M-unit || M-unit M-unit M-unit M-unit M-unit M-unit M-unit M-unit B-unit B-unit M-unit M-unit M-unit M-unit M-unit

Slot1 I-unit I-unit I-unit || I-unit || L-unit L-unit M-unit M-unit M-unit M-unit F-unit F-unit M-unit M-unit I-unit I-unit B-unit B-unit B-unit B-unit M-unit M-unit F-unit F-unit I-unit

Slot2 I-unit I-unit || I-unit I-unit || X-unit X-unit || I-unit I-unit || I-unit I-unit I-unit I-unit || F-unit F-unit || B-unit B-unit || B-unit B-unit || B-unit B-unit || B-unit B-unit || B-unit B-unit || I-unit

Template eld encoding for Itanium 2, showing the positions of inter-instruction stops

CSA Rob Williams Pearson Education (c) 2006

CSA ch 22 - p 316

#include <stdio.h> /* selection_sort.c A good basic sort routine. Works by scanning up through the array finding the "smallest" item, which it then swaps with the item at the start of the scan. It then scans again, starting at the second position, looking for the next smallest item... and so on. */ int selectionsort(char *pc[ ], int n ) { int min, i, j, k; char *pctemp; for (i = 0; i < n; i++) { min = i; for(j = i+1; j < n; j++) if (strcmp(pc[j], pc[min]) > 0) min = j; pctemp = pc[min]; pc[min] = pc[i]; pc[i] = pctemp; for(k=0; k<n; k++) printf("%s ", pc[k]); printf("\n"); } return 0; }

void main() { int i; char *names[7], *testset[7] = { "Monday", "Tuesday", "Wednesday", "Thursday", "Friday", "Saturday", "Sunda for(i=0; i < 7; i++) names[i] = testset[i]; printf("\n\nSelection Sort\n"); i = selectionsort(names, 7); }

CSA Rob Williams Pearson Education (c) 2006

CSA ch 22 - p 317

.file "selection_sort.c" .pred.safe_across_calls p1-p5,p16-p63 .section .rodata .align 8 .LC0: stringz "%s " .align 8 .LC1: stringz "\n" .text .align 16 .global selectionsort# .proc selectionsort# selectionsort: .prologue 14, 34 .save ar.pfs, r35 alloc r35 = ar.pfs, 2, 4, 2, 0 .vframe r36 mov r36 = r12 adds r12 = -48, r12 mov r37 = r1 .save rp, r34 mov r34 = b0 .body ;; adds r14 = -32, r36 ;; st8 [r14] = r32 adds r14 = -24, r36 ;; st4 [r14] = r33 adds r14 = -16, r36 ;; st4 [r14] = r0 .L2: ; FOR i loop adds r14 = -16, r36 adds r15 = -24, r36 ;; ld4 r16 = [r14] ld4 r14 = [r15] ;; cmp4.gt p6, p7 = r14, r16 (p6) br.cond.dptk .L5 br .L3 ; Exit FOR i loop ;; .L5: adds r15 = -20, r36 adds r14 = -16, r36 ;; ld4 r14 = [r14] ;; st4 [r15] = r14 adds r15 = -12, r36 adds r14 = -16, r36 ; get ipntr ;; ld4 r14 = [r14] ; ;; adds r14 = 1, r14 ; incr i ;; st4 [r15] = r14 ;

; FOR j loop adds r14 = -12, r36 adds r15 = -24, r36 ;; ld4 r16 = [r14] ; get npntr ld4 r14 = [r15] ; get jpntr ;; cmp4.gt p6, p7 = r14, r16 (p6) br.cond.dptk .L9 br .L7 ; Exit j FOR loop ;; .L9: adds r14 = -12, r36 ;; ld4 r14 = [r14] ;; sxt4 r14 = r14 ;; shladd r15 = r14, 3, r0 adds r16 = -32, r36 ;; ld8 r14 = [r16] ;; add r16 = r15, r14 adds r14 = -20, r36 ;; ld4 r14 = [r14] ;; sxt4 r14 = r14 ;; shladd r15 = r14, 3, r0 adds r17 = -32, r36 ;; ld8 r14 = [r17] ;; add r14 = r15, r14 ld8 r38 = [r16] ;; ld8 r39 = [r14] br.call.sptk.many b0 = strcmp# mov r1 = r37 mov r14 = r8 ;; cmp4.ge p6, p7 = 0, r14 (p6) br.cond.dptk .L8 adds r14 = -20, r36 adds r15 = -12, r36 ;; ld4 r15 = [r15] ;; st4 [r14] = r15 .L8: adds r15 = -12, r36 adds r14 = -12, r36 ;; ld4 r14 = [r14] ;; adds r14 = 1, r14 ;; st4 [r15] = r14 br .L6 ;; .L6:

.L7: mov r16 = r36 ; get temppntr adds r14 = -20, r36 ;; ld4 r14 = [r14] ;; sxt4 r14 = r14 ;; shladd r15 = r14, 3, r0 adds r17 = -32, r36 ;; ld8 r14 = [r17] ;; add r14 = r15, r14 ;; ld8 r14 = [r14] ; ;; ; pctemp=pc[min] st8 [r16] = r14 ; adds r14 = -20, r36 ;; ld4 r14 = [r14] ;; sxt4 r14 = r14 ;; shladd r15 = r14, 3, r0 adds r16 = -32, r36 ;; ld8 r14 = [r16] ;; add r16 = r15, r14 adds r14 = -16, r36 ; get ipntr ;; ld4 r14 = [r14] ;; sxt4 r14 = r14 ; sign extend i ;; shladd r15 = r14, 3, r0; i x 8 adds r17 = -32, r36 ;; ld8 r14 = [r17] ;; add r14 = r15, r14 ; build pntr ;; ld8 r14 = [r14] ; ;; ; pc[min]=pc[i] st8 [r16] = r14 ; adds r14 = -16, r36 ; get ipntr ;; ld4 r14 = [r14] ; get i ;; sxt4 r14 = r14 ;; shladd r15 = r14, 3, r0; i x 8 adds r16 = -32, r36 ; get pc[] base ;; ld8 r14 = [r16] ;; add r15 = r15, r14 ; build pc[i] pntr mov r14 = r36 ; get pctemppntr ;; ld8 r14 = [r14] ; ;; ; pc[i]=pctemp st8 [r15] = r14 ; adds r14 = -8, r36 ; get kpntr ;; st4 [r14] = r0 ; zero k

.L11:

; FOR k loop adds r14 = -8, r36 ; get kpntr adds r15 = -24, r36 ;; ld4 r16 = [r14] ld4 r14 = [r15] ;; cmp4.gt p6, p7 = r14, r16 (p6) br.cond.dptk .L14 br .L12 ; Exit k FOR loop ;; .L14: adds r14 = -8, r36 ;; ld4 r14 = [r14] ;; sxt4 r14 = r14 ;; shladd r15 = r14, 3, r0 adds r17 = -32, r36 ;; ld8 r14 = [r17] ;; add r15 = r15, r14 addl r14 = @ltoffx(.LC0), r1 ;; ld8.mov r38 = [r14], .LC0 ld8 r39 = [r15] br.call.sptk.many b0 = printf# mov r1 = r37 adds r15 = -8, r36 ; get dest kpntr adds r14 = -8, r36 ; get src kpntr ;; ld4 r14 = [r14] ; ;; adds r14 = 1, r14 ; incr k ;; st4 [r15] = r14 ; br .L11 ;; .L12: addl r14 = @ltoffx(.LC1), r1 ;; ld8.mov r38 = [r14], .LC1 br.call.sptk.many b0 = printf# mov r1 = r37 adds r15 = -16, r36 ; get Dest ipntr adds r14 = -16, r36 ; get Src ipntr ;; ld4 r14 = [r14] ; ;; adds r14 = 1, r14 ; incr i ;; st4 [r15] = r14 ; br .L2 ; Bottom of i loop ;; .L3: mov r14 = r0 ;; mov r8 = r14 mov ar.pfs = r35 ; save FP mov b0 = r34 .restore sp mov r12 = r36 br.ret.sptk.many b0 ;; .endp selectionsort#

.text ; Code Section .align 16 .global main# .proc main# main: .prologue 14, 32 .save ar.pfs, r33 alloc r33 = ar.pfs, 0, 4, 2, 0 .vframe r34 mov r34 = r12 ; set FP from SP adds r12 = -144, r12 ; open stack frame mov r35 = r1 .save rp, r32 mov r32 = b0 ; save branch reg .body ;; adds r15 = -48, r34 ; build tablepntr addl r14 = @ltoffx(.LC2), r1; build RAM pntr ;; ; using offset+base pntr ld8.mov r14 = [r14], .LC2 ;; st8 [r15] = r14 ; save strnpntr in table adds r16 = 8, r15 :bump pntr addl r14 = @ltoffx(.LC3), r1 ;; ; "Tuesday" ld8.mov r14 = [r14], .LC3 ;; st8 [r16] = r14 ; save strnpntr in table adds r16 = 16, r15 addl r14 = @ltoffx(.LC4), r1 ;; ; "Wednesday" ld8.mov r14 = [r14], .LC4 ;; st8 [r16] = r14 ; save strnpntr in table adds r16 = 24, r15 addl r14 = @ltoffx(.LC5), r1 ;; ; "Thursday" ld8.mov r14 = [r14], .LC5 ;; st8 [r16] = r14 ; save strnpntr in table adds r16 = 32, r15 addl r14 = @ltoffx(.LC6), r1 ;; ; "Friday" ld8.mov r14 = [r14], .LC6 ;; st8 [r16] = r14 ; save strnpntr in table adds r16 = 40, r15 addl r14 = @ltoffx(.LC7), r1 ;; ; "Saturday" ld8.mov r14 = [r14], .LC7 ;; st8 [r16] = r14 ; save strnpntr in table adds r15 = 48, r15 addl r14 = @ltoffx(.LC8), r1 ;; ld8.mov r14 = [r14], .LC8 ;; ; "Sunday" st8 [r15] = r14 ; save strnpntr in table adds r14 = -128, r34 ; build ipntr ;; st4 [r14] = r0 ; clear i

; star t of FOR i loop adds r15 = -128, r34 ;; ; names[]=testset[] ld4 r14 = [r15] ; get i ;; cmp4.ge p6, p7 = 6, r14 (p6) br.cond.dptk .L19 ; test end of FOR loo br .L17 ;; .L19: adds r15 = -112, r34; get Destpntr adds r16 = -128, r34 ; get ipntr ;; ; local variables ld4 r14 = [r16] ; get i ;; sxt4 r14 = r14 ; sign extend ;; shladd r14 = r14, 3, r0; i x 8 ;; add r16 = r14, r15 ; index Destpntr adds r15 = -48, r34 ; get Srcpntr adds r17 = -128, r34 ; get ipntr ;; ld4 r14 = [r17] ; get i ;; sxt4 r14 = r14 ; sign extend ;; shladd r14 = r14, 3, r0:ix8 ;; add r14 = r14, r15 ; index Srcpntr ;; ld8 r14 = [r14] ; | get next_word ;; :| st8 [r16] = r14 ; | put next_word adds r15 = -128, r34 ; get ipntr ;; ld4 r14 = [r15] ; get i ;; adds r14 = 1, r14 ; incr i adds r16 = -128, r34 ; get ipntr ;; st4 [r16] = r14 ; save i br .L16 ; bottom of FOR ;; .L17: addl r14 = @ltoffx(.LC9), r1 ;; ld8.mov r36 = [r14],.LC9; print banner br.call.sptk.many b0 = printf# mov r1 = r35 ; return value adds r14 = -112, r34 ; get Destpntr ;; mov r36 = r14 ; param1=Destpntr addl r37 = 7, r0 ; param2=7 br.call.sptk.many b0 = selectionsort# ; c mov r1 = r35 ; get return value mov r14 = r8 adds r17 = -128, r34 ; get ipntr ;; st4 [r17] = r14 ; store in i mov ar.pfs = r33 mov b0 = r32 ; restore branch addr .restore sp mov r12 = r34 ; restore SP br.ret.sptk.many b0 RETURN to shell ;; .endp main# .ident "GCC: (GNU) 3.3.5 (Debian 1:3.3. .L16:

.section .align 8 .LC2: .align 8 .LC3: .align 8 .LC4: .align 8 .LC5: .align 8 .LC6: .align 8 .LC7: .align 8 .LC8: .align 8 .LC9:

.rodata

; Constants Section stringz stringz stringz stringz stringz stringz stringz stringz "Monday"; constant strings store "Tuesday" "Wednesday" "Thursday" "Friday" "Saturday" "Sunday" "\n\nSelection Sort\n"

Itanium assembler code produced by gcc

Call stack window

Browser window

Registers window

Source code window

Disassembler window

gdb window

Linux-64 with gvd/gdb debugger to watch Itanium code


CSA Rob Williams Pearson Education (c) 2006

CSA ch 22 - p 322

CSA Ch 23
CSA Computers Fetch-execute cycle Hardware CPU Arithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Serial communication Networking Local Area Networks Ethernet USB Wide Area Networks Other Networks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

CSA Rob Williams Pearson Education (c) 2006

CSA ch 23 - p 323

23. CSA - Parallel Processing

Program has N instructions Instructions take secs each to complete Uni-processor run time will be N x IDEALLY, P processors could reduce run time to (N )/P But only a fraction of real application code can be parallelized:

total _time = serial _part + parallel _part = N f +

N (1 f ) P

While f is the fraction of the problem that must be carried out sequentially due to data or control dependencies, (1 f ) is the fraction which can run in parallel. Note that f + (1 f ) evaluates to 1. P is the number of processors available. The speed-up-ratio is then dened as the uni-processor-time divided by the (smaller!) multi-processor-time, which is:

speed _up_ratio: S =

N 1 = N (1 f ) f + (1 f )/P N f + P

Parallelizable code, Amdahls Law

CSA Rob Williams Pearson Education (c) 2006

CSA ch 23 - p 324

fraction parallel code, (1-f ) x6


0.9

x5 S, speed-up ratio

x4

0.8

x3

0.7

x2

0.5 0.3 0.1

x1 2 4 6 8 10 12 14

P , number of CPUs

Amdahls Law plotted for 1-15 processors and 0.1 - 0.9 compliant code

CSA Rob Williams Pearson Education (c) 2006

CSA ch 23 - p 325

SISD SIMD MISD MIMD

Instruction stream Single Single Multiple Multiple

Data stream Single Multiple Single Multiple

Personal PC Vector processors Possibly none. Central server

word processing geological simulation WWW search engine

Flynns processor taxonomy


local memor y local memory local memory

CPU1

CPU2

CPU3

CPU1
cache

CPU2
cache

CPU3
cache

CPU1
cache

CPU2
cache

CPU3
cache

System bus shared memory


data

copies memory shared memor y

Single bus, shared memory multi-processing (SMP)


Cache event Read Hit Miss Hit Miss Action cache read main memor y read cache update main memor y write cache marked stale main memor y write

Write

Cache coherency protocol with write-through

CSA Rob Williams Pearson Education (c) 2006

CSA ch 23 - p 326

local memor y

local memory

local memor y

CPU1
cache

CPU2
cache

CPU3
cache

CPU5
cache

CPU4
cache

CPU6
cache

local memor y

local memory

local memor y

Hardware conguration for an MPI system


int MPI_Send( void* sendBuf, int count, MPI_Datatype datatype, int destinationRank, int tag, MPI_Comm comm) int MPI_Recv( void* recvBuf, int count, MPI_Datatype datatype, int sourceRank, int tag, MPI_Comm comm, MPI_Status *status) int MPI_Bcast ( void* buffer, int count, MPI_Datatype datatype, int root, MPI_Comm comm )

CSA Rob Williams Pearson Education (c) 2006

CSA ch 23 - p 327

Storage Logic

256 kbyte

Local storage

I-fetch

Control Logic

Decode Dispatch

Front end

Execution Logic

BU

SCU

L/SU

Vperm

SPU1

SPU2

Byte

FX1

FX2

Vector arithmetic units

R-commit

Control unit

The IBM/Sony Cell SPE unit

CSA Rob Williams Pearson Education (c) 2006

CSA ch 23 - p 328

64 bit PowerPC 32 kB L1 512 kB L2

SPE 7

SPE 3

SPE 6

SPE 2

SPE 5

SPE 1

SPE 4

SPE 0

MIC 2x XDR

BIC FlexIO

Cell schematic architecture

workstations Switching Hub

A single switched hub Cluster with Star topology

CSA Rob Williams Pearson Education (c) 2006

CSA ch 23 - p 329

workstations

Internet

Application originator

Grid computing

CSA Rob Williams Pearson Education (c) 2006

CSA ch 23 - p 330

5 /1/07 Fri Jan 5 00:09:48 GMT 2007 localhost

CSA Rob Williams Pearson Education (c) 2006

CSA ch 23 - p 331