ISA 6

LOAD STORE ARCHITECTURE

ISA 6 - Load Store

Ab br eviatio ns
Carry Flag Over-flow flag Sign Flag Zero Flag Parity Flag Instruction Pointer CF OF SF ZF PF IP

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ISA 6 - Load Store

Ins tru ction format

General Instruction format

5-bit Opcode 47

3-bit Addressing Mode 43 42 40 39

19-bit operand

Operand 2 36 25 21 19 5

Operand 1 1 0

Operand addressing modes and notations

000 100 101 010 110 111

Immediate Direct Indirect register Direct Register Indirect Index

# default & $ ! @

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ISA 6 - Load Store

Ins tru ction Set Su mmar y

Arithmetic instructions....................................................................... 5
ADD SUB MUL DIV INC Addition................................................................................................... 5 Subtraction............................................................................................... 5 Signed multiplication............................................................................... 6 Signed division ........................................................................................ 6 Increment a register by 1 ......................................................................... 7

Logical instructions............................................................................ 7
AND OR XOR SHL SHR ROL ROR NOT Bit-wise And............................................................................................ 7 Bit-wise OR ............................................................................................. 8 Bit-wise XOR .......................................................................................... 8 Shift a register left 1-bit........................................................................... 9 Shift a register right 1-bit......................................................................... 9 rotate a register left 1-bit........................................................................ 10 rotate a register right 1-bit ..................................................................... 11 Ones compliment negation ................................................................... 11

Control Transfer................................................................................ 12 Conditional Branches....................................................................... 12

JC JOF JS JP JZ Jump if carry (CF = 1) ........................................................................... 12 Jump if an over-flow (OF = 1)............................................................... 12 Jump if Sign (SF = 1) ............................................................................ 13 Jump if parity (PF = 1)........................................................................... 13 Jump if result is zero (ZF =0) ................................................................ 14

Unconditional branch ....................................................................... 14

JUMP Jump ...................................................................................................... 14

Loop Instructions.............................................................................. 15
LOOZ Loop until zero....................................................................................... 15

Calls and Returns ............................................................................. 16

CALL Call procedure ....................................................................................... 16 RETURN Return from procedure ..................................................................... 16

Miscellaneous instructions.............................................................. 17
NOP No operation .......................................................................................... 17

Data Movement instructions............................................................ 18

LOAD STORE .......................................................................................................... 18 .......................................................................................................... 19

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ISA 6 - Load Store

Ins tru ction s et r ef er en ce

Arithmetic instructions

ADD
Opcode Format Description

Addition
10000 ADD Register operand1, Register operand2 Adds two registers. Result modifies Operand1. ADD instruction performs integer addition. It evaluates the results for both signed and unsigned integer operands and sets the CF and OF flags to indicate a carry in the signed or unsigned result, respectively. The SF indicates the sign of the signed result. operand1 operand1+ operand2 Immediate and register direct ZF, OF, SF and PF are set according to the result.

Operation AMs Flags affected

SUB
Opcode Format Description

Subtraction
10001 SUB Register operand1, Register operand2 Subtracts the register 2 from register 1. Result modifies the Register1. SUB instruction performs integer subtraction. It evaluates the results for both signed and unsigned integer operands and sets the CF and OF to indicate a carry in the signed or unsigned result, respectively. The SF indicates the sign of the signed result. operand1 operand1 operand2 Immediate and register direct ZF, OF, SF, CF and PF are set according to the result.

Operation AMs Flags affected

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ISA 6 - Load Store

MUL
Opcode Format Description

Signed multiplication
11011 MUL operand1 (8-bit), operand2 (8-bit) Performs signed multiplication on lower 8-bits of operand 1 and operand 2. Mul instruction produces a 16bit result. Both operand 1 and operand 2 are registers. operand1 (16-bit) operand1 * operand2 (8 LSBs) (8 LSBs)

Operation

AMs Flags affected

Immediate and register direct ZF, SF and PF are set according the product. OF and CF is cleared, as no overflow occurs in this situation and no carry considered.

DIV
Opcode Format Description

Signed division
11100 DIV operand1, operand2 Divides operand 1 by operand2. Div instruction produces an integer output. Both operand 1 and operand 2 are registers. operand 1 operand 1 / operand 2 Immediate and register direct ZF, SF and PF are set according the product. OF and CF is cleared, as no overflow occurs in this situation and no carry considered.

Operation AMs Flags affected

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ISA 6 - Load Store

INC
Opcode Format Description

Increment a register by 1
10101 INC operand Adds 1 to the register specified. Evaluates for both signed and unsigned operands. operand operand +1 Implied register direct the CF is not affected. The OF, SF, ZF and PF are set according to the result.

Operation AMs Flags affected

Logical instructions

AND
Opcode Format Description

Bit-wise And
10010 AND operand1, operand1 Performs bit wise AND operation on o the specified two registers, operand 1 and operand2. Each bit of the result is set to 1 if both corresponding bits of the operands are 1; otherwise, it is set to 0. Result replaces the operand 1. operand1 operand1 AND operand2 Implied register direct OF and CF are cleared; SF, ZF and PF are set according to the result.

Operation AMs Flags affected

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ISA 6 - Load Store

OR
Opcode Format Description

Bit-wise OR
10011 OR operand1, operand2 Performs bit wise OR operation on the specified two registers, operand 1 and operand 2. Each bit of the result is set to 0 if both corresponding bits of the operands are 0; otherwise, it is set to 1. Result replaces the register specified as operand 1. operand1 operand1 OR operand2 Immediate or register direct OF and CF are cleared; SF, ZF and PF are set according to the result.

Operation AMs Flags affected

XOR
Opcode Format Description

Bit-wise XOR
10100 XOR operand1, operand2 Performs bit wise XOR operation on the specified registers, operand 1 and operand 2. Each bit of the result is set to 0 if both corresponding bits of the operands are 1 or if both corresponding bits of the operands are 0; otherwise, it is set to 1. Result replaces the register specified as operand 1. operand1 operand1 XOR operand2 Immediate or register direct OF and CF are cleared; SF, ZF and PF are set according to the result.

Operation AMs Flags affected

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ISA 6 - Load Store

SHL
Opcode Format Description

Shift a register left 1-bit

10111 SHL operand Shifts the bits in the register (operand) to the left by one bit. Bits beyond the boundary are first shifted in to the CF. At the end of the shift operation CF contains the MSB of register operand. Least significant bit is cleared. operand operand (MSB-1 down to 0) & 0 CF MSB (original operand) Implied register direct The CF contains the value of the bit shifted out of the operand. OF is set to zero if the value of the MSB of the operand is same as the CF; otherwise it is set to 1. SF, ZF and PF are set according to the result.

Operation

AMs Flags affected

SHR
Opcode Format Description

Shift a register right 1-bit

01010 SHR operand Shifts the bits in the register (operand) to the right by one bit. Bits beyond the boundary are first shifted in to the CF. At the end of the shift operation CF contains the LSB of the operand. Most significant bit is cleared. operand 0 & operand (MSB down to 1) CF LSB (operand) Implied register direct The CF contains the value of the bit shifted out of the operand. OF is set to the MSB of the original operand. SF, ZF and PF are set according to the result.

Operation

AMs Flags affected

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ISA 6 - Load Store

ROL
Opcode Format Description

rotate a register left 1-bit

11001 ROL operand shifts (rotates) the bits of the register (operand) left by 1 bit. Instruction includes the CF in the rotation, first shifts the CF into the LSB. And shifts the MSB to the CF. The original value of the CF are not a part of the result, but the CF receives a copy of the bit that was shifted from one end to the other end. OF is set to the exclusive OR of the CF (after the rotate) and the MSB of the result. tempCF MSB (operand) Operand operand (msb-1 down to 0) & CF CF tempCF OF MSB (operand) XOR CF (after the rotation) Implied register direct The CF contains the value of the bit shifted out of the operand frame. OF is set to the exclusive OR of the CF (after the rotate) and the MSB of the result. SF, ZF and PF are set according to the result.

Operation

AMs Flags affected

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ISA 6 - Load Store

ROR
Opcode Format Description

rotate a register right 1-bit

11010 ROR operand shifts (rotates) the bits of the register specified to right by 1 bit. Instruction includes the CF in the rotation, first shifts the CF into the MSB and shifts the LSB to the CF. The original value of the CF is not a part of the result, but the CF receives a copy of the bit that was shifted from one end to the other end. OF is set to the exclusive OR of the two most significant bits of the operand. tempCF LSB (operand) MSB (operand) CF CF tempCF OF MSB (operand) XOR CF Implied register direct The CF contains the value of the bit shifted into it. OF is set to the exclusive-OR of the two most significant bits of the Acc. SF, ZF and PF are set according to the result.

Operation

AMs Flags affected

NOT
Opcode Format Description

Ones compliment negation

10110 NOT operand Performs bit-wise NOT operation (each 1 is set to 0, and each 0 is set to 1) on the register specified (operand), and stores the result in it. operand NOT operand Implied register direct none

Operation AMs Flags affected

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ISA 6 - Load Store

Control Transfer Conditional Branches

JC
Opcode Format Description

Jump if carry (CF = 1)

00001 JC {Signed offset (IP relative)} Check the state of the CF in the PSW (Programmers Status Word register) and, if the flag is set, performs a jump to the target instruction specified by the operand. If the condition is not satisfied, the jump is not performed and execution continues with the instruction following the JC instruction. The target instruction is specified with a relative offset (a signed offset relative to the current value of the IP register). Machine code level the offset is encoded as a signed immediate value, which is added to the IP. IP IP + Operand IP relative addressing is applied in the address calculation. none

Operation AM Flags affected

JOF
Opcode Format Description

Jump if an over-flow (OF = 1)

00010 JOF {Signed offset (IP relative)} Check the state of the OF in the PSW (Programmers Status Word register) and, if the flag is set, performs a jump to the target instruction specified by the operand. If the condition is not satisfied, the jump is not performed and execution continues with the instruction following the JOF instruction.

Operation AM Flags affected

IP IP + Operand IP relative addressing is applied in the address calculation. none

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ISA 6 - Load Store

JS
Opcode Format Description

Jump if Sign (SF = 1)

00011 JS {Signed offset (IP relative)} Check the state of the SF in the PSW (Programmers Status Word register) and, if the flag is set, performs a jump to the target instruction specified by the operand. If the condition is not satisfied, the jump is not performed and execution continues with the instruction following the JS instruction IP IP + Operand IP relative addressing is applied in the address calculation. none

Operation AM

Flags affected

JP
Opcode Format Description

Jump if parity (PF = 1)

00100 JP {Signed offset (IP relative)} Check the state of the PF in the PSW (Programmers Status Word register) and, if the flag is set, performs a jump to the target instruction specified by the operand. If the condition is not satisfied, the jump is not performed and execution continues with the instruction following the JP instruction IP IP + Operand IP relative addressing is applied in the address calculation. none

Operation AM Flags affected

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ISA 6 - Load Store

JZ
Opcode Format Description

Jump if result is zero (ZF =0)

00101 JZ {Signed offset (IP relative)} Check the state of the ZF (Programmers Status Word register) and, if set, performs a jump to the target instruction specified by the operand. If the condition is not satisfied, the jump is not performed and execution continues with the instruction following the JZ instruction IP IP + Operand IP relative addressing is applied in the address calculation. none

Operation AM

Flags affected

Unconditional branch

JUMP
Opcode Format

Jump
01111 JUMP {Signed offset (IP relative)}

Description

Transfers the program control to a different point of the instruction stream. The operand specified the signed offset being jumped to. This operand is an immediate signed offset.
IP IP + operand IP relative addressing is applied in the address calculation. none

Operation AM Flags affected

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ISA 6 - Load Store

Loop Instructions

LOOZ
Opcode Format Description

Loop until zero

01000 LOOZ {Signed offset (IP relative)} Performs a loop operation using an implied register as a counter. Each time the LOOZ instruction executes, the counter rregister is decremented, then checked for 0. If the count =0, the loop terminates and the program execution continues with the instruction following the LOOZ instruction. If the count is not 0, a jump is performed to the specified operand, (a signed offset is specified in the instruction) which is presumably the instruction at the beginning of the loop. The decremented counter value is written back to implied register whenever it is nor zero. 31st register of the register bank is reserved as the counter.

Operation

Count Count 1 IF Count =0 Loop termination ELSE IP IP + operand END IF IP relative addressing is applied in the address calculation. none

AM

Flags affected

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ISA 6 - Load Store

Calls and Returns

CALL
Opcode Format Description

Call procedure
01010 CALL {Immediate address} Saves IP in the implied register and branches to the procedure (called procedure) specified by the operand. This operand is an immediate value. When executing a CALL, the processor pushes the value of the IP register on to the implied register (For use latter as a returninstruction pointer). The processor then branches to the address specified with instruction. 29th register of the register bank is reserved to hold the return address.

Operation

implied register (29th register) IP IP IP + Operand Immediate operand is used as the jumping location none

AM Flags affected

RETURN
Opcode Format Description

Return from procedure

01011 RET Transfers program control to the return address specified in the implied register. Return is made to the instruction that follows the CALL instruction. IP implied return address Contents of the implied return register is used as the jumping location none

Operation AM Flags affected

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ISA 6 - Load Store

Miscellaneous instructions

NOP
Opcode Format Description Flags affected

No operation
01110 NOP Performs no operation. Takes up space in the instruction stream but does not affect the context, except IP. none

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ISA 6 - Load Store

Data Movement instructions

LOAD
Opcode Format Description 01100 LOAD AM operand1, operand2 Immediate Addressing Copy the 16-bit immediate source operand (operand 2) to the destination register (operand 1). Direct Addressing Copy the contents of the source (operand2) address (of memory) to the destination register (operand1). Register Indirect Addressing Memory address is found by accessing the register bank for the source register (operand 2). Content of the memory location is copied to the destination register (operand 1). Indexed Addressing Base register (operand 2) and the implied index register is added to make the address of the source operand. Contents of the memory address then copied to the destination register (operand 1). 30th of the register bank is the implied Index register Operation Immediate Addressing
Register bank (operand 1) 16-bit immediate Operand 2

Direct Addressing
Register bank (operand 1) memory (operand 2)

Register Indirect Addressing

Register bank memory {register bank (operand2)} (Operand 1)

Indexed Addressing
Register bank memory {register bank (operand2) + register bank (implied Index register)}

AMs Flags affected

Immediate, direct, Register Indirect and Indexed none

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ISA 6 - Load Store

STORE
Opcode Format Description 01101 STORE AM operand1, operand2 Direct Addressing Copy the contents of the source register (operand2) to the destination memory address (operand1). Indirect Addressing Copy the contents of the source register (operand2) to the destination memory address found at operand1 in memory. Register Direct Addressing Copy the contents of the source register (operand2) to the destination register (operand 1). Register Indirect Addressing Copy the contents of the source register (operand2) to the destination memory address found by accessing the register bank (operand 1). Indexed Addressing Base register (operand 2) and the implied index register are added to make the destination memory address. Contents of the memory address then copied to the destination register (operand 1). 30th of the register bank is the implied Index register Operation Direct Addressing
Register bank (operand 1) memory (operand 2)

Indirect Addressing
Register bank (operand 1) memory {memory (operand2)}

Register Direct Addressing

Register bank (Operand 1) register bank (operand2)

Register indirect Addressing

Register bank memory {register bank (operand2)} (Operand 1)

Indexed Addressing
Register bank memory {register bank (operand2) + (operand1) register bank (implied Index register)}

AMs Flags affected

Direct, indirect, register direct, register Indirect and Indexed none

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