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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
BASIC PROCESSING UNIT
Control Unit has two major Iunctions:
To control the sequencing oI inIormation-processing tasks
perIormed by machine
Guiding and supervising each unit to make sure that each
unit carries out every operation assigned at the proper time
Control oI a computer can be distributed or centralized
Early computers used distributed control and a lot oI
redundant hardware
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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
PROCESSING UNIT FEATURES
Execution of a Complete Instruction
Add (R3), R1 /* R1 |R1| ||R3||
Adds the contents oI a memory location pointed to by R3 to
register R1.
Sequence oI control steps:
1. PCout, MARin, Read, Select4, Add, Zin
2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. R3out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, SelectY, Add, Zin
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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
7. Zout, R1in, End
Multiple bus architecture
Single-bus structure: Control sequences are long as only one data item
can be transIerred over the bus in a clock cycle.
Figure on next slide shows a three-bus structure.
All registers are combined into a single block called register Iile with
three ports: 2 outputs allowing 2 registers to be accessed
simultaneously and have their contents put on buses A and B, and 1
input allowing data on bus C to be loaded into a third register.
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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
Buses A and B are used to transIer source operands to the A and B
inputs oI ALU, and result transIerred to destination over bus C.
For the ALU, RA (or RB) means that its A (or B) input is
passed unmodified to bus C.
Add R4, R5, R6 /` R6 R4] + R5]
Adds the contents of R4 and R5 to R6.
Sequence of control steps:
PCout, RB, MARin, Read, IncPC
WMFC
MDRoutB, RB, IRin
R4outA, R5outB, SelectA, Add, R6in, End
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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
Hardwired control
The control logic is implemented with gates, F/Fs, decoders, and
other digital circuits
To execute instructions, a computer's processor must generate the
control signals used to perIorm the processor's actions in the proper
sequence. This sequence oI actions can either be executed by another
processor's soItware or in hardware.
Hardware signals are generated either by hardwired control, in
which the instruction bits directly generate the signals
hardwired control usually was implemented using discrete
components, flip-chips, or even rotating discs or drums. This can be
generally done by two methods.
The classical method oI sequential circuit design. It attempts to
minimize theamount oI hardwire, in particular, by using only log
2
p
Ilip Ilops to realize a p state circuit.
An approach that uses one Ilip Ilop per state. While expensive in
terms oI Ilip Ilops, this method simpliIies controller unit design and
debuggi
Combinational logic
Determine outputs at each state.
Determine next state.
Storage elements
Maintain state representation
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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
Hardwired Implementation
The Cycles (Fetch, Indirect, Execute, Interrupt) are
constructed as a State Machine
The Individual instruction executions can be constructed
as State Machines
State Machine
Combinational
Logic Circuit
Storage
Elements
nputs Outputs
Clock
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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
Common sections can be shared. There is a lot of
similarity
One ALU is implemented. All instructions share it
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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
Microprogrammed control
A control unit whose binary control variables are stored in memory
(control memory).
The Control Memory contains sequences oI microinstructions that provide
the control signals to execute instruction cycles, e.g. Fetch, Indirect,
Execute, and Interrupt
Microinstruction : Control Wora in Control Memory
The microinstruction speciIies one or more microoperations
Microprogram
A sequence oI microinstruction
Dynamic microprogramming : Control Memory
RAM
n RAM can be used Ior writing (to change a
writable control memory)
n Microprogram is loaded initially Irom an
auxiliary memory such as a magnetic disk
Static microprogramming : Control Memory
ROM
n Control words in ROM are made permanent
during the hardware production.
Microprogrammed control Organization :
1) Control Memory
A memory is part oI a control unit : Microprogram
Computer Memory (employs a microprogrammea
control unit)
--Main Memory : Ior storing user program
(Machine instruction/aata)
--Control Memory : Ior storing microprogram
(Microinstruction)
2) Control Address Register
SpeciIy the address oI the microinstruction
3) Sequencer ( Next Aaaress Generator)
Determine the address sequence that is read Irom
control memory
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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
Next address oI the next microinstruction can be
speciIied several way depending on the sequencer
input : 4) Control Data Register ( Pipeline
Register )
Hold the microinstruction read Irom control
memory
Allows the execution oI the microoperations
speciIied by the control word simultaneously with
the generation oI the next microinstruction
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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
Microprogrammed control
--Typical Microinstruction Formats
--Micro-instruction Types
Each micro-instruction speciIies single (or Iew) micro-operations to
be perIormed
(vertical micro-programming)
Each micro-instruction speciIies many diIIerent micro-operations to
be perIormed in parallel
(hori:ontal micro-programming)
Vertical Micro-programming
Width is narrow
n control signals encoded into log2 n bits
Limited ability to express parallelism
Considerable encoding oI control inIormation requires external
memory word decoder to identiIy the exact control line being
manipulated
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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
Horizontal Micro-programming
Wide memory word
High degree oI parallel operations possible
Little encoding oI control inIormation
Micro-instruction Address
Function Codes
1ump
Condition
Internal CPU Control Signals
Micro-instruction Address
1ump Condition System Bus
Control Signals
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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
Nanoprogramming

Use a 2-level control storage organization

Top level is a vertical Iormat memory
Output oI the top level memory drives the address register oI the bottom
(nano-level) memory
Nanomemory uses the horizontal Iormat
Produces the actual control signal outputs
The advantage to this approach is signiIicant saving in control memory
si:e (bits)
Disadvantage is more complexity and slower operation (doing 2 memory
accesses Iro each microinstruction)

Example: Supppose that a system is being designed with 200 control

points and 2048 microinstructions
Assume that only 256 diIIerent combinations oI control points are ever
used
A single-level control memory would require 2048x200409,600 storage
bits
A nano programmed system would use
Microstore oI size 2048x816k
Nanostore oI size 256x20051200
Total size 67,584 storage bits
Nano programming has been used in many CISC microprocessors
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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
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Lecture plan
Code & name oI subject: 141403 computer organization and architecture
Unit no: 2
Nano programmed machine
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