The B0BBand 8086

Microprocessors and TheirMemoryand fnput/OutputInterfaces

INTRODUCTION
fiom the Up to thispointin thebook,we havestudied 8088and8086microprocessors a pointof view.We havecovered instruction how theirsoftware architectufe, set, software programs assenbly in language, foundthatthe8088and and to wdte,execute, debug and point of view.This is no! lrue of the hardware from the software 8086were identical Now we beginexamining the architectures the8088and8086microcomputer of systems. we 8088 and 8086nicrocomputel from the hardwarcpoint of view In this chapter, cover the 8088/8086\ signal interfaces,memory interfaoes,inputoutput interfaces,and bus and aspects these of cycles. The chapters fbllow coverotherhardware intedacing that This includes followingtopics: the Focessors. chapter 8.1 8088and8086Microprocessors and Systems 8.2 Minirnum-Mode Ma.{imum-Mode Interface Signals 8.3 Min;rnum-Mode 8.4 Maxinum Mode InterfaceSignals 8.5 Elecirical Characteristics 8.6 System Clock 8.7 Bus CycleandTime States 8.8 Hadware organizarionof ihe Memory Addres$Space Bus Codes 8.9 Address Status

3t5

8.10 Memory Control Signals 8-11 ReadandWrite Bus Cycles 8-12 Memory InterfaceCircuiis 8.13 Programmable Logic Arrays 8.14 Typesof Input/Output 8.15 IsolatedInput/Outputlnterface 8.16 Input/OutputData Transfers 8.17 lnput/Ou.putInstructions Bus 8.18 Input/Ouiput Cycles

a 8.1 8088 AND 8086 MTCROPROCESSORS

Tte 8086, amounced in 1978, was tLe filst 16-bit miqoprocessorintroducedby Intel Corporation.A secondmemberof rhe 8086 family, fte 8088 midoprocessor followed it in 1979.The 8088 is tuny softwarecompatiblewilh its predecessorthe 8086. The differencebetweenthesetwo devicesis in their hardwarearch;tecture. like the 8086.the Just 8088is intemally a lGbit MPU. However,extemally the 8086 hasa 16-bit databus, and the 8088 hasan 8-bit databus.This is the key hardwareditrerence.Both deviceshave.he ability 1oaddress to lMb)te of nemory via their 20-bit addrcss up buses. Moreover they can address to 64K of b'te-wide irput/output ports. up The 8088 and 8086 are borh manufactued ]usittqhish-petomance metul oide semiconductor(HMOS) technolog), and the circuitry on their chips is equivalent to apFoximately 29,0,mtransistors. They arc housedin a 40 pin dual in line package. This package be mountedinto a socketthat is soldered the circuit boardor haveits leads can to inserteddrough hole.s the board and soldered. in The signalspinnedoui to eachlead arc shownin Figs. 8-1(a) and (b), respectively. Many of iheir pins have multiple funclions. For example,in lhe pin layout diagrarnof the 8088, we see thal addressbus lines A0 drough A? and databus lines Do throughD7 are multiplexed.For this rcason,theseleads arelabeledADo throughAD?. By nubiplered we meanthat the samephysicalpin canies an addftss bit at one time and the databit at anothertime.

EMMPLE8.I
At what pin location on the 8088's packageis address A16 output?With what other bit signal is it multiplexed?What tunction dosthis pin serveon the 8086?

Solution
Looking at Fig. 8-1(a), we find that the signal,t16 is l()catedat pin 38 on the 8088 and that it is multiplexed wirh signal L. Fipre 8 1(b) showsus that pin 38 servesthe same functions on the 8086.

335

Thea08a and aO86Microprocessors Chao.I

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8,2 MINIMUM-MODE AND I\,4AXIMUM-MODE SYSTEMS
Tle 8088and 8086nicroproces ,fiorscan I

lf*i;i.trilT',ffi t* iTfr :tfrHfi,l'd,ils!.; j:ifli,:H# [",;]fi #iif *5':ffi ll_it','i,!'_fpil$ n:[,n *l#";*'x": i;run**: :;i#m ffi
sec.8.2 Mjnimum-Mode ci Maximum an Mooesystems

337

The signalsof the 8088 microprocesr;or commonto both modesof operation,those unique minimurn Lo modednddrose uniquI to maximummode,are lisLcdnr Figs. 8 2(a). (b), xnd (c). respctively. we lind the name,tunclion, and type lor each signal.For Hefe the g example, signal is in ihe common roup. lt tunctions as a rcxd control ouiput and RD is usedlo signal memory I/O devices 1enthe 8088'ssystem is setup to readin or wl bus data. Moreover, note that the signals ho ld reqnest (HOLD) and hold achowledge (HLDA) a.re producedonly in the minimun r-modesystern- the 8088 is set up for marIf imum mode,they arc replacedby the reque svgrant bus access control lines RQ/GToand RQ/GT,.

Mlnim0m mod. riqnalr(MN/MX= Ve)

HOLD

wnIO/M DT/FDEN

sso
INT'A MN/MX FD

l\raximum mode siqnah(MN/fit= GNo)

NMI

LOCK

sr-so
+5V
GND

os1, oso

Fieure 8-2 (a) Signalscormo! ro borh min inun and narinum modcs. Unique (b) minlnum-mode siendls(c) Ulique maximunj

334

The 808 rg and 8086 Microprocessors Chap. I

EMMPLE8.2
Which pins provide ditrerentsignalfunctionsin the minimun-mode 8088and rninimunnode 8086?

Solution
Conparingthe pin layouts ofthe 8088and8086in Fig. 8-i, we find thefbllowing: 1. Pins 2 ihrough 8 on the 8088 are address lines Ara tbroughAs, but on the 8086 they are address/dala lines ADia throughADs. 2. Pin 28 on rhe8088i' lhe lO,M ourpu,andon $e 8080iri5 lhe M,4-0 ourpur. cupplie. BHE/\? 3. Pin 31 of rhe8088rs $e SSOouFur.aodon lhe 808brhicpin rhe output.

A 8.3 MINIMUM-MODEINTERFACE SIGNATS

When minimum modeoperationis selectd, 8088 or 8086 itself plovides a[ rhe con, the aol signalsneded implementthe memory and I/O interfaces.Fignres 8-3(a) and (b) to show block diagramsof a minimum-modeconfigurationof the 8088 and 8086, respctively. The minimum-mode signals can be divided into the following basic groups: address/data status,control. intenupt, and DMA. bus,

Address/Data Bus
Let us first look at the address/data In an 8088-based bus. microcomputersysten, theselines sene two turctions. As n adnrcssbus, they are usedto carry address infor nation to the memory and l/O ports. The addrcss is 20 bits long and consistsof sigbus nal lines A0 tbroush Are. Of ihese.Are represents MSB and A{r the l-SB. A 20-bit the givesthe 8088 a lMbyte memory address address space.However.only address Lines A0 yO throughAr5 are usedwhen accessing I/O. This givesthe 8088 an independent address spacethat is 64Kbytesin length. The eight ddta ,rr lines D0 though D? are actually multipiexedwith address lines A0 tbroughA7, respectivell For this reason.they are denotedasADo tlrough AD7. Data LineD7 is the MSB in the byte of data and D0 the LSB. Wben acting as a databus, rhey carry readwrite data for memory input/output data for l/O devices,and interrupttype codesfrom an interruptcontroller Lookine at Fig. 8-3(b), we seethat the 8086 has 16 databus lines insreadof 8 as in the 8088.Data fines aft rnultiplexedwith address lines Ao tbroughAr5 and aft theretore denotedasADo throughADr5.

5ec. 8.3

Minimum-ModelnterfaceSignals

339

ADo-AD?. A16/S3-Ao/sa !trTA TEST

REST IO/M HOLD RO

wBDEN

CLK

INTR ifTA

aD o-AD,r.A 6/S!-A,r/36

NMI

AIE
RESET

BnE/S? M/Io Dl/R RD WR DEN

DMA

HOLD

cL( (b) I'tgue E-3 (a) Block diagrm of the minimum'mode 8088 MPU (b) Btock diagran of the mininum-mode 8086MPU

s4

5l 0

AlrgrnareG6rariv. ES rorhe se!men0 srackterarive rness s.qm.o b

Cod.lNonelrelalivslo lhe CS seg menr or a del.rrr ol zro) DalatGlalive lh os segm ) to

FigurEE-4 Addre$ bussiarur (Repiintd pernission codas. wilh of I el Corporaliotr, 1979) @

Status Signals
The foul most significantaddress lines,Are drough A16of both the 8088 atrd8086 are also multiplexed,but in lhis casewilh stdt r stgrals 56 through53. Thesestaos bits are output on the bus at the sametime thal dataare hansfered over the other bus lines. Bits Saand Sr togetherform a 2 bit binary codethat identifieswhich of the intemal segment registerswas usedto geneBtethe physical address that was output on the addrcss bus during the cunent bus 'Jycle.The,se four codesand the regisren they representare = shownin Fig. 8-4. Note that the code SaS3 00 idenrifieslhe extra segment rcgister as the sourceof ihe segment addrcss. internalchrmcteristicof the MPU- It is the Stalusline Sj rcflectsthe statusof another flag.The status 56is alwaysat the0 logic level. logic levelof theintemalintempt enable bir

Control Signals
T\e contml siqnals arc ltrovided to suppod the memory and I/O interfacesof the 8088 and 8086. They control functions such as when the bus carries a valid addrcss, which direcdon data are transferredover lhe bus. when valid write data are on the bus. andwhen to put readdataon the systembus.For example.addrcsslatch etnble (ALE\ is a pulse to iogic 1 that siglals extemalcircuitry when a valid addrcssis on the bus. This address be latchedin extemrl circlitry on the I to 0 edgeofthe pulse at ALE. _ can Using the IO/M (lo/nenoO line. D' R (data transmit/receiye\line, and SSO (statusoutput) line, the 8088 signalswhich type of bus cycle is in progressand in which directiondataare to be tsansfened overthe bus.The logic level of IO/M tells extemalcncuiry wherler a memory or UO trdnsferis taking placeover the bus. lngic 0 at this output signalsa memory operalion,and logic I signals an VO operatioi. The direction of datatansfer over the busis sienaledby rne logic level ouFut at DT/R- When this line is logic I during the datatransferpan of a bus cycle, the busis in the transmitmode.There fore. dataare either written into memory or output to an UO device.On the other halrd. logic 0 at DT,R signalsthat drc bus is tu the rcceivemode.This conesponds .eading to datafmm memory or inpur of dataftom an input porl ComparingFigs. 8 3(a) and 8 3(b), we find two differences befv/en minimumthe mode8088 and 808b microproce,ssors. rhe 8086 s memoryno conFotrMI-Or 'isnal Fi^L is the complement the equivalentsignaloflhe 8088.Secondthe 8088\ SSOstatussigof nal is rcplacedby bdnt /,ish e able (BtE\ M tre 4086.l-ogic 0 on tlis line is usedas a mernoryenablesignalfof r}le nosr sienmcantb)'te har of the databus, Ds drough Drs. This line also carriesstatusbit 57.
Sec-8.3 Minimum-ModelntedaceSionals

t4l

The si$als r.dd(RD) and n/itu (WR) indjcate that a readbuscycle or a write b[s c)cle. respeclel). i, in progress. MPU suilchesWR-ro log;c0 ro 5ignalexremal The devicesthat valid write or outputdataare on the bus On the otherhand,RD indicatestl|i fte MPU is perforning a readof dataoff the bus.During rcad operations, otherconone aol signal,DEN (data r.rbla), is also supplied.It enablesextemaldevicesto supplydaE to the miuoprocessor. One other control signalinvolved with the memory and I/O interface,the READY signal,can be usedto insert wait states into the bus cycle so ihat ir is extended a num by ber of ciock periods-Th;s signalis providedby way of an extemalclock generator device andcan be suppiiedby tbe memoryor I/O subsystem signal the MPU whenit is ready to io pemit the datatsansferto be completed.

InterruptSignals
The keyinterrupt interface signals arc intettupt rq&rt (INTR) and intenwt (INTA). INTR is an input to the 8088 and 8086 that can be used by an acknowledSe externaldeviceto signalthat it needsto be seNiced.This inpur is sampled during the final clock period of eachtfftroction acquisition cyck. Logic I at INTR represents active an interrupt request. Wlrcn the MPU recognizes interupt request,it indicatesthis fact to an exrematcircuirs with pulsesto logic 0 at the INTA outpur. The TEST input is also relatedto the exiemal interruptinterface.For example,execulion of a WAIT instructioncauses 8088or 8086to checkthe logic level at the TEST the input. If logic I is found at this iDput,the MPU suspends opention and goesinto what is known as the idle rtdt?. The MPU no.longerexecutes instructions;instead,ir repeatediy checksthe logic level of the TEST input waiting for its transition back to logic 0. As TEST switchesto 0, executionresumeswith the nexi instruction in the program. This feanre can be used to synchonize the opemtion of lhe MPU to an eveni in exremal hardware. There are fwo more inpuis in the irtenupt inretface: nonnaskable interrupt (NMl) and,'rer (RESET). the 0{o-1 t ansition NMI, controlis passed a ronOn of to maskable intenupt serv;ceroutineat completion execution the currentinstruc, of of tion. NMI is the interrupt requestwith highesr pdority and cannot be maskedby software.The RESETinput is usedto providea ha.dware resetfor the MPU. Switchirg RESETto logic 0 initializesthe intemalregisters ihe MPU andinitiatesa resetser of

DMA InterfaceSignals
T\e diect memory dcc?rr (DMA) inreface of the 8088/8086minimum-mode microcomputersystem consists of the HOLD and HLDA signals. When an extemal devicewantsto take control of the systembus, it signalsthis fact io drc MPU by switcb ing HOLD to the 1 logic level. For xample,when the tlOLD inpur of the 8088becomes active, it enten the hold state at the completion of the cnrrent bus cycle. When in the hold state, signallinesADo through AD7.As tbrough Ar5,A16/5rthrough Arr/56,SSO,

342

The 8088 and 8086 MicroDrccessofs ChaD.8

IOA4. DT/R, RD, WR, DEN, and INTR are all put into tlle high-Z state.The 8088 signals exremaldevices.hat it is in this stateby switching its HLDA output to the I logic level.

INTERFACE 8.4 MAXIMUM-MODE SIGNAIS

is configfation, it Wlen the 8088 or 8086 microprocessor set for the maximum-mode producessignalsfor implelnentlng^ nuhprccessor/coptuc.ssorslstem enrimnment-By exist in the system nulnprccessot eNionnen. we mean that multiple microprocessors and that eachprocessor executes own proglam. Usually in this t)?e of systemenviits ronment, some systemresouces arc commonto all processors. They are caled gldb"l Effu'.er. There are also other resomces that are assigned specitrcpmcessors. to These dedicated resources kt(t\\rn as local or pilate resourcesare rn the maximun-mode system,facilities are provided for inplementing allocation of global resources passingbus conFol to other microprocessors and sharingthe systen

8288 BusController; Commands ControlSignals Bus and

Looking at &e maximum-mode block diasramin Fig. 8-5(a), we seethat the 8088 not directly provide all the s+nak rnat arerequnedto control ft memory I/O, and does intenupt inlerfaces.Specifically, the WR, IO/M, DT/R, DEN, ALE, and INTA signals are no_longerproducedby the 8088. Instead,it outputs a statuscode on three signals lines. S0.Sr, and S,, prior to the inidation of eachbus cycle. This 3 bit b!..rrtdt r co./e identifies whichtype ofbus cycleis to follow. SrSrS0 input to the extemai,rs corare trollel device,the 8288, which decodes then to ideniry fte type of MPU bus cycle. The block diagramandpin Iayoutoflhe 8288 are shownin Figs- 8 6(a) and (b), respectively. In response. bus controller generates appropriatelytimed commandand control the the sisnals. Figure 8-7 showsthe relationshipbetween busstatuscodesandthe typesof bus the cycles.Also shown are the output signalsgenerated tefl extemal cncuitry which type to of bus cycle is taking place.Theseoutput signalsare neDory read comtnnd (MRDC), nenorJ x)rik comnandO,tw'lc), adrancednenory wik convand (t\MwC\. I/O read comand IORC), I/O wfte conafund (rOwC), advared xO wntu conoMnn (NOWC), (INf A). audinterrupt acknowledqe The 8288 produces one or two of rhesesevetr conunandsignalsfor eachbus cycle. For instance, when the 8088 outputsthe code SrSrS0: 001, it indicatesthat an I/O read cycle is to be perfonned.In turn, the 8288 makesits IORC output switch to logic 0. On the orherhand,if the code 1I I is outputby fte 8088,it is signalingtlat no bus activiry is no to takeplaceithe 8288produces command signals. The other contol outputsproducedby the 8288 consi:rtof DEN, DT,R, and ALE. Thesettuee signalsprovidedle sane tunctionsasthosedessibed for the minimum mode. Figure 8-5(b) showsthat the 8288 bus corto er connets the 8086 in the sameway to as the 8088,and it also produces sameoutput signals. the
Sec 8.4 InterfaceSrgnals fMaxrmumMocle

343

M36a M'E

t'

ozee ar.

otN DT/i

EEd @d
AIOWC-

tnra
MCE/FEEfr

DT/RDEN ADo-AO?, Ar.A,-A01S.

R6

-FO/Glr

-RO/Glo

Lo6lbu. 6nrol

(a' (b) FtguE 8-5 (a) 8088nardmuxn-node blockdiagram. 8086rnerimum-mode block

EMMPLE8.3
ff the bus statrs codeSrSlS0equals101,what g?e of bus activity is taking plac?Wlich conmand ouFut is Fodrced by the 8288?

Solution
Lookingat thetable Fig.8 Z we see busstatus in that code101identifies read a memory bnscycleandcauses MRDCoutput thebuscontrollel be switched logic 0. the of to to

344

The8088 and a0a6 Microorocessofs Chao.I

AIN

MRD'
MlrTC

s.

3233

^Mra
io-Rc'o-*:c

RESET

AIOWC

iMI
MCE/FDEN

DT/i

a-ft
BHE

RD

EoicT, Ra/cL
(b)

FigurEE-s (cortinued)

Lock Signal
To implement a multiprocessorsystem,a signal called lock (LOCK) is provided on the 8088and 8086.This signalis meantto be output(logic0) whenever plocesthe sor wants io lock ont the other processon from using the bus. This would be the case when a sharedresourceis accessed. LOCK signal is compatiblewith the Mrltibrr, The an industry standard for interfacing microprocessor systems in a multiprocessor

sec 8.4

Maximum-lvlode lnterface Srgnals

345

-'l. o-id

iFiI

n
iit -iE fiic

la

i6ta 6i-4

tbt
Figure 8-6 (.) Blocl diagrM of the 82E8.lReprjited tith permisjon of (Rcprhtedwnh pemission htcl of lnLel Corporation, 1919)(b) Pin layout. E O Corporation. i979)

Status Signals Oueue

produced the 8088and 8086.in the naxinum-modemicro Two orhersignals by status sysrem, queuestatus are outputs computer QSoand QSr tharfon ^2bjt queue informationwas This code tells lhe extemalcircuitry whal type of .,1e, QSlQSo. clockcycle.Figure8 8 shows duringthe previous tiom the inltructionquene rcmoved = that Note tharQSlQSo 0l indicates the first byte siatus codes. thefour dillerentqueue of an insfirctioD was taken off the queue.As shown. the feich of the Dextbyte of lhe of the is by instmclion identilied the codeil. Whenevef queue reseldueto a t|,tnsfer is codc10 is ouiput. |he control, reiniiialization

s2
0 0 0 0
I 1

s1

s0
0 1 0 1 0 0 1

CPUCycle
Inlerupt Acknowledge

E2!6Comm.nrl

-----to--o s9M_RDC lvlFDC

Hall

frfrJaA-Mwc

(Repnnbd O wnh permisior of l.rel CoiPoratiotr. 1979) Figure8-7 Bus staius codes.

t46

The 8088 and 8086 Mjcroprocessors Chap I

os1 osn

OuaueSlrlur

0 No Operalion. Ourin! lhs

clock cycl, nolhing was

Firsl Syle.The bylstakan lrom lhe qleue wss the lirsl byle ol the

1(high)

0 Ouue Emply.The queue has reinilislireda rssultollhe as ben inslruction. ol sreculion a transfer Byte.Thebytelaken Subssqusnl was Iromths queue a subsequnl figure 8-8 Queuestatuscodes. (Reprintedlith pernisslon of lntel byleol theinslrucllon.
Corporanon, 1979) O

LocalBusControlSignals
In a maximum mode configuration,the minimum-modeHOLD and HLDA interThesetwo signalsarc rcplacedby requen/qrunt face of the 8088/8086is also changed. mechanismfor accessl,rr RQ/CToand RQ/GTj. They provide a prioritized bus access ing the local bus.

CHAMCTERISTICS 8.5 ELECTRICAL

ln the precedingsections,the pin layout and minimum- and maxinum-mode interface were intoduced. Herc we will firsl look at signalsof the 8088 and 8086 microprocessors power supply ratings of theseprocessors and then their input and output electricel the characteristics. pin Looking at Fig. 8 l(a), we find that poweris appliedbetween 40 (V".) andpins together.The nominal value I and 20 shouldbe connected I(GND) and 20(GND). Pins thatthe 8088or of as of V.. is specified +5 V dc with a tolerance =10EoThis ineans in voltagebetweenV"" and GND is 8086 will operateconectly as long as the ditrerence (25oC), bothtbe 8088 greater than4-5V dc andlessthan5.5V dc.At roomtemperature and 8086 draw a maximum of 340 mA from the supply. of Let us now look at the dc yO characteristics ihe microprocessor-that is. its input and output logic levels.Theseratingstell the minimun and ma{imum vollagestor the 0 and I logic statesfor which the circuit witl opente corectly Different valuesare speciliedfor the inputs atd outputs. for Figure 8-9 showsthe I/O voliage specifications the 8088 Notice thal the minfor is ai imumlogic I (highlevel)voltage an ouQut(VoH)js 2.4V This voltage specilied (IoJ as a test condition thai identifiesthe arnountof currentbeing sourcedby the ou@ut -,100 pA. Al1 processors must be tesledduring manufacturingto ensurethat under ths lest condition the vollagesat all outputswill remain abovethe value of VoH-i"
sec.8.5 ElectricalCharacteristics

347

+2.0 v +2,4 V

v.. + 0.5 v
Figure 8-9 I/O voltage levels.

lnput voltagelevels are specifiedin a similar way; exceptherethe raringsidentify the rangeof voltagethat will be correctly identified as a logic 0 or a logic 1 a1an input. = -0.5 V to VL,,"* = +0.8 V represent vilid For inslance, voltages therange in Vn a ",i. logic 0 (lowerlevel)dt an inputofthe 8088. The I/O voltage levels of the 8086 microprocessor identicai to ihose for ihe are 8088asshown Fig. 8-9. However, in thercis onedifference theiestconditions. the in For 8086,VoL is measued 2.5 mA instead 2,0mA, at of

A 8,6 SYSTEM CLOCK

The dme basefor synchronization the internal and extemal operations the microof of pro.essorin a microcompuier systemis providedby the cl.rc* (CLK) input signal,At pfesent,the 8088 is available two different speeds. standard oprutes 5 MHz and pan in Tbe ot the8088-2 operales 8 MHz.On theolberhand, 8086microprocessor at the is manufactuled in threespedsr s-MHz 8086,the 8-MHz 8086-2, dle lo-MHz 8086-1. the and The 8284 clockgenerator driverIC generate$ Figul8-I0 is a blockdiagram and CLK, ofthis device.

Iigu.e 8-10 Block diagam of the 8284clock generator(Repnntedwilh peF misslonof Intel Corporation.@ 1979)

348

The8088 and 8086 Microorocessors chao-8

CLK

Ftd

IigN E-ll Connetingthe8284lo the 8088. (Reprintedwith penission of lntei Cor?oration.@ 1979)

The standard way in which this clock chip is usedwith the 8088is to connecteither a 15- or 24-MHz crystal betweenits Xr and X2 inputs. This circuir connecrionis shown in Fig. 8 11.Note that a seriescapacitorCL is also required.trs lpical value when used with the 15-MHz crystal is 12 pF The funnanental crystal frcquerry is divided by 3 within tbe 8284 to give either a 5- or 8-MHz clock signal. This signal is internally bufferedandoutput at CLK. The CLK outputof the 8284canbe dnectly connected the to CLK input of the 8088.The 8284 connects the 8086 in exacdythe sameway. to Figure 8-12 showsthe wavefom of CLK. Here we seethat the signal is specified at metal onde semiconductor O4os)-compatiblevoltagelevels andnoi transistortransisior logic (TTL) levels.Its minimu.n and maximun low logic levels a.e VLdi : -0.5 V andVlda = 0.6 Y respectively. Moreover the minimum and marimum high logic levels areVs-i" = 3.9 V andVHms : Ve + 1 Y respectively. petrd of the clok signalof The a 5 MHz 8088 can rangefroln a nininum of 200 ns to a mrximum of 500 ns, and the maxilj.u.mrise andfatl tines of its edgesequal 10 ns. Figure 8-10 shows two morc clock outputs on the 8284i tte peripheml cLock (PCLK) and oscilLdtorclo.* (OSC).Thesesignalsare provided to drive peripheraiICs. The clock signal output at PCLK is half the frequencyof CLK. For instance,if an 8088 is operated 5 MHz, PCLK is 2.5 MHz. Also, it is at TTl-compatible levelsratherthan at MOS levels.On dre otherhand,the OSC output is at the crystal frequency, which is thre times that of CLK. Figure 8-13 illustratestheserelationships. T]le 8284 can also be driven from an extemalclock sourcejhe extemalclock signal is applied to ihe exiemal frequencyinput (EFI). Input F/C is provided for clock sourceselection.Wlen it is strapped the 0 Iogic level, the crystal betweenXr and X, to is used.On the otherhand.applyins logic I to F/C selects EFI as the sourceof the clock. The clock sync (CSYNC) input can be usedfor extemalsynchronization systems in that employ multiple clocks.

Figue E-12 CLK voltageand timing chdacteristicsfor a 5-MHz processor(Reprintedwilh permissjon of Intel Corpontion, O 1979)

s e c . 8 - 6 SystemClock

341)

Figure 8-13 RelationshjpbelweenCLK and PCLK. (Reprintedwith pennission of lntel Coryonrlon, O I 979)

EMMPLE 8,4
If theCLK inputofan 8086MPU is to be ddvenby 4 9-MHz signat, wha!speed version of the 8086mustbe usedandwhatfrequency crystal mustbe attnched the 8284? to

Solution
The 8086-l is the version the 8086that canbe run at 9 MHz. To create 9-MHz of rhe clock,a 27-MHzcrystal mustb usedon the 8284,

A 8,7 BUSCYCLE AND TIME STATES

A Dlli c)cb defines basicopemlion th pertbrms communicate that a microproces$or to with external devices, Examples bus cyclesare the memorylead, Demoly write, of input/output read,and inpuvoutput write.As shownin Fig. 8-14(a),a buscycleco esponds a sequence events stall with an address to of that beingoutputon the system bos followedby a reador write datatransferDuringthese operations, MpU produces the a series controlsigralsto conlrolrhedirection tinringof thebus. of and The buscycleof the 8088and8086microprocessors consists at least of four clock priods. These four time states calledT , T2,Tj, rnd Td.DuringTr, theMpU puB an are addrcss the bus, a write memory on For cycle, dataareput on thebusduringstate and T, maintained through andTa.Whena readcycleis ro be pedomed,the b s is first pur T3 in the high-ZstateduringT, and thenihe datato be readmusrbe available the bus on dudngT1 andTa. ThesefoLrrclock staLes gi\e a bus .jlle durationof 125ns X 4 = 500ns in an 8-MHz 8088system. If no bus cyclesare reqxired,the microFocessorperforns whal are knowr as td? rratr. During thesestates, bus activiry takesplace.Eachidle staGis one clock period no long,andanynumber themcanbe inserred ol berween cyctes. bus Figure8-14(b)shows two buscyclesseparated idle states.Idle stares perfomed if the insrructionqueue by are in.idelhe nicroproce*,'r tLll dnd ir aoe.nor neea,o'e,,dor wrireoperrnd. i. from Waitnoks .al also be insededinto a bus c),cle. This is donein response a ro request an eventin extemalhardwareinsteadof an internal evenrsuchas a full queue. by

350

The 8088 rnd 8086 MrLroproce\o.\

Chdp. 8

*-ru

-"-r"t"t"-]*"--l

tl --___________x__]@-

JL "*,*....- J _""r","."". *' ".". J 1-;';y;,".pgi**

FisuE E-r4 (a) Bus cycle ctock periods.(Reprinkn wirh lemisior of Inlel Corporation,O 1979) (b) Bus cycle with idle states.(Retrtured with pemissiotr of Iltel Corporaliorr O 1979) (c) Bus cycle with wait states.(Reprinted wirh pemi$ion of Intel CorpoEtion, O 19?9)

ln fact, the READY input of the MPU is Fovided spe.ificaly for rhis pupose. Figwe 8 14(c) showsthat logic 0 at this input indicatesthar tlle cuneni bus cycle shouldnot be completed.As long as READY is held at the 0 leve], wait statesare inserredberween states andTa of the curent bus cycle, and the dararhar were or the bus during T3 are T3 maintained.The bus cycle is not completeduntil rhe extemalhardwarereturnsREADY back to the 1 logic level. This extendsthe duration of the bus cycle, therebypermitring the use of slower memory and I/O devicesin the system.

EMMPLE8.5
What is the duration of the bus cycle in the 8088-based microcomputerif the clock is 8 MIIZ and two wait statesare iDserted?

Solution
The duration of the bus cycle in an s-MHz systemis give, in generalby ty.=500ns+Nx125ns
5 e c .8 . 7

BusCycleand llme States

35t

In this expression standsfor the numberof wait states.For a bus cycle wirh two wair N

t y"= 500rs+ 2 x 125 = 500ns+ 250ns ns = 750ns

8.8 HARDWARE ORGANIZATION THE MEMORY OF ADDRESS SPACE

From a hardwarepoint of view.the memory address spaces the 8088 and 8086-based of microcomputers organizedditrerently.Figure 8-i5(a) showsrhat the 8088'smemory are subsystem irnplemented a single 1M X 8 memory bank. Looking ar &e block dia is as gram in Fig. 8-15(a), we seethat thesebyte-wide storagelocationsare assigned conlo secutiveaddresses over the rangefrom 0000016 throughFFFFFT6. During rnemoryoperations,a 20,bit ad&essis appliedto the memorybank over address lines Ao ttuoughA,, It is this adahess selecrs storagelocation thar is to be a.cessed. that the Bltes of dataare trdnsferred beiweenihe 8088 and memory over databus lines Do throughD7. On the other hand, the 8086's lMbyte memory addressspace,as shown in Fis. 8 l5(b), is implenented as rwo independenr 512Kbyte banks: the torr (et)en)bank and 6e high (odd) bank Data. bltes associated (0000016, with an evenaddress 0000216. etc.) reside thelow bant, andthose in (0000116, with oddaddresses 0000316, reside rhe etc.) in hish bank.
.]IM SYTES

5 1 2 tl Y t E s

srrEs t12r(

2 0

(b) Fisur 8-15 (a) lM x 8 hemory bank of rhe 8088. (b) Hish and low memory banks of tle 8086. (Reprintedwirh permision of Intel Corporation, o 1979)

352

The4088 and 8086 Microorocessors ChaD. 8

The diagramin Fig. 8 l5(b) showsthat for the 8086 ad&essbits, A1 throughAre They are appliedto both banksin paralselectthe storagelocation that is to be accessed. signals.lngic 0 at A$ idennlel. A0 and bank high enable(BHE) are usedas bank-select On the byte fies an even-addressed of dataandcauses low bant of memoryto be enabled. byte an the the othgi hand,BHE equalto 0 enables high bank to access odd'adahessed of data. Eachof the memorybanl6 provideshalf of the 8086's 16-bi! databus. Notic that the lower bank transfersbytes of dataover datalines Do throughD7,while datatransfers for a high bant(useDs throughD,5. micrccomputersystem of We iust saw that the memory subsystem the 8088-based as is actuallyorganized 8_bitbytes,not as 16-bit words However'the contentsof any two b)4e as byte storagetocationscan be accessed a word The lower-addressed consecutive byte least significantbyte of the word. and the higher-addressed is its most signifiis the capt byte- It us now look at how a b)4e and a wod of dataare readfrom memory. Figure 8-16(a) showshow a byte-memoryoperationis perfomEd to the storage is Iocation at addrcssX. As shown in the diagram,the adahess suppliedlo the memory

(x+1t

(b1

Figue E-16 (a) B}'te trdsfer bY the 8088. (b) word tmsfer by the 8088

Sec-8.8

Space HardwarcOrganjzationof the MemoryAddress

35

bank over lines A0 throughAre, and the byre of datais wrilten into or read from storage locarion orerline.Do-hrough D cdJries \4SBo, rheoyteotdara.dnd X D-. rhe D0c;riestheLSB. This shows thara byte of datais accessed rhe 8088jn onebuscvcle. by A memory cJ(le lor an F088rLrnning 5 MH,, w t- no $aiL.rare.rate. 800n.. ar When a word of data is ro be transfer"ed berweenrhe 8088 and mernorv.we must rso Derform acce$e.ofremor). readjog sriling a bytFin eacn or acce-. Figure r6lbl 8 illustates how the word storage locarionstartingal address is accessed. bus cycles X Two are requred ro access word of data.During the fusr bus cycle, the leastsignificanrbyte a of the word, locatedat address is accessed. X. Again the address appliedro the mem is oD banx over lhrough and.heb)reot data Fan.fered o, irolnuo"g.'o.u. A. Aro. i. to tron X over Do tbroughD?. Next, the 8088 automaticallyincrementsrhe addressso rhat it now points to bvte dddre$ + L hi. addre$ X poin..lo lhene\rcon.ecutive b)re.lorage tocalion men in ory, which conesponds the most significantbyte of the word of daraat X. Now a secro ond memory buscycle is initiated. Durirg rhis secondcycte,daraare writren inro or read l?om the storage location at address + 1. Sinceword accesses memorytake two bus X of cycles instead one,it takes1.6ms to access word of datawhenthe 80S8 oDerarins of a is dr r 5 MH,, cloc,(ralew h ao wail !!ares. The 8086 .nicroprocessor performs byte and word data transfe$ differently from the 8088.Lel us next examine daratransfers can takeplacein an 8086-based the thar Fignre 8 17(a)showsthat whena byte-memory operarion pedorhed ro address is X, an even-addrcssed storagelocarion in dle low bank is accessed. Therefbre.A" is sei ro .ogic0 ro enJble lo$ bant of nemoD drd BHE-lo togrc I ru di.abrernehrshbao*. rhe 45 \houn ia rheblockdiJgran.d d arenan.rened or rromrhe toser bdnl ;\ er ddrd ro buslinesD0tbrough Line D? carries MSB of thebyte,andDo rheLSB. D?. rhe On the other hand.to access byte of dataat an odd address a suchas X + I in Fig. 8 l7,br.q0 r".el lo log,cI andBHFro logic0. Thi. enable, highbanx memor) rne of and disablesthe low bank. Daia are transfered betweenrhe 8086 dnd the hish bant over Du,rine( dTough Ds D.. He? Dr, repre.enrr MSB andDRrheLSB. rhe Wheneveran even,addressed word of datais accessed, both the high andtow banks areaccessed the same at time.Figure8-17(c)iltusrraies a wordar even how address is X accessed. Nole that both A0 and BHE equat0; therefore,both bants are enabled.In rhis case,bytes of data are ransfefed from or to borh banks at rhe samerime. This l6_bit word is aansfeffed over the comp]etedata bus Do through Dr5. The byres of an even_ addressed word are said io be aligned and can be rransfenedwith a memorv oDeration _ndlale\,rst onebuscycte. A word at an odd-addressed boundaryis said to be unaligned.That is, the leastsig_ nificanl byte is at the lower addresslocation in rhe high memory bank. This is demonstratedin Fig. 8 17(d).Here we seethat the odd byte of the word is locaied ar ad&ess X + I andthe evenbyreat address + 2. X Two buscyclesarerequiredto access unalignedword. Dwing the first buscycle, an theoddbyteof ihe word,whichis locared addrcss + 1 in thehish bank.is accessed. ar X .ignaloAo- t andBtU - 0 anda Jara Pr'. h rccompan'eJ \etecr b) ran,reroverD" throughDr5. Even thoughrhe datatransferusesdatatines Ds throughDr5, to the proces" ,or ;_i. thelow b\te of lhedddre,,ed $uro oard

354

The 8088 dna 8086 V.(rop.o.es\or5

Chap. 8

(d)

Figue 8-17 (a) Even-address byte transfd by the 8086.(Reprlnredwith per nision of Intei Corporariotr,O 1979) (b) Odd'addres byte tmsfer by ihe 8086. (Reprinted with permision of Inte] Corloetion. O 1979) (c) Even addres word transferby the 8086.(Reprintedwith permision of Iniel Corloration, O i979) (d) Odd addres wod iransfer by ihe 8086. (Reprhted wilh pemission of Intl Cor?oration.O 1979)

355

Next, the 8086 auromarically increments address tharA. = 0. This reDresenrs the so lhe nerl addreq, memoryuhich ,s eren.Thena \econdmemon bu. c\cte L iniridred. in During rhi,,econd clcle.rhee\enb)re localed X - 2 in rheto\ banl is acces,ed. ar The datatransfertakesplace over,buslines D0 throughD7. Tbis tansfer is accomDanie.d b)& 0and BHE - l. lo rheproce.soj. ie rhehigh dri, blreofrheuordol daia.

EMMPLE 8.6
Is theword at memory address 0123116 an 8086based of microcompurer atigned mis or aligned?How manybus cyclesare requiredto read it ftom memory?

Solution
The first byte of the word is rhe secondbyre ar the aligned-wordaddress 0123016. There_ fore, the word is misalignedand requirestwo bus cyclesto be read from memory

8.9 ADDRESS BUS STATUS CODES

Whenevera memory bus cycle is in plogress,an address bus statuscode S,S. is outDut b) rl'eprccessor 5rdru, The code n utripte\ed aodre.. Ar- andqr".'ftr. ruo. rs wirh birs bit codeis outpur aathe samerime the daraare caded ovr the daralines. Bits Sr and53 togetherfom a 2,bir binary codethar idenrilieswhich one of the four segment regrters was used to generate physical addressthar was oumur duinq ihe rhe periodin rhecurrenr c)cle. The tow add,"ssbut snru,,oae, are lisreain addresr bur Fig. 8-4. Here we find thar codeSaSr= 00 idenrifiesthe exrrasegmenr register 01 ide.r tifies the stacksegment register,l0 identifies the code sesment regisret and 11 identifies the datasegrnent regisrer Thesestatuscodesare ourput in both the minimum and rhe maximum modes.The codes can be examinedby external circuifty. For example,they can be decodedwith extemal circuirry ro enableseparatetMbyte adatress spaces ES, SS, CS, and DS. In fbr this way, the menory address reachof the microprocessor be expanded 4Mbytes. can to

8.I O MEMORYCONTROL SIGNATS

Earlier in the chaprerwe saw rhat similar control signatsare producedin rhe maximum andminimum mode.Moreover,we found ihat in rhe ninimum mode,the 8088 and 8086 microprocesson produceall the conrrotsignals.But in the maximum mode,the g288 bus contoller producesthem. Here we wiil look morc closely ar each of thesesisnais and rbeirtunctjons irh re,pecr memory u lo inlerface operdrion.

Minimum-Mode MemoryControlSignals
In the 8088 rnicrocompurersysrernshown in Fig. 8_18, which is configureal for Lhe minimum mode otoperarion. tindlhartheconnot $e prorjded srgnat( ro.upDon rhe inrerface rhe memory\ub\ysrem ALL, tOA4, Dt/R, RLi. WR. arl nf|,r. T|*" ro are

356

The80aa and 8086 Microprocessors Chap.I

8@8

Io/i
DEN

sso

Figure8-18 Mininun-no.le 8088remory hterface. when the bus is carrying a va]id control signalsarerequiredto tefl the memorysubsysiem in address, which dircction dataarc to be tansfend over the bus, when valid write data latch enable are on the bus,and when to pur read dataon the bus.Fot example,ad.dress (ALE) signalsextemal circuit y that a valid address on the bus. It is a pnlse to the I is in logic level alrd is usedto latch the address extemalcircuitry. T\e input-ouput/memory AO/ll{) and d^ta tnnsmit/rece e (DT/R) lines signal and extemalcircuitry whethera menory or I/O buscycle is itr progress whetherthe 8088 or receivedataover the bus-Dudng all memory bus cycles,IO/M is held at will transmit the 0 logic level. The 8088 switchesDT/R to Iogic I during the datatransferpart of the buscycle, the bus is in the transmitmode,anddataare written into memory On the oaher hand, it setsDT,.Rto logic 0 to signal that the bus is in the rcceive mode, which corlespondsto readingof memiry. The signarsr"d/ (RD) and lrn& (WR) identit that a read or write bus cycle, is respectively, in progess. The 8088 switchesWR to logic 0 to signal memory that a write cycle is taking place over the bus. On the other hand, RD is svritchedto logic 0 whenevera read cycle is in progess. During a[ memory operations,the 8088 produces one other control signal, ddta enable@El0.l.og:,c O at &is outPutis usedto enablethe databus. The logic level memoryinterface. Slrtus l;n" SSOis alsopart ofthe minimum-mode is tbat is outputon this line during Iead buscyclesidentfies whethera codeor dataaccess instmctioncodeis readfrom memory in progress. SSOis setto logic 0 whenever The contol signalsfor the 8086'smidmum-node memoryinterfacediffer in three (M/IO) sigways.First, the 8088's IO/M signal is replacedby the mmory/input-output nal. Whenevera memorybuscycle is in plogress,ihe M/IO output is switchedto logic 1. Second,the si$al SSO is removedfiom the interface.Thftd. a new signal, ,anft tlgll enable(BHE), hasbeen addedto the interface.BHE is usedas a selectinput for the high That is, logic 0 is output on this line bant of memory in the 8086'smemory subsystemSec. LI0 Signals Memory Control

357

during the ad&esspart of all rhe bus cyclesin which darai, the hish-bank Darrof mem ory is to be accessed.

Maximum-Mode MemoryControlSignals
W}len the 8088 is conligured to work in rhe maximum mode. it does nor diectlv pro\ideall rl.econtrol.ignal( ro supponrhe memor)inrerface. Incread. exremal an bu' controllet the 8288,providesmemoryconmandsandcontol signats.Figure 8 19 shows an 8088connected thiswav in Specificalt). WR. tOA4. DT,R.bLN. ALE. andSSOrignat rine.on rhe8088 rhe are Lhanget. The) dre replaced virh nultiproce\\ot /or* rlOCKr signat. b,l \rdrar a (SrS1SJ, a 4rar? rrarrr cod?(QSreS0). 8088stitl does and produce sisnal The rbe !94e provides RD.which lhe.ame lJnclion il did in minimum as mode The 3-bil busstatus codeqS,Sn is nutputprior to the iritiation of eacbbuscycle. It identjfies whichlype ofbus cycleis to follow This codeis inputto the g2ggbuscon_ troller Here it is decodedto identify which type of bus cycle commandsignalsmust be generaled, Figure8-20 showsthe relationship belween busstatus the codes andthe typesof buscyclesproduced, Also shown this chartare the names the co$esDondins in of commandsignals rharare generaed the ourputs the 8288.For instance, inprircode ar of rhe S:SrSo equalto 100fldicares rhatan inerruction ferch cycleis ro takeplace. bus Since fie insructionferchis a memory read. 8288makes nenory readconnand (fr-RDC1 lhe the outputswitchto logic0. Anorher command bus provrded thememory tbr subsystem SrSl56 is equalro I J0. This represents memorywrite cycleand it causes a both the memorywrite conmand

8288

Figure E-19 Mdimun-mod 8088menory interface.

358

The8088 and 8086 Microprocessors Chap. 8

s!
0

sr
I

0
I

iflrA toRc rovc-, A-i6Fa

MRDC MIDc Mwlt. AMwc

Figure 8-20 Memory bus cycle stalus codesp.oducd in ffiimum (Reprintedwith pemission of lntel Corporation,@ 1979)

mode.

(MWTC) and advancedmenary \rfte command(|\NN{C) outputs to slvitch to the 0 logicle\e'. The other control oulputs producedby the 8288 arc DEN, DT,/R.andAlE These pins on the 8088 by signalsprovidethe sane tunctionsasthoseprcduced dle conesponding in the minimun systemmode. The two statussignals.QSoand QSr, lorm an instruction queuecode This code tells the exlernalcircuitry what type of infomation was removedfrom the queueduring For the previousclock cycle. Figure 8-8 sholvsthe four diffetent queuestatuses- instance' from the qneue The = Ol indicatesthat the lirst byte of an instructionwas ta.ken QSTQSo nextbyte of the instructionthat is letchedis identifiedby queuestatuscode 1l Whenever the queueis reset(e.g.,due to a transferof control) the reinitialization code 10 is output Simitarly, il no queueoperatio occurred,statuscode00 is outpur. The bus prioriD lock (LOCK) signal, as shownin the inteface, can be usedas an input to a bus arbiter.The bus arbiier is usedto lock otherprocessoffoff the systembus suchas glordl nendD' in a muldprocessor of during accesses conmon sysGmresources system.The READY signalis usedto intedaceslow memory devlces. microcomfor A11 the memorycontrol si$als we just described lhe 8088'based of 8086 microcomputerHow puter systemservethe samefunction in the maximum-mode ever thereis one additionalcontol signalin the 8086'smemoryinlerface,the BHE. The BHE performs the samefunction as it did in fie ninimum-mode svstem That is, it is usedas an enableinput to the high ban&of memory'

BUSCYCLES AND WRITE 8.I1 READ

with tl'e In the precediry sectionwe introducedlhe slatusand contml signalsassociated in memory interface.Here we continueby studyingthe sequence which thev occur during the read and write bus cyclesof memory sec.8.1I Read and write Buscycles

35t

Read Cycle
Figure 8-21 showsthe memoryinterfacesignalsof a minimum-mode8088 system. Here their occurenceis illustraredrelarivero the four time stares Tz, Tr. andT1 of the Tr, 8088'sbus cycle. Let us trace ihe eventsthat occur as dataor instructionsare read from The rcad bus q,cle begtnswith srateTr. During this period, the 8088 ourputsrhe 20'bit address fie memorylocation to be accessed its mulriplexedaddress/data of on bus ADo through AD?, As throughAr, and multiplexed lines A6/51 tbrough Arr/56. Nore that al the sametime a pulseis also producedat ALE. The rrailing edgeor the high level of this pulse shouldbe usedto latch the addrcss extemll circuitry. in Al.o \^e ceelhalar he {a1 ofT.. siCnal, lO/\4lld DT,Rare,et to rhe0logic level. This indicaresto circuitry in rhe memory subsystemihar a memory cycle is in p,!,sre\\ rha, 8088 lornr ro recei\e d from,bebu..Srdru. ,he ana ; d SSOr. at.oour-

IO/M RO

DT/F

-- -t

figure E-21 Minimum,modememoryreadbus rycte of the 8088.(Reprinted with lemision of intel Corporation,O I 979)

360

The 8088 and 8086 MicroDrocessors Chao. I

Dut at this time. Noie thai all tkee of thesesignalsare maintainedat theselogic levels ihroughoutall four periodsof the buscycle. Beginning with stale T2, statusbits 53 through 56 are outPut on the upper foul that ad{tress lines A16throughArr. Rernember bits 53 and S1identifv to extemalcirbus just output. This status the register was used to generate address cuitry which segrnent part of the ad&essoutput on information is maintainedttuough periodsT3 and T+ The Tr. bus address lines As tlrough Ars is naintained tfuough states Tr, andT4. On the other bus hand.address/data lines ADo throughAD? are put in the high-Z statedu.ing Tr' srbslsro in T. Lare penod RD i. 'qilchedro logic0 Ttu' indjcarec $e memoD 'o enable circuirr) erkmal ro'ogic 0 re.rl|ndrr rerd clc,e r' in progess DE\ I' ssirched to allow the datalo move from memory onto the midoprocessor'sdaia bus. As shownin the lvaveforms,input data are readby the 8088 during T3. The memterminates ory must provide valid dataduring T3 and maintainit until after the processor the rcad operation.As Fig. 8-21 shows,ir is in T! that the 8088 switchesRD to the inactive I logic level to lerninate the read operation.DEN retums to its inactive logic level late during Ta to disablethe exiernalcircuitry, which aliows datato move from memory The readcycle is now complete. ro the processor. A timing diagramfor the 8086'smemoryreadcvcle is Sivenin Fig 8-22(a) Comparing thesewaveformsto lhoseof the 8088 in Fig. 8-21' we ind just four differencesi dudng Tr; the datarcad bv the 8086 during T3 can BHE-is output along with lhe address carriedover a[ 16 databus lines; M,4O. which replacesIOA4, is switchedto logic I be

Fisur s-22 (a) Minimum-mode memory read bus cvcle of dre 8086' o o e I R ; o r i n d + t r np e m i . . i o n l l n r e l C o r p o r a l i O l o T q ' ' b ' \ 4 d r m u m _ m o d e Repr Inredwirl. Derris,ionol lnrelCoF mr:^ry ead bu, cycleof .he d08{-., poralior O 1979) Sec.8.1 I Readand Write Bus Cycles

361

FigureS-22 (continued)

of at the beginning ofTr andis held at this levelfor the duration the buscycle;andthe produced. SSO statussignal is not Fignre 8-22(b) showsa read cycle of s-bit data in a Ina\ilnum mode 8086 based microcomputersystem.Thesewavefoms are similar ro those given for the minimunthese two timingdiagrams, seethatthe we modereadcyclein Fig. 8 22(a).Comparing address datatnnsfers that take place are identical. In fact, the only differencelbund and in the maximum modewaveforms that a buscycleslatus is coite,SrSrS0, outputjFsr is prior to the beginningof the buscycle. This statusinformation is decoded the 8288to by producecontrol signalsALE, MRDC. DT/R, and DEN.

V/riteCycle
Figure8-23(a)illustrates tnite bus clcie trmingof 8088in ninimummode. rhe the It is similarto thatgivenfor a rcadcyclein Fig. 8-21. Lookjngat the write cyclewaveforms. we find that dudng Tr the address output and latchedwitb the ALE pulse.This is is identical to lhe read cycle. Moreover,IO/l'{ is set to logic 0 to indicate that a memory cycle is in progressand statusinformation is ouiput at SSO.However.this time DT,&. is switchedto logic L This signalsextemal circuits that lhe 8088 is going to tansmit data

362

The8088 and 8086 Microprocessors Chap.I

ro/ti
w3

ora__j
DEN

L.

_-J

sso

--1
r,

r(a)

modemmory wite b6 cycle of the 8088. Figure E-23 (a) MitriDDm (Repiinled pmission Intel Corporatior@1979)(b) Mdimum-node with of wrile buscycleof the 8086.(Reprinted penission of Intel CoF with memory poration, 1979) @

that As T, starts,the 8088 switchesWR to logic 0. This tells the memorysubsystem a write operationis to follow over the bus. The 8088 puts the dataon the bus late in T, and maintainsthe data valid though Ta. The writing of data into memory startsas WR becomes0, and continuesas it charyes to I early'in Ta. DEN enablesthe extemal circuitry to provide a path for data ftom the processorto the memory.This completesthe for Just as we described the readbus cycle, the write cycle of the 8086 ditrers from in four ways; agaia SSOis not prcduced!Bm isiutput along with the that of the 8088 addressi data ,re canied over a 16 databl]s lines: and fnally, M/IO is the complement of dle 8088'sIO/M signal.The wavefoms in Fig. 8-23(b) ilustrate a wrjte cycle of word datain a ma,\imum-mode 8086 system.

sec. 8.1 I

Readand Write Bus Cycles

363

FiguE E-23 (co lnued)

^' 8.i2 MEMORY INTERFACE CIRCUITS

This section describesthe memory interface circuits of an 8086-based microcomputer system.The 8086 systemwas selectedinsteadof an 8088 microcomputerbecause is it more complex. Figue 8-24 shows a menory interface diagram for a ma,\imum-mode 8086-based microcomputer syslem.Here we find that the interfaceincludesthe 8288bus contoller, address latchesand an addressdecoder.data bus transceiver/buffers. bus and bank read and w.jte control logic. The 8088 microcompuGris simpler in that the interfacedoesnot rcquire bank wdte control logic because address its spaceis organizedas a sinele banl. Lookingat Fig. 8 24, we seethatbusshruscodesignals Sr, andSo,whicharc Sz, outputs of the 8086, are supplied direcdy to the 8288 bus controller. Here ftey are decoded producethe commandand conhol signalsneeded coordinatedatatransfers to to over the bus.Figure 8-2o]ighlights the slaluscodesthat reiateto the memoryinterface. : For example, codeS2S]S0 101indicates a datamemory the thai readbus cycleis in progress. This codemakesrhe MRDC conmand output of the bus control logic slvitch to logic 0. Note in Fig. 8-24 that MRDC is applied to the banh read control logic. Next let us look at how the address is latched,buffered,and decoded. bus Looking at Fig. 8-24, we seethat address lines Ao throughAD are latchedalong with contlol signal Bm in the ad&ess bus latch. The latched addrcsslines AjrL tlrough ArrL are

t64

The8088 and 8086 Microprocessors chap. 8

-cE" cE-,

BHE

wR, WR.

Fd

Figure8-Z

Memory interface blockdiagram.

chip enable outpubCq Lhrough . Notice$ar lhe 8288busconeE decoded produce lo troller producesthe addresslatch enable (ALE) control signal from SrSlSo.ALE is and appliedto lhe CLK input of the lalchesad strobesthe bits of the address bank high latch devicesbuffer thesesignals. nablesignalinto the ad&essbuslatches.The address directlyto the address linesArL tbmugh Ar6LandCq tuough CE7areapplied Latched memory subsystem. ihe Du.ing readbuscycles,the MRDC ouqut of the buscontrol logic enables bytes of dataat the outputsof the memorysubsystem onto databus lines Do tbroughD15.During read operationsfrom memory fte batrk read control logic determineswhether the on dataare readIiom one of the two memorybanksor ftom bolh. This depends whether place over fte bus. a byt- or word-datatransferis taling Similarlyduring wrile brtscycles.rhe IvfwTC ourpurof he bu. coDtrollogic erablesbytsof datafrom the databusDo drough DE to be written into the memory.The to bank wnte conaol logic determtues which memory bank the da(aare wdtten5ec.8.12 Memory lnteriaceCjrcuits

t6t

Note in Fig. 8 24 that in ihe baDl write control logic the latched bad( high enable and address l;ne AoL are galed wilh lhe memory $rile conmand signa] {g4LBmL MWTC toTroduce 4 leparale wrile enable signal for each bank. These signals are denotedas WRL' and WRL. For dample, if a word of dala is Io be wriLlcn|o memory over data bus lines D0 tbrougl Drr, both WRu and WRL-are switched to their acrive 0 logic level. Similarly the memory read control logic uses MRDC, AoL. and BIIEL to gene te RDu and RDL sisnals for bank read control. The bus transceiven conirol the direction of dala ransfer between the MPU md memory subsysten In Fig. 8 24, we see that the opoation of the t ansceiver is con trolled by the DT/R and DEN ouFuts of thc buJi controllcr DEN is applied to the EN This happens input of the transceiverjdnd enablesthen fo. operatioD. during all read and wriie bus cycles. DT/R selects the direction of data transfer ttuough the devices. Note that it is supplied ro lhe DIR input of lhe dala bus ransceiYels- W})en a read cycle is in progress. DT/R is \et to 0 and dala are passed from thc memory subsystem 10 the MPU. On dre other hand. when a write cycle is taking place. DT/R is switched to logic I and data are carried from the MPU to the memory subsyslem.

AddressBus tatches and Buffers

The 7,lFl73 is xn examplc of an octal latch dcvicc that can be used to implement the ddr.rr /d.., section of the 8086 s memor) i erface circuit. A block diagram of this device is shown m Fig. 8-25(a) and fts intemal circuit] is shown in Fig. 8-25(b). Note that ii accepF eight inpuis: lD through SD. As long as the clock (C) inpnt is ar logic I, the outpxts of fte D-t-vpe ltip-flops follow fte logic level of the data applied to their cor responding inputs.When C is swilchedro logic 0, fte current contenlsof tbe D type fiip flops de latched. The laiched inrbmation in the flip flopr is not output at data outputs 1Q through 8Q unless the output'control (OC) irpu. of the buffers that fo ow dre larches is at logic 0.IfOC is at logic l, fte outpulsare in ihe high-impedance srareFigure 8 25(c) summdizes this operation. In the 8086 microcomputer system, the 20 addresslines (ADo AD 5, A 6 Ar,) and the bank higlr enable signal BHE a.e nomally la.ched;n ihe addressbus latch. The circuit configuration shown in Fig. 8 26 can be used to latch these signals.Fixing OC at the 0 logic le\l permanendyenableslalched outputs AoL rhrough AreL and BHEL. Moreover. thc addressinformation is latched at the outputs as the ALE signal ffom the bus controller returns to losic 0 that is, when the CLK itrput of all devices is switched io logic 0. In general.it is importail to m;nimize the propagationdelay ofihe addresssignals as they go through the bus in erface circuit. The switching propeny of the 7,1F373latches that deternine this delay for.he cncuit of Fig. 8 26 is called enableao-output propagation d?ldJ and has a maxirnum value of 13 ns. By selecting fasi latches that is, iatches with a shoner Fopagation delay time a maximum amount of the 8086's bus cycle tirne is preservedfor fte accesstimc of the memory deviccs.In this way slower. lower cost memory ICs can be used. These latches also provide bulTering for the 8086 s address lines. The outpuis of the latch can sint a maxnnum of 2,1 lnA.

356

lhe 80aa and 4086 Microorocesso6

Chao I

0c
iD

10 20 30 Ito

c
1D

m o

m
ao

80

O-C
L LHL

Enabl C
I.]

D
H

o
L

Figure 8-25 (a) Block diaSm of d @ta] D'rype latch. (b) Circuit diagm of the 74F373. (CouJtesyof Texas lnstrumentsIncorporated)(c) Operation of the 74F373. (Courtesyof TexasInstrumnts hcorpoFted).

''lll t-Tv

|]l
I

oc

tl Ir*
r---L

t
-[

f"'v

i Ll

AHE

oa

Figurc 8-26

Addresslatch cjrcuit.

Bank V/rite and Bank ReadControl Logic

The memoryof the 8086 nicrocomputer is organizedin upper andlower banks.Il requiressepdrate wrire dnd read control signaisfor the rwo banks. The logic circuit in Fig. 8 27 showshow the bank wdte contlol signals.wRu lbr the upper bank and wR! for the lower bank can be generaied from lhe bus controller signalsWRTC, the address AoL buslarchsignals andBmL. Two OR gates used thispurpose. are for Similar io the bank wdte conirol logic circuit. the bant rcad contol logic circuii can be designedto generaleRDu. the read for the upperbank of memory.and RDb the readfor the lower bank. Figure 8 28 illustratessuch a circuit. Note that ihe circuit uses the MRDC signalfrom the bus controller

DataBusTransceivers
dala bush lnsceiNerblock of the busintertacecircuir cm be implemented with 74F245 octalbustransceiver Figure8 29(a)shows blockdiagram this device. ICsa of Nole thati1sbidirectional input/ourput Iinesarecaued through andB I drough Bs. Aj As Lookingat the circuitdiagram Fig. 8 29(b).we seedut the G inputis used enable in to 'lhe

t6a

The 8088 and 8086 Microprocessors Chap. I

1432

Figurc 8-27 Ba'k wite controllogic. the buffer for opration.On the other h'ind, the logic level at the direction (DIIR) input selectsthe direction in which data are transfendthroughthe device.For instarrce,logic 0 at this input setsthe transceiver passdata{iom the B lines to the A lines. Siwitching to DIR to logic I reverses direction of datatlansfer. the Figure 8-30 showsa circuit that implementsthe databus transceiver bl,ock of the businterfacecircuit using the 74F245.For the 16-bit databusof the 8086micr(rcomputer, two devicesarerequired.Here the DIR input is ddven by the signaldatatransr"ioit/receive (DT/R), and G is supptiedby data bus effable(DEN). Thesesignalsaie outlputs of the 8288 busconholler Another key function of the data bus hansceivercircuit is to buffer t.loe &ta bus lines.This capability is definedby how much currentthe devicescan sint at rheir outputs. Ihe IoL rating of the 74F245is 64 mA.

BHEL
MRDC

7432 FigureE-2E Banl readcontrollogi..

5e..a.l2

Memory Interface Circuits

36t

Figure 8-29 (a) Block diaeramof the 74F2450cl2l bidirecrionalbus tmsceiver (b) Circuir diagramof tle 74F245.(Coudesyof Texaslnstro-

Addft 3ssDecoders
A s shownin Fig. 8-31, the adnrcssdecodern Ae 8086 micrdcomputrsystemis located at the output side of the addrcsslatch. A typicat device used to pelfolm this de.ode1:unctionis fte 74F139dual2line to 4line decoderFigures8 32(a)and(b) show a block diagrarnand circuit diagram for tbis device, respectively. When the enable(G) input is r at its actrve0 logic level, the output conespondingto the code at the BA inputs

t70

The 8088 and 8086 Micfoprocessors Chap. 8

:N

iR

Mic,op@s$d d.ta b6

G ] I DBo-D8,

74F245

Figm 8J0

Databustransceiver circuit.

switches.o the 0logic level. For instance, whenBA : 01, outputYr is logic 0. The table in Fig. 8-32(c) summarizes operationof the 74F139. the The circuit in Fig. 8 33 employsthe addrcssdecoderconfigurationshown in Fig. 8 31. Note that addressLinesArTL and ArsL are applied to the A and B inputs of the /,1flJq decoder. address Aror i( usedro erableone ol rbedecoders {r,r. fte line and obtainedusing an inverter,enables seconddecoder the 74F139.Eachdecoder the genol eratesfour chip enable(CE) outruts. Thus both decoders the 74F139togetherFoduce of the eight outputsCEottuough CE7.

M crop'@e$r

dddr*

bus

Figure 8-31 Sec.8.12

Addressbus connguation with ad.liessdecoding.

Memory Inteface Circuits

371

Y2 Y3

e,* I'^

L2B

Ftgure 8-32 (a) Block diasrm of th 74F139 2line to 4line decoder/ denu|iplexer (b) circuit diagrm of the 74F139. (Counesy of TexasInslrunents Incoryorated)(c) oleration of the 74F139 de.oder. (counesy of Texas Instruments Inco@rated)

372

c&
cEr
cEr 1Y3 74F139 . 2Y0 2v1 2\2 2\3
cE4 cE5 cE3

cE
CF,

Figur8-33 Add.ress de.oder circuit.

The block diagram of anothercornmonly used dcoder,the 74F138,is shown in Fig. 8-34(a). The 74F138is similar to the 74F139,exceptthat it is a single three-Iineto eight-line decoder The circuit usedin this deviceis shown in Fig. 8-34(b). Note that it can be usedto produceeight CE ouQuts.The table in Fig. 8-34(c) descdbes opera the tion of the 74F138.Here we find that when enabled,only the output that corespondsto the codeat rhe CBA inputs swirchesto the active0 logic level. The circuit in Fig.8 35 usesthe 74F138to generate chip enablesignalsCEotbrough CE7by decodingaddress linesAr7L.ArsL, andArrL. Connecting enableinputsto +5V the and groundpermanently enables decoder. the The advantage using the 74F138overthe of 74F139for decodingis that it does not re4uire an extra inverto to genemteeight chip enablesisnals.

sec.8.12

Memory lnterface Ckcuits

313

YO

\2 Y3

Y5

dzA GzE

Y6 Y7

'*t*'

(c)

ol-:T::: dT.cr-al,- lf ' 8-34 Frsure - d' qb.k rcorp"rar'"' ''' .ff"iJ,i'"T'iii of Te\as Ins!ruments tc;unes\ ofTe\asln\mments licorPonre!| (Counesy "ifll,T

cBz
cE3 cE4

c1

cEj

c2B

@1

Figure E-35 Addres decodercircuit using74Fi38.

B. i3 PROGRAMMABLE LOGICARMYS
In the last section we found that brsic logic devicessuch as latches,tiansceivers. and decoders rcquired in the bus interfacesectionof the 8086 microcomputer are system. We showed thesefunctionswercperformed that with standard logic devices suchasthe 74F373 octal imnsparenilaich,74F245 ocral bus tansceiver and 74F139 two-tne ro four-line Todayprcgrunnable logic aftay (PLA) devicesare becomingvery decodet respectively. impotant ir the desigr of microcomputer systems. example, For address controlsignal and decodingin the memoryinterfacein Fig. 8-24 canbe inplemenled with PLAS.insteadof with sepaEtelogic ICs. Unlike the earlier mentioneddevices,PLAS do not implementa specificlogic function.Instead, rlEy arc general-purpose logic devics dlat havefie abiliry to perfonn a wide variety of specialized loglc tunctions.A PLA contains general-purpose a AN'D OR NOT aray of logic gate circuits. The user has the ability to interconnect the inputs to the AND gatesof this array.The defnition of theseinputs determines logic the functionthat is implemented. process The inputsof lhe AND usedto connector disconnect gateanay is known asprosldnm,n& which leadsto the nameprogrammable logic array.

PLA5. GAt"s. and EPLD5

A variety of different types of PLA deviceslre available-Early deviceswere atl process,Thesedevicesare referred to as manufactured with the bipolar semiconductor pal PALi aDdrenain iD usetoday.Bipolar devicesarc programmed with an interconnect tem by burningout fuselinks widin the device.ln the initial state,all of thesetuse links are intact. During pmgramming.unwantedlinls are open-circuited injecting a current by
sec 8.13 Programmable LogicArrays

375

tlmugh the fuse to bum it out. For this reason,once a device is programned it cannot be reused.If a design rnodificaiion is required in the pattem, a new device must be prograrnrned substitutedfor the original device.Since PALSare madewith an older and by technology,they lre limited to sinpler funcrions and characrerized slower bipolar andhiSh power consumption. operatingspeeds With this Focess' with the CMOS process. Newer PLA devicesare manufactured high-speed, low-power devicescan be made.Two kinds of CMOS PLAS very complex, arein wialeusetoday; the GA, andthe tPrD. Thesedevicesdiffer in the type of CMOS ns:j..g ekcti&ll, erasableftttd'onlv technologyusedin their design.GALS are designed (E':ROM) technology.The inpuroutput operationof this device is determined r1?r,orl cells are also electricallv by rhe p.ogranming of cells. Theseetectricallyprogrannnable can be used for one apPlication'erased,and then reefasable.For this reason,a GAL programmedfor anotherapplication.EPLDS are similar io GALS in that thev can be and programmedr eraseal, reused;however,the erasemechanismis different. They are with electricallr prcSrannable read onb memory(EPROM) technologv manufactured That is, they employ EPROM cells instadof E'zROMcells. Therefore,to be erasedan EPLD must be exposedto ultraviolet lighi. GALS and EPLDS are cunently the mosa of rapidly growing segments the PLA marketplace.

Block Diagram of a PLA

a The block diagramh Fig. 8 36 rcprcsents typical PLA Looking at this diagram, we seethal it has 16 input leads,marked Io through IL5 There are eight output leads' outputs For this reason.ii labeledF0 lhrough F7.This PLA is equippedwith ttue-state conaol lead.In the block diagram.fiis control input is narked CE. The hasa chip-enable if logic level of CE determines the outputsare enabledor disabled. When a PLA is used to implement random logic firnctions. the inPuts represent randomlogic func_ Booleanvariables,and the outputsare usedto provide eight separate equato AND OR-NOT army is programmed definea sum-of-product tions. The intemal lheseoutputsin tems of the inputs and their complemenlsln this way, tion for eachof

Figure E-36 Block diacIm of a PLA. (Reprlited wilh the permission of WalterA. Tribel)

376

The 8088 and a086 Microprocessors chap. 8

we seethat the logic levels applied at inputs I0 tbrough Ir5 and the Progaaming of the AND arraydeterminewhat logic levels areproducedat outpul'tFotbroughF7.Therefore, the capacityof a PLA is measwedby thee Fopertiesr the numberof inputs, the number of outputs,and the numberof productterms (P-tems).

Architecture a PtA of
AND-OR-NOI Wejust pointed out that the circuitry of a PLA is a generalpurPose aray. Figue 8 3?(a) showsthis architecture.Herc we seethat the input buffen supply connections the in A input signalsA andB andtheir complemenis andB. Programmable AND aray permit any combinationof these inputs to b combinedto form a product term. The Foduct term outputs of the AND array are supPliedto fixed inputs of the

*".,1 *t
tI
I

F=AB+AB

(b) 37 G) BasicPLA archilectue. Inllenenting the losic tunctionF = 44E l!:_ (AB + AB). sec.a.l3 Programmable Afays Logjc

317

futction. Finally, the OR array.The output of the OR gateproducesa sum-of-products

h r n l e r t e fc o m p l e m e n tts i s f u n d j o n .

The circuit in Fig. 8 37(b) showshow dre functionF - (AB + AB) is implemented that th widl the AND OR NOT aray. Notice that an X markedinto theAND arraymeans !ba! fuseis left intact,andno markingmeans it hasbeenblown to folm an opencircuii. Rr to ihis reason.the upperAND gateis connected A and B and Foduces the productterm to AB. The second AND gatefrom the top connects A andB to producethe Foduct term AB. The bottomAND gaGis markedwith an X to indicatefiar it is not in use.Cateslike this that arc not to be activeshouldhaveaI of their input tuse Linksleft inlact. Figurc 8 38(a) shows the circuit structurethat is most $ridely used in PLAS. It differs from the circuit shownin Fig. 8-37(a) in two wals. First, the inverterhas a programmable thre-state control and can be usedto isolate the logic function Aom the oul_ put. Second,the bnffered output is fed back to fbnn anolherset of inputs to the AND array.This new output conligumlion permitsthe outputpin to be progJallllrcdto wo* as ^ standardautput, standad input, or logic-cantrcllzd inputlor,tput For instance,if the upperAND gate.which is the control gatefbr the output buffer is set up to permanendy enablethe inverter and the fuse links for ils inputs that arc fed back from lhe outputsare all blown open,the output functionsas a standardoutput.

OIJTPUT

Kt-

CLOCK

INPUT

(b)

FEEOSACK

rigu.e 8-38 (a) Tylical PLA archltecture.(Counesy of Teaaslnslrunents IncorpoEted) (b) PLA *nb output larch. (courlesy of TexasI.strunent$ Incorporated)

374

lhe 8088 dnd 8086 Vr.'op.ocessoA

Chcp. 8

PLAS are also available in {'hich the ou9uts are Iatched with registers Figure 8-38(b) showsa circuit for this rypeof device.Here we seethat the ouFut of $e OR gate is appliedto the D input of a clockedD t)?e flip-flop In this wav' the logic level produced at by the AND OR array is not presented the ouiput until a pulse is first applied at the out CLOCK input. Futherrnore,the feedbackinput is Foduced ftom the complementd is inverterThis configuration known asa PL4 unn pui of ihe flip-flop, not the outputofthe to re|isteredoutputs atrdis designed sirnpliry implenentationof state,?4.*r,e designs'

StandardPALruDevices
Now that we bave introducedthe rypesof PLAS, block diagram of tlle PLA' and internal drchitectureof the PLA, let us continueby examini4 a few of the widely used anay logic, is a PLA in which the OR arav is PAL devices.A PAl, or a programmable fixed; only the AND array is programmable The 16L8 is a widely used PAL IC. lts intemal circui.rv and pin numberingare shown in Fig. 8-39(a). This device is housedh a 2Gpin package'as shown in Fig 8-39(b). Looking at this diagam. we seerhat it employsthe PLA drchitectue illustrated in Fig. 8-38(a). Note that it has 10 dedicatedinput pins. All of.hese pins are labeledI' There are also two dedicatedoutputs,which are labeled with the letter O' and six pro I/O grarnmable lines,which are labeledyO Using fte programmable lines' rhe num I/O to ber of input lines canbe expanded as many as 16 inputs or the Nmber of outputscan to be increased a5 many as eigh. linesare All the 16L8's inpuLs bufferedand produceboth the original form of the signal The outputsof the butrer are appliedto the inputs of the AND arrav' and its complement. This array is capable of producing 64 product terms- Noie that the AND gates are arranged into eight groupsof eiglt. The outputsof sevengatesin eachof thesegoups are usedas inputs 1oan OR gate, and the eighth ouFut is used to p.oduce an enablesignal tlEee-state outputbuffer' In this way. we seethd rhe 16L8 is capafor the corresponding ble of producingup to sevenFoduct termsfor eachourpu! andthe Foduct ierms canbe formed using any coqbination of lie 16 inputs {iom a +5V :l:109' It with bipolar tchnology- operates The l6L8 is manufactured dc power supply and drawsa maximum of 180aA. Moreover,all it! inpuis and outputs are at TTL compatiblevoltagele\ls. This deviceexhibitshigh-speedinpui-outputpropagationdelays.In fact, the maximum l-to-O Fopagation delay is ratedas 7 ns Anotherwidely usedPAL is the 20L8 devic.l-ooking at the circuitv of this device Fig. 8-40(a), we seethat it is similar to that of the 16L8jusr described Howeve! the in 20L8 has a maxim m of 20 inputs, eight outpuls, and 64 P terms. The device's24-pin packaseis sllown in Fig. 8 40(b) The 16R8is also a popular20 pin PLA. The circuit diagramal}dpin lavout for this FIom Fig. 8 41(a), we find that device;re shown in Figs. 8-41(a) and O), rcspectively. I inpursand AND-OR array are essedially the sameas thoseof the 16L8' its eight fixed Thereiii oDechnge. The outputsof eight AND gates.insteadof seven,are suppliedto the inputs of eachOR gare. havebeenmadeat the ouiput side of the 16R8-Note thai the A numberof changes gatesare fiIst latchedh D type flip-flops wirh the CLK signal Thev outputsof the OR are then bufferedand suppliedto the eight Q outputs-Another charge is tbat the enable
Sec.8.l3 LogicAffays Programmable

37t

tE vo

tll] "o

!l 'o

rigure 8-39 {a) l6L8 circuit diaSrd. (Counesy of Texar lnslrumentsIncor?orated) (b) 16L8 pin layout. (Couliesy ofTexas Ilstrumenis Incorporated)

380

Figure 8-40 (a) 20L8 ctcuit diagram. (Courtesyof TexasInstrumentsIncorporated) (b) 20L8 lin layout. (Courtesyof Texashstrumenls lncorporaled)

3Al

6,:':

Figure 8-41 (a) 16R8 cncuir dia81am.(Couresy of TexasInstrutnerts lncorporated) (b) 16R8pin layout. (Couresy of TexasInstrunents lncorporated)

342

srgnalsfor the ootput invertersale no longer prognmmable. Now the logic level of the outputs OE control input enablesa[ three-state The last changeis in the part of the circuit that Foduces the feedbackinpuis ln the output of the colle16R8,theseeight inpu! signalsare derivedftom ihe complementary the ouq)utleadscanno spondinglarch insteadof the output of the buffer' Fo. this rcasoq longer be pro$ainmed to work as direct inputs. The 20R8is the registeroutputvenior of the 20L8 PAl Its circuit dia$am andpin layout are give! in Figs. 8 42(a) atrd(b). respectively

PtA Expanding CaPacity

the that haverequimments exceed capacityof a singlePLA IC- For Sone appiications hasthe abiliry to supply a rnaximumof 16 inputs' 8 outputs.and instance, 16L8 device a capacityLei us now look terher canexpand several devices 64 productterms.ConDecting $e to expand numberol inputsandoutputs. a! the way in which PLASare intercomected ff a single PLA does not have enoughoutputs,two or more devicescan be connectedtogelher into the configurationof Fig. 8 43(a) Here vr'esee that the inputs I0 through Ir5 on the two devicesare individualy connectedin parallel This connection doesnot changethe numberof inputs. usedto form On the olher hand, the eight outputsof the two PLAS are separately word. The bits of this wod are denotedas the upper and lower btaes of a 16-bit output OothroughOr5.So with this conneciion,we havedoubledthe numberof outputs. \vhetr data are appliedto the inputs, PLA I outputsihe eight leart significantbits of data.At the sameinstantPLA 2 outputsthe eight most significantbits Theseoutputs individual logic tunctions. can be usedto represent Another limitation on the apPlicationof PLAS is the numberof inplrts-The ma,\r mum numberof inputs on a single 16L8 is 16.Howevet additionallcs can be connecled the to expand capacityof inputs Figue 8-43(b) showshow oneadditionalinput is added is This permits a 17-bit input denoredasIo through116The new bit 116 suppliedtbrough invertersto the CE inputs on the two PLAS.At the output side of the PLAS, outputsOo in through 07 of the two devicesare individually connected paralel. To inplemenl this muslbe rsed ourpulc or coMeclion. PLA detrce'$i!h open-colle{lor three-\tale When 116 logic 0, CE on PLA 1 is logic 0. This embles the devicefor operation' is andthe oulput functionscodedfor input I0 tfuoughIr5 are output at Ootbrough07- At the sameinstant,CE on PLA 2 is iogic 1 and it rernainsdisabled Making the logic level of 116 equalto 1 disablesPl-A 1 aDdenablesPLA 2 Now ihe input at Io throughIr5 causes the output function definedby PLA 2 to be output at Oo through07 Actually, this conthe nection doublesthe numberof Foduct terms as well as increases numberof inputs

OF 8,I4 TYPES INPUT/OUTPUT

allows peripheralsto provide data or The input/output system of the microprocessor tbe receiveresults of processing data.This is done using I/O ports The 8088 and 8086 can microcomputers employ two diffemnt types of input/output (I/O): isolakd I/O at].d menory-mappedI/O. Thesel/O methodsdiffe. in how I/O pofts are mappedinto the employ both kinds of I/OSomemicrocomputersystems 8088/8086'saddressspaces. sec 8.14 Types Input/Output of

383

3{

6---i--i----1t--

t;

(a)

{b)

Figure 8-,12 (a) 20R8 circuit diaelam. (Couiresy of TexasInstrumentsIncorporated) (b) 20R8 pin lalour. (Courtesyof Te{as Insrtunents Incorporated)

344

llL
..-i_ I I

(a)

(Reprifiedwirh tbepenis; outPut wordlength. Figure8-43 (a)ExPanding with (b) Exlandingin?ut woid len$l. (Reprirted A. sid of Warler Tnebel) A. of thepermission Walier Triebel)

that is, some peripherallcs are treatedas isolaied I/O devicesand oihers as memoryI/O rnapped devices.Let us now look at eachof theseryPesof I/O.

Input,/OutPut lsolated
Wlten using isolatedI/O in a microcomputersystem,the I/O devicesare treated architectures because so{iwarcand hardwaxe the from memory.This is achieved separate Figure 8-zg illusoithe 8088/8086supportsepamtememory and I/O addressspaces. spaces. tratesthesememory and I/O address In our study of 8088/8086softwarearchitectue in Chapter2, we exarninedthese spaces from a softwarepoint of view.We found that infbrnation in memoryor at address sec.Li4 of Types lnput/Output

345

nemoryand Figure8-44 8088/8086

spacecontainslM conI/O pofs is organizedas bytes of data; that lhe memory address and through FFFFFL6I that the I/O address ,".uilu" Uyt" iaa..ttes io the range 0000016 FFFF 0000r' tuough In blre .o,...oniuin' O+K.on..cuLi\e add'e'se. Ineran8e " mapof rhi' l/O add'e'csp:ce Herc$e find Figure8 45,ariho\\s a morederailel] as could be accessed word-wide I/O that the;ltes of data in rwo consecutive addrcsses as can and 000216, 000316 be treated 000016,000116' l/O data.For instance, addresses 2, and3, or pons0 and 1 mavbe considered ports0. 1, l/O byte-wide ports. independenr togetheras word-wide Pot 0. Note that the pan of the I/O ad&essspacein Fig 8-45(a) from address000016 00FFr6is refered to aspdg a Cedain UO inslructionscan only perform opernhrough rarge Olher I/O instruciionscaninput or output ations'topots in this part ofrhe address space in datafor pons anywhere the I/O address This isolatedmerhodof I/O offers someadvantagesFirst, the complete lMbyte memory addressspaceis available for use urith memory' Second' special instuctions to havebeenprovided in *re instruction set ol the 8088/8086 perforn isolated I/o inp'rt tailored to maximize I/O pedorand ouD; operations.These instruciions have been i mance. dis;dvantageof this rype of I/O is that all input and output datatransfersmusl take piacebetueen the AL or AX registeranddre UO port

lnPut/OutPut Memory-MapPed
I/O devicescan be placed in the memory addressspaceof the microcomputeras In space. this cdse,lhe MPU looks at the UO pon well as in the independentI/O address in memory.For this reason'the methodis known as as though it is a storagelocation netnory napped I/O. systemwith menory-mappedI/O' someof the memoryaddress ln a microcomputer m to is space dedicated l/O ports For example'in Fig. 8 45(b) the 4096 memoryaddresses to are assigned I/O devices Here the contents tire rangefrom E0000r6throltgh E0FFFL'j E0000t6 b)'te-widel/O port 0, andthe conlentsof addresses represent E0000r6 of a<trtrlss por 0 to correspond word-wide and8000116

346

Theaoaa and 8086 Microprocesso6 Chap S

va

: E0oo316 E0004s Eooolls

0000i6 (16-bilpod (15-bil po't)

(b) risur 8-4s (a) IsolaiedI/o ports. (b) Menory-napped I/o ports

347

Wllen I/O is configuredin this way,inslructionsthat affect datain memoryare used in insteadof ihe specialinput/outputinslructions This is an advantage that many more modesare availableio perform I/O operations For instance' instructionsand addrcssjng l/O the contentsof a memory-mapped poll can be directly ANDed with a value in an intemal register.In addition, l/O tansfers cannow take placebetweenan l/O port andan in@mal registerother than ju$ Af or A,I. However,lhis also leads to a disadvantage. That is, the memory instructionstgnd to exe.ute slower than thosespecifically desigrcd for isolatedUO. Therefore,a memory mappedI/O routine may take longer to perform than an equivalentprogrl]musing the inputoutput tnstructlons. space of Anolher disadvantage usingthis methodis drat part of the memo.y address ihrough the range from 8000016 in in is lost. For instance, Fig. 8-45(b) addresses E0FFFI6.allocatedto I/O, cannotbe usedto jmplementmemory

INTERFACE INPUT/OUTPUT 8.I 5 ISOLATED

permitsthem to of The isolatedinput/outputt,?tdac the 8088and 8086 microcomputers with the outsideworld. Tlre way in whicb the MPU dealswith inpuvoutput communicate circuitry is similar to the way in which il interfaces with memory circuitry. That is' bus. This input/output data transfersalso lake place over lhe multiplexed address/data parallel bus permits easy interface to LSI peripheralssuch as Parallel I/O expanders. interval timers. and serial cornmunicationcontrollers. Through this UO interface, lhe MPU caninput or outputdatain bit, byte, or word (for ile 8086) formats Let us continue for by looking at how an isolatedUO interfaceis implemented minirnum- and maxirnummicrocomputersystems. mode 8088 and 8086

Interface Minimum-Mode
Let us beginby looking at the isolatedI/O interfacefor a minimum-mode8088 system. Figure 8-46(a) showsthis minimum-modeinterface.Here we find the 8088' interfaceciicuity, andVO poris for devices0 tbroughN I/O devices0 throughN can represent input devicessuch as a keybo.rd, output devicessuch as a printer' or inpuvoutpui port An exampleof a rypical I/O serial communications devicessuchas an asynchronous peripheralinterface(PPI) IC' such is device usedin the l/O subsystem a programmable as the 82C55A.This type of deviceis usedto implementparallel input and output poris The circuiis in the interface seclion must perform functions such as selectthe I/O port' lalch output data. sampleinput dgta, synchronizedata transfers,and translatebetwen TIL voltagelevels and ihoserequiredto operatethe I/O devices. The data path between the 8088 and l/O interface circuiis is the multiple)Gd bus. address/data Unlike the memory interface,fiis time just dre 16 least significantlines of the bus,ADo tlrough AD? andAs rhough Ar5, are in use This interfacealso involves as the control si$als that we discussed pad of the memory interface-that is ALE, SSO. RD. WR. IO,M. DTA.. and DEN. Figure 8-46(b) showsthe isolaredI/O intedace of a minimum-mode8086-based micrccomputersystem.Looking at this diagram.we find thai the interface differs from in tbat of the 8088 microcomputer severalways.First, the compleiedatabusADo through

384

The8088 and 8086 Microorocessors chap B

sso
, aDo-aD, \--------------)

vo
!o

Aa-A,a ---------------8@8 FD

uo

IO/M MN/MX

OEN

uo

tHE
' ADo-ADr5 RD

\-,/
3036

VE
M/id DT/F
MNA,IX

tEN
N

(b)

(b) risue 8-46 (a) Minimum-node 8088syslem interface. MinimDmVO mode8086system inlerface. I/O

AD;. is u.ed for inpurandourpur dararran'ter'r'econd.rbe V,4Oconrol .igal rs rhe of the equivalentsignalIOA4 in the 8088'sinterface;and third, statussignal lg4llenent SSOis replaced BHE. by

Maximum-Mode lnterface
tvhen fie 8088rs .trapped opemre rhe ma{mum moder\4J\/M} corurecred ro rn gound), rhe inteface to the I/O circuihy changes.Figure 8 47(a) illustrates this to configura.ion. Sec. Ll5 lsolated lnput/Output Interface

349

8233

vo

3133

Figure 8-47 (a) Ma-\imumnode 8088 systen I/O interface.(b) Mdlmum mode8086 systen I/O interface.

3to

s:

5,
0
I

iNlA

rorvc. A-idwa
I

0 I
I

iliSt MRDC fuwrc,AMw'c

with codes(Reprinled pernision of Intel Figure8-4E l/O buscycleslatus copyight/Intelcory. 1979) Corporalion, As in the naximum-modememory interface.lhe 8288 bus conholler produceslhe bus The control signalsfor the yO subsystem- 8288 decodes commandslatuscodesoutput by the 8088 at S,SIS0.Thesecodestell which type of bus cvcle is in Fogless. If the the code corespondsto an I/O read bus cycle, the 8288 generates /O rcad colllAll l/O dl/tprr (IORC) andfor an I/O write cycleit generacs wite mnma n ouQutsGOWC) an,l (AIOWC). The 3288 also Foduces the control signalsALE, DT,&.' and DEN The and datatransferpath between8088 and ma\imum node UO intedaceremains address bus address/data lins ADo throughAD? andAs throughAr i isolatedI/O intedaceof an 8086microFigure 8-47(b) showsthe maximum-mode processor syslem.Therc are only two differencesbetweenthis intedacediagramandthal As for the 8088microprocessor in the minimum mode,the tu1l 16-bit darabusis the path datatransfers,andlhe signal BHE, which is not suppliedby the 8088' is includedrn for the interface. The table in Fig. 8 48 showsthe busconmand statuscodestogetherwith the command signalslhat they produce.Thosefor I/O bus cyclesare highlighted The MPU indi= the catesthat dataare to be inpul (readI/O pori) by codeS2SrS0 001-This codecauses Thereis oneotler code produce controloulputI/O readcommand oORC) buscontrollerto two an that represents ouQutbus cycle,the write UO polt codeS,SrSo: 010.It produces UO \rrite cycle (IOWC) andadvanced \lTite cycle (AIOWC) srgnals: I/O outputcommand bus are sig:nals usedto enabledataftom the l/O ports ontothe system durThesecommand lo lhe l/O porl' duringan ouFul operalion Jno rngal irpul operalion from theMPU

DATATRANSFERS 8,I6 INPUT/OUTPUT

can Input/outputdatatransfersin the 8088 aid 8086rnicrocomputers be either byte-wide by or word-wide.The pon that is a(essed for input or outpui of daia is selected an /o as is drldrrs.This address specified palt of the instructionthal performsthe I/O operation' are I/O addresses 16 bits in length and are output by the 8088 to the l/O interface the over bus linesADo throughAD? andAs tl oughAr5.ADo represents LSB andAr5 the sec.Ll6 lnpuvoutput DataTransfers

3.rl

Arr, are held at the 0 logic lerel lines,A16through address MSB. The mostsignificant linesareusedto Since16 address period(Tr) of all I/O buscvcles duringtlre sddress I/O of 64K byte-wide ports consists space 1/O I/O address oorts,the 8088's address on thebusis for an I/O pon circuitrvthai rheaddress ro The 8088signals extemal insleadof a memorylocationbv switchingthe IO,M control line to the I logic level This js inputor ouQutbuscvcle For th'sreason' signal heldat the I leveldxringthecomplete decoderin externalI/o circuit$' latch or address it;an be usedto enablethe address Data transfersbetweenthe 8088 and I/O devicesafe performedover the databui' Data tfttnslersto byte-wideI/O poris alwaysrequire onebus cycle Byle datatransten to a pon dreperformedover buslines DothroughD? Word transfeNalso takeplaceoverthe as is this data bus,16througl17. However, ivpeofoperation pedormed two consecuiive two buscycles. datatrinsfersandlakes byte-wide bus ale I/O For the 8086 microcomputer, a{ldresses outputon iddress/data lines whether dataare A0 of ADrr' The logic levels signals andBHE delermine ADo lhrough or pon, even-addressed byte"wide-pttt' a byte-wide for inpuVoutput an odd-addressed I/O byte-wide pon is if port For example, A0BHE = l0' an odd-addrcssed word-wi;e over are ai to Byle accessed, datatransfers a pol,t an evenaddress perfbrmed buslinesD0 pon overDs lhrcughD 5 Data io an odd_addtessed areperformed D?;nd lhose through takeplacein onebuscycle I/O to lrAnsfers byte-wide ponsalways by arc lhe between 8086andI/O devices socompanied lhe code word dalatmnsLers D = 00 andareperfoDred thecomplete bur' Dothrough 5 A wordirans' data over A0BE for that To either ol two buscycles, ensure justonebuscycleis requircd one fer canrequhe bouudaries al b I/O word'wlde pofisshould aligned even-address theworddatatrmsfer,

INSTRUCTIONS A 8, I7 INPUT/OUTPUT
that ale operations pefbrmedby the8088and8086micrcprocessols employ Input/outpul addressI/O p-ort wilh the logether inputAndoltput iDslructions llO isolated usingspeclal S-49' Tbeir ir instructions, (IN) and o&r (OUT), are lisiedin Fig Thes=e i:rg motles. of with a brjefdescription theiroperations together are rnienonicsandforrnats provided Note tha! there arc two diilbrent forms of IN and OUT instructionslthe dircct 1/O can be instluclio s andvariahleI/O /tntt?rclr",{t.Either of thesetwo rypesof instrxrclions I/O dev;ce an used1()tansfer a byte or word of data.All dau anslerstakePlacebetween this registerFor thisreason, nethod of perfoming l/O is known MPU'Saccumulatof andthe and involvetheAL rEgister, nod transfeNtheAX r8is^s arumulat.tr t/O Byte nansfers

IN

( A . O l P o r r )

A c .= A L o r A x

o!rT
(v.dable) Outputindnci

Fieure 8-49

Inputoutput nstructom

3q2

The8088 and 8086 l\4icroprocessorschap. 8

registerin an I/O instuction indicates or ter.In fac! specjlyingAl asthe source destination to a byte transfer.That is, b)te-wide or word-word input/output rs that ii corresponds (Acc) in the instuction asAL or AX' respectivetv. by setected specifyingthe accumulator I/O instruction, the addressof the I/O polt is specifiedas part of tbe ln a dire.t its For instruction.Eight bits areprovidedfor this direct address. this reason, valueis limequalsFFr6 This raageis referred equals00b to 25510 rangefrorn 010 ited to the address space. to as page0 in the l/O address An exampleis the instruction
IN AI,, OFEH

I/O ihe of causes contents ihe byte_wide As Fig. 8-49 shows,executionof this instrucaion register This data porr at addressFEr6 of the I/O addressspaceto be input lo the AL transfertakesplace in one input bus cycle

EMMPLE8.7
to of Write a sequence instroctionsthat will output the dataFF16 a byte'wide outputport space. at address L6of dre I/O address AB

Solution
First, the AL registeris loadedwith FFr6 as an immediateoperandin the instuction
MOV AL, OFFH

port with the instruction Now the datain AL can be ouFut to dle byte-wide outpLrt
OUT OABH, AL

The differencebetwenthe direct alrd variablel/O inslructionslies in the way in We of which the address the I/O port is specified. jusi saw that for direct I/O instructions addrcss specifiedas part of the instruction.On the otherhand.the variableI/O is an 8 bit thai instmctionsusea 16 bit address residesin the DX registerwithin the MPU The value that an offset.It is the actualaddress is to be outputon ADo tfuoughAD7 and in DX is not is the I/O buscycle. Sincethis address a tulI 16 birs in length variAs throughAr5 during sPace. in portslocatedanywhere the 64K-byteVO address access ableI/O instuctions can I/O instruction,the datamusl be loadedinto or rcmoved When usingeirher type of from theAL or AX registerbeforeanotherinput or output operaiioncanbe pefomled ln the caseof variable I/O instructions,the DX registermust be toadedwith (he addrcss the This requiresexecutionof additionalinstructions.For instance, instructionsequence
MOV IN MOV DX, 0A00011 AL, DX B'-, AL

space into AL inputsthe contentsof lhe byte-wideinput port at A000i6 of the I/O address il in BL. and then saves sec.8.17 lnnftrcnons InPuVOutPut

3rt

EMMPLE8.8
Write a sriesof irsrructions that will output FFr6 ro an outpur port locatedat address B00016 the I/O address of space.

Solution
The DX registermust firsr be loadedwith the address rhe ouFur port. This is donewith of theinstruction
MOV DX,0B000H

Next, the dararhat are to be output must be loadedinto AL with the insruction
MOV AL, OFFH

Finally. the dataare outpui with the insrrucrion

OUT DX, AI-

EXAMPLE 8,9
Data are to be read in from rwo blre-wide input polts at addrcsses AA16 and A916and thenoutpui as a word to a word-wideoutput port ar address B00016. Wrire a sequence of insiruciionsto perfom this input/ourputoperarion.

Solution
We can firsr read in the byte from the pot at address AA16 inio AL and move it to AH. This is done fith the instructions
IN MOV AL, AI{, OAAII Ni

Now the other byte, which is at port A96, can be read into AL by the instrucrion
IN AL, OA9H

The word is now held in AX. To wrile our the word of data,we load DX with rhe aaldress 800016and usea variableoutpurinsruction. This teadsto rhe following:
MOV DX, OBOOOH

ouT Dx, ax

l. 8.IB INPUT/OUTPUT CYCLES BUS

In Section8.15, we found that the isolatedUO interface signatsfor the minimum mode 8088 and 8086 miffocomputer sysremsare essentially rhe same as rhose invotved in the memory interface.In fact. dle function, logic levels. and riming of a signalsother

3t4

The 8088 dnd 8086 lvr'L.ooro.esrori

Chap. 8

$an IO/M (M^O) are identical to those already describedfor the memory interface in 8.11. Section Waveforms the 8088'sXO input (l/O rcad) bus ctcte andUO output (XO lt'rite) for l,ookiry at the input and out,&r c],.lz are shownin Figs. 8 50 a 8-51, respectively. put bus cycle waveforms,we see that the timing of IO/M does not change.The 8088 It switchesit to logic I to indicate that an I/O bus cycle is in progress. is mai ained at the I togic level for fte duration of ihe UO bus cycle. As in memory cycles,the adahess is output together with AIE dudng clock period Tr. For the jnput bus cycle, DEN is switchedto logi 0 to signal the UO ifierface cncuitry when to put the dataonto the bus and rhe 8088 readsdataoff the bus during period Tr. On fte other hand,for the output bus cycle in Fig. 8-51, dre 8088 puts write data on the bus late in T2 and maintains it during th rest of the bus cycle. This time WR switchesto logic 0 to signalthe I/O systemthat lalid dataare on the bus. The waveformsof the 8086's inpul and output bus cycles are shownin Figs. 8-52 and 8 53, rcspectively.Let usjust look at the differencesbetweenthe input cycle of the 8086 andriat of the 8088.Conpariry the waveformsin Fig. 8-52 to thosein Fig. 8 50, in we seethat the 8086outputsthe signalBHE alongwith the addrcss T-stateTr. Remem-

on. b$ cvil.

r'lr,

IO/M F6 DT/F

$o --J Fig@ 8-50 Inpd bns cycle of the 8088.

sec.8.l8

Inpuvoutput

Bus Cycles

395

ro/fi
WU DT/RDEN

---t
Figure 8-51 Outpulbuscycleolth 8088.

^',.iitrd:l@

Figurc 8-52 Inputbuscycleofthe 8086

bus Figure8-53 OutPut cycleof the8086 this ber that for the 8086 microprocessor signal is usedaloDgwith Ao to selectrhe byteporr. Next, lhe 8086'sdatalransferpath to the I/O intedaceis the wide or the word-wide bus, 16-bit address/dafa not 8 bjts as in the 8088 system.Thercfore.datatransfels,which rakeplaceduring T3,cantakeplaceoverthe lower 8 databuslines, upper8 databuslines, or all 16 databus lines. Thhd, dre 8086 outpuislogic 0 on the M/IO 1ine,while the 8088 outputslogic 1 on the IO/M line. Thar is, the M,{O contol signalof the 8086is the con plementof that of the 8088.Finally, the 8086doesrot producean SSOoutput signallike the onein the 8088.

R E V I E WP R O B L E M S 8.l Section
1. 2. 3. 4. 5. 6. Nameihe tecbnologyusedto fabricalethe 8088 and 8086 rnicroprocessors. wlat is the transistorcount of the 8088? Wlich pin is usedastheNMI inputon the 8088? on the outpntsignals the 8086? which pin provides BHE/S? can dle 8088 and 8086 direcily address? How much memory spaceof fie 8088 and 8086? How large is ihe I/O address

8.2 Section
7. How is minimurn or naximum modeof operationselected? 8. Describeihe differencebetweenthe minimum-mode8088 systmand ma,\imum_ mode8088system.

tq7

9, What ouFut funciion is performedby pin 29 of dle 8088 when i" the minimum mode? Maximummode? 10. Is the sienalN4,/I'O input or output of the 8086? an 11. Nameonesignal thatis supplied lhe 8088but not by the 8086. by 12. Are the signalsQSo and QSL producedin lhe minimum mode or maximum

Section 8.3
13. Wlar are rhe word lengths of the 8088\ addrcssbus and data bus? The 8086's address anddatabus? bus 14. Does$e 8088havea multiplexedaddress/dara or independent bus address data and buses? 15. What mnemonic usedto identifythe leastsignificani of the 8088'saddress is bit bus?The most significantbir of the 8088'sdatabus? 16. \l/llat does statuscode SlSr : 01 mean in terms of lhe memory segmentbeing 17. Which output is usedto signal exiemal circuity fiat a byte of datais availableon the upper half of the 8086's databus? 18, What doesthe logic level on M,{b signal to extemal circuitry in an 8086 micro, 19. Which outputis usedto signalexternal circuity in an 8088-based microcomputer lhat valid datais on the bus during a write cycle? 20. What signal does a nininun-mode 8088 respondwith when it acknowledges an aciive inlerupt request? 21. Wlich sigr)alsimplement the DMA interface in a mininun-mode 8088 or 8086 microcomputersystem? 22. Lisi the signalsof the 8088 that are put in the high-Z staie in response a DMA to

Section 8.4
23. ldentify the signal lines of tbe 8088 that are different for the minimum-modeand ma,{imummodeinterfaces. 24. Wharsiatus outputs the 8088areinputsto rhe8288? of 25, Whar maximun'mode contol signalsare generated the 8288? by 26. What function does the LOCK signal serve in a ma{imum mode 8088 microcomputersystem? 27. What statuscode is output by the 8088 to rhe 8288 if a memory read bus cycle is takingplace? 28. What connand output becomes activeif the statusinpursof the 8288 are 1002? julnp instruction,what queuestatuscode would be output? 29. ff lhe 8088 executes a 30. What signalsare provide.d local bus control in a ma{imum-mode8088 system? for

394

The 8088 and 8086 Micfoprocessors

Chap. 8

Section 8.5
31. ffiat is the range of power suppty voltage over which rhe 8089 is guaranted to work correcily? 32. What is the maxinum valueof volragerhatis considered valid togic 0 ar bit D0 of a the 8088'sdatabus?Assumerhat the oueut is sintdng2 InA. 33, What is the mininum value of voltage that would rcpresenra vatid togic 1 at rhe INTR input of rhe 8088? 34. At what value curent is Volmd measured the 8086? on

Section 8.6
35. At v,hat speeds 8088sgenerallyavaitable? are 36. What frequencycrystal must be connectedberweenihe Xr and X? inputs of rhe clock generator an 8088-2is ro run ai tul1 speed? if 37. What clock ourputsare produce.d the 8284?Wlat would be their frequencies by if a 30-MHz crystal were used? 38. What are the logic levels of the clock waveformsapplied ro the 8088?

Section 8.7
39. How many ciock srares in an 8088 bus cycte that has no wait states? are How are thesestatesdenoted? 40. Wlat is the durationofthe bus cycle for a 5 MHz 8088 that is running at tuI1speed and with no wait stares? 41. What is an idle srate? 42. Wlat is a wait stare? 43. If an 8086running at 10 MHz perfonnsbus cycleswith two wail states, wharis the durationof the buscycle?

Section 8.8
44. How is the memory of an 8088microcompurer organizedfrom a hardware poinr ot view? An 8086 microcompurer? 45, Give an overviewof how a byte of datais readfrom memoryaddrcss B0003t6of an 8088-based microcornpute! and list the memory control signals along with their activelogic leveis that occur during the memoryreadbus cycle. 46. Give an overview of how a word of data is wriften to memory starting ai actdress A000016of an 8088 basedmicrocompute! ,nd tisi the memory conaol signats togetherwith their acrivelogic levelsthat occur dwing the mernorywrite cycle. 47. In which banl of memoryin an 8086-based microconputer areodd-adatressed byres of datastored? Whar bank selectsignalis usedto enablethis bant of memory? 48. Over which of the 8086'sdarabus lines areeven addressed byresof daratransferred and which bank selecrsignal is active? 49, List the memory control signalsrogetherwith their active logic levels that occur when a word of data is writter io memory address A000016 a minimum,mode in 8086microcomputer system.

399

50. List the memory conlrol signals togetherwith their active logic levels that occur when a byte of data is wditen to memory address8000316in a minimum-mode 8086 miffocompurer Over which datalines is the byte of datatransfered?

Section 8.9
51. In a naximum-mode 8088 microcomputer,what code is oulput on SaSrwhen an iDs.ruction'fetchbus cycle is in progress? 52. What is the value of SaS3 the operandof a pop instruction is being read from if memory?Assumethe microcomputer employsthe 8088 in the maximumnode.

S e c t i o8 . 1 0 n
53. mich of dre 8088'smemory control signalsis the complement the correspondof ing signalon the 8086? 54. What memorycontrol ouipur of ihe 8088 is not providedon the 8086! What signal replaces on ile 8086? it 55. In a maxirnum-node 8088 basedmicrocornpuie! what memory bus statuscode is output when a word of instruction code is fetchedfrom memory?Wbich memory control outputG)is (are) Foduced by the 8288? 56. In ma{mun node, what memory bus statuscode is output when a destination operard is writlen to memory?Wlich memory control output(s)is (are) produced by the 8288? 57. When the instruciion PUSH AX is executed,what addressbus status code and memorybuscycle codeare outputby the 8088 in a rnaximum,mode miffocomputer system? Which conlmandsignalsare output by the 8288?

Section i I 8.
58. How mary clock statesare in a readbus cycle that hasno wait states? What would be the duraiion of this bus cycle if the 8086 were operatingat 10 MHz? 59. What happens the TL part of the 8088'smemory reador wrire bus cycle? in 60. Descdbethe bus activity that takesplace as an 8088, in minimurn mode, wites a byte of datainio memory address 8001016. 61. Wtich two signalscan be used to determinethat the current bus cycle is a write 62. Which signalcan be usedto identil' the stmt of a bus cycle?

Section i 2 8.
63. Give an ove iew of the function of each block in the memory interfacediagram shown Fig. 8-24. in 64, When the instructionPUSH AX is executed, what bus statuscodeis output by the 8086 in maximun mode, whal are the logic levels of Ao and BHE, and what rcad/write control signalsaft producedby the bus controller? 65. Wlat type of basic logic devicesis providedby the 74F373? 66. Specilythe logic .ererrol Bl-tLL.lTwRC. raRDC.aodAa $hen rJre 808bIn l-r8. 8 24 rcadsa word of datafrom address12340H.

400

The 8088 and 8086 ^,licroorocessoE Chao. I

67. Make a truth tab1e. using the circuits in Figs. 8 27 and 8 28, to speciryine logic levels of RDu, RDr, wRu, wRb BIIEL, MRDC. MWTC, and AoL when the (a) readsa byte from address 01234H (b) writesa byteto address 01235H (c) reads word from address 01234H a (d) writes a word to address 01234H 68. wlat logic devicesare Fovided by the 74F245? be ro 6c. lD lhe circuirof Fig. 8 30. $ha' logic level.muqr dpptied the DE\ and DT/R inputs to causedata on the systemdatabus to be transferredto the microprocessor 70, MaLe a drawing lite ihat shownin Fig. 8-30 to illustrate the data bus tansceiver microcomputersystem. circuit neededin an 8088-based five chip selectsignals? 71. How nany address iines must be decodedto generate 72. Name an IC that implementsa twoline to tbur-Linedecoderlogic tuncrion. 7 3 . I f l h e i n p u r " r o7 4 F l l 8d e c o d e 'r e a C r LC,^ 0.G.8 0.anaCBq l0l , which output is active! 7,1. MaLe a drawing for a ninimum-mode 8088-base.d microcomputerfor which a decoderis used to generate MEMR and MEMW from the RD, WR, and 74F138 IO,M sigftls.

Section | 3 8.
75. 76. 77. 78. 79. What doesPLA standfor? List tkee properies that measue the capacityof a PLA. wlat is the programmingmechanism usedin the PAL called? What doesPAL standfor? Give the key diftbence betweena PAl- and a PLA. Redmw the circuit Eol,n in Fie. 8-3?(b) to illostrate how it can implement lhe logictunctionF: (AB + AB). input/outpuis.and 80. How many dedicatedinputs, dedicatedoutputs, prograrnmable tems are suppoftedon the 16L8 PAl? Foduct 81. what is the rnarimun numberof inputs on a 20L8 PAL? The maximun Dunber of 82. How do the outputsof dre 16R8differ ftom thoseof the 16L8? addre- line' ArTLLluougn Arqr to generaF Ch through CLa. 83. Usea lol8 ro decode

Section B.l4
84. Name the two types of inpuUoutput. 85. What type of I/O is in use when peripheraldevicesare rnappdto the 8088's l/O address space? space mus.be giYen that 86. Which type of I/O hasthe disadvantage part of the address up to implementI/O ports? ihat 87. wlich type of I/O has the disadvantage all I/O datatransfersmust take place rhrcughthe AL or AX register?

401

8 Section.l5

lires relaiilc to an isoand of St Wr.ata.. tle runctions the 8088s address d'itabus l latedl/O operation to microcompulerwhich lignal indicates Dxremal 89. In a mininun-node 80118 lbr rhe t/O inledaceand nol lhe menory cifcuiry that the curent bus cycle is betweenrhe 8088'snininun-mode l/O inrerlacein Fig' 90. List the differences 8-46(a) andtharofthe 8086in Fig s-46(b) IO/M andM OI rhe beiwecn signals 91. Whatis lhe logic relationship the prcduces input(rexd)output(wnte)' whichdevice svstem' 92. In a m.tiimum-modc Lhe interlace? I/O for .mdbuscontd sign.tls in Fig the Briefly describe functionof eachblock in the I/O inteifacecircuit 93. 817(a). an codeidentifics inputbus what status microcomputer 80i16 94. ln a maximum'node Jrownin l:a c 4-'ur' whJlarethcloSr(levLo,nrerla.e 95. ln rhemax.mum-rn.d< bJ' ara .r' ot ibnC, iOrr,C. atOuC d rins31uurpur clcle'l

8. Section I 6

I/O address'l 96. How manybits arei)r the 8088's spdce? in of 9?, wblt is therange byte addresses lhe 8088'sI/o address I/o in space lermsol wotd-wide porls? 98. What is the sizeof ihe 8086'sI/o 0ddrss ol whatArethe logic levels Ao 4ndBHE syslem, lnicrocomPuter 99, ln rn 8086-based If A00016l a word of dalais addrcss *lr"n o tyr" ul aomis beilu writtento l/O A000r6? beingwriltento address how mrny buscyclesare I equired outputa $yslem, 100. In an 8088microco[]puter -to system? microcomputef In AOO0ld? aI1801t6 wordof datato I/O address

8 Section.l7

IN by perforned the instfuction AX' 1AH the 101, Describe operalion as operution thatof theinstruc to sequence pedbrn the same 102. Write an instluclion I/O or tion in problem101.but this tinreusevariable indirec! OUT 2AH AL' pertbrncdbv the instruction 103. Delcribethe operation the that sequence outputs byie of dala0Fr6to an dutpulpod at 104. Write an insirltction 10006 address inputpofs at l/O that of 105. Write a sequencc insructions inputsthebvteof darafion1 the and saves sun in thesevaluestogether' adds and A.OOO* 800016. aaaresses lO lnemorylocation SUM. p rl ' n un W r : r e Je q u e r t r \ 'io l' r r t r c L rr h l 'r r l i n T ulrn c c o n l e n l ' oh e i n p J l o n a r l / O 106. hd l h eL r b e l v i d o d r e '8 0 J n Jj l m p r o r h eh ( e r n r gr o J e n h ( r o J l i n ed e n l i h < " bit ACTIVE INPUT if the lcastsignilicanl of the datais I

4|J2

The 8088 and 8086 Microprocesso6

Chap S

Section 8.l8
10?. In the 8088's input bus cycle, during which T siate do the IO/M, ALE. m. and DEN control signalsbecomeactive? 108. During which T statein the 8088'sinput buscycle is the ad&essoutputon the bus? Arc darareadftom the busby rhe MPU? 109. If an 8088is midne at 5 MHz, wharts tte durationof the outputbusoperationperlbrmed by executingthe insEuctionOUT 0C0H, AX? 110. If an 8086 running at l0 MIIZ tusertstwo wai. statesinto aI UO bus cycles,what is the duation of a bus cycle in which a byte of daia is being output? 111. If the 8086 h problem 110 ouFuis a wod of dala to a \yod-wide porr ar I/O address1A116, whar is the dumrion of the bus cycle?

4|)3