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Product specification
IRF840
SYMBOL
d
GENERAL DESCRIPTION
N-channel, enhancement mode field-effect power transistor, intended for use in off-line switched mode power supplies, T.V. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching applications. The IRF840 is supplied in the SOT78 (TO220AB) conventional leaded package.
PINNING
PIN 1 2 3 tab gate drain source drain DESCRIPTION
SOT78 (TO220AB)
tab
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total dissipation Operating junction and storage temperature range CONDITIONS Tj = 25 C to 150C Tj = 25 C to 150C; RGS = 20 k Tmb = 25 C; VGS = 10 V Tmb = 100 C; VGS = 10 V Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 500 500 30 8.5 5.4 34 147 150 UNIT V V V A A A W C
13 8.5
mJ A
1 pulse width and repetition rate limited by Tj max. March 1999 1 Rev 1.000
Philips Semiconductors
Product specification
IRF840
ELECTRICAL CHARACTERISTICS
Tj = 25 C unless otherwise specified SYMBOL PARAMETER Drain-source breakdown voltage V(BR)DSS / Drain-source breakdown Tj voltage temperature coefficient RDS(ON) Drain-source on resistance VGS(TO) Gate threshold voltage gfs Forward transconductance IDSS Drain-source leakage current V(BR)DSS IGSS Qg(tot) Qgs Qgd td(on) tr td(off) tf Ld Ld Ls Ciss Coss Crss CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 0.25 mA MIN. 500 2.0 3.5 TYP. MAX. UNIT 0.1 0.6 3.0 6 1 40 10 55 5.5 30 18 37 80 36 3.5 4.5 7.5 960 140 80 0.85 4.0 25 250 200 80 7 45 V %/K V S A A nA nC nC nC ns ns ns ns nH nH nH pF pF pF
VGS = 10 V; ID = 4.8 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 4.8 A VDS = 500 V; VGS = 0 V VDS = 400 V; VGS = 0 V; Tj = 125 C Gate-source leakage current VGS = 30 V; VDS = 0 V Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 8.5 A; VDD = 400 V; VGS = 10 V VDD = 250 V; RD = 30 ; RG = 9.1
Measured from tab to centre of die Measured from drain lead to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
March 1999
Rev 1.000
Philips Semiconductors
Product specification
IRF840
PD%
PHP6N60
0.1
P D
tp
D=
tp T t
20
40
60
80 100 Tmb / C
120
140
0.001 1us
10us
100ms
1s
30 25 20 15
20
40
60
80 Tmb / C
100
120
140
30
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 10 V
ID / A
S/ ID
100
BUK457-500B
10
S RD
(O
N)
VD
tp = 10 us 100 us
1.5
6.5 V 7V
10 V
1 ms 1 DC 10 ms 100 ms
0.5
20
25
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
March 1999
Rev 1.000
Philips Semiconductors
Product specification
IRF840
25
PHP8N50
4
VGS(TO) / V max.
20
3 typ.
15
min. 2
10
1
5 Tj = 150 C 0 0 Tj = 25 C
10
-60
-40
-20
20
40 60 Tj / C
80
100
120
140
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS
ID / A SUB-THRESHOLD CONDUCTION
10
1E-01
1E-02
1E-03
2%
typ
98 %
1E-04
1E-05
1E-06
20
25
2 VGS / V
10000
2
Ciss 1000
1
100 Coss
Crss
10
1000
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
March 1999
Rev 1.000
Philips Semiconductors
Product specification
IRF840
20
PHP8N50
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHP8N50E
15
10 150 C 5 Tj = 25 C
20
60
80
0.2
1.2
1.4
1000
100
td(off)
1
VDS
tp ID
0.1 1E-06
Fig.17. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tp); unclamped inductive load
10
1
1 0.95 0.9 0.85 -100
125 C
0.1
1E-05
1E-03
1E-02
Fig.18. Maximum permissible repetitive avalanche current (IAR) versus avalanche time (tp)
March 1999
Rev 1.000
Philips Semiconductors
Product specification
IRF840
E P
A A1 q
D1
L2(1)
L1 Q
b1
3
b c
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 4.5 4.1 A1 1.39 1.27 b 0.9 0.7 b1 1.3 1.0 c 0.7 0.4 D 15.8 15.2 D1 6.4 5.9 E 10.3 9.7 e 2.54 L 15.0 13.5 L1 3.30 2.79 L2 max. 3.0
(1)
P 3.8 3.6
q 3.0 2.7
Q 2.6 2.2
Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC TO-220 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11
March 1999
Rev 1.000
Philips Semiconductors
Product specification
IRF840
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
March 1999
Rev 1.000
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