8051 Interfacing: Address Map Generation

EE4380 Fall02 Class 6

Pari vallal Kannan

Center for Integrated Circuits and Systems University of Texas at Dallas

8051 Interfacing
Address Mapping
Use address bus and data bus Interfaced device show up as memory locations from the processor They use up some of the address space Memories, displays etc

I/O Mapping
Connect the devices to the I/O Ports of the processor Dont use up address space Sensors, pushbuttons, LCDs, motors, LEDs etc

12-Sep-02

8051 Address Generator

Address Generator is a piece of hardware that produces unique addresses to each interfaced device Each Interfaced Device can use up 1 or more locations from the address space of the processor
Memories typically use up in Other devices typically use a

A[15:0] f1 Addr. Gen f3 8051 D[7:0] f2

Device 1

Device 2 A[15:0] D[7:0] D[7:0] Device 3

Kilobytes (2K, 4K, 8K etc) few (<16) addresses

CE CE CE

Addresses of devices should not overlap

A[15:0] A[15:0] D[7:0]

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What is needed ?
Need to know the following for all the devices before address generator can be designed
Base address of each device Where it starts in the address map Size of the device How much of the address space it uses up
Code RAM 4K RAM1 32K 0x1000 Code ROM1 4K0x5000 0x0000 0x4000 Code Memory Data Memory

LCD 8b LEd 2b

0x0000 0x8000 0xF000

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Example 1 : 2K Memory at 0x0000

Pins : address - A10 to A0, Data D7 to D0, _RD, _WR, _CE Base address = 0x0000 Size = 2k (2 *1024 = 2048 bytes = 0x0800) Address Map occupancy
0x0000 to 0x07FF that is, 0000 - 0000 - 0000 - 0000 binary to 0000 - 0111 - 1111 - 1111 binary

11 lowest address bits A10 to A0 have to be connected to the address pins on the memory
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Example 1 : (contd.)
Unused address bits are
A15 to A11

Truth-Table for CE
A15 A14 A13 A12 A11 0 0 0 0 0 X X 1 X 1 1 X 1 1 X X _CE

X X X X CE is active low X X _CE = A15 + A14 + A13 X + A12 + A11

Then connect _RD and _WR

Base address is 0x0000 CE has to be generated if all the unused address bits are logic-0

X X X X X X X

0 1 1 1 1 1

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Ex-2: Same Memory at 0x4000

Base address is 0x4000
0100 0000 0000 0000
A15 A14 A13 A12 A11 X 0

Size is 2K Unused address bits

A15 to A11

CE has to be generated as per the truth-table Expression is

X X X and X

0 1 1 1 so 1 1

_CE

X X X on X

X 0

X 0

X X 1 1

0 0 1 0 1

_ CE = A A A A A11 15 14 13 12
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1 0 1 1 1 1 1 1 1

(In)Complete Addressing
Complete addressing:
Use all unused address bits to generate CE

Incomplete addressing
Use a sub-set of the unused address bits Used to reduce the address generator complexity Produces address aliases (same device at multiple addresses)

Example
2K memory at 0x0000, we used A15 to A11 Instead just connect A11 to _CE Same 2K memory device will then be aliased for all values of A15 to A12 0x0000, 0x1000, 0x2000, 0x3000, . , 0xF000 Address generator became very simple, but we lost a lot of address space
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74138 Decoder for Address Gen.

3 to 8 decoder, available in a single DIP package. Takes 3 address lines and generates complete addressing among those Example
Connect A15, A14, A13 to the
A15 A14 A13

C B A
G2 G1

Y0 Y1 Y2

GND Vcc

decoder inputs addresses for

Y7 74LS138

Decoder outputs give base

0x0000, 0x2000, 0x4000, 0x6000, 0x8000, 0xA000, 0xC000, 0xE000

For more complicated address decoding use programmable devices like PALs, PLDs or FPGAs
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External (pure) Code Memory

Could be RAM or ROM Address generation as per standard procedure Connect _PSEN to the _OE of the memory device _RD and _WR are ignored
Dont connect these 8051 pins to the memory device

Connect Data bits D7-D0 of the memory and the 8051

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External (pure) Data Memory

Could be RAM or ROM Address generation as per standard procedure Connect _RD from the 8051 to OE of the memory Connect _WR from the 8051 to WR of the memory Ignore _PSEN Connect Data bits D7-D0 of the memory and the 8051

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External Code + Data Memory

Could be RAM or ROM Address generation as per standard procedure Logically AND _PSEN and _RD and then connect to the OE of the memory Connect _WR from the 8051 to WR of the memory Connect Data bits D7-D0 of the memory and the 8051

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External Non-Memory Devices

Same procedure as for interfacing memory Only difference is that these devices have smaller sizes and use lesser portions of the address space Example:
8 LEDS connected to a 8bit latch. The latch is address mapped to 0xF000. Size is 1byte 8255 I/O device memory mapped at 0xD000. Size is 4 bytes

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Case Study - Sample 8051 System

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Case study Sample 8051 System

8031 based
No on-chip ROM, 128 bytes on -chip RAM, 18.432MHz oscillator,

74HC373 based ADBUS demuxer

SRAM and EEPROM share code memory space. So decoding needed.

A15 line is used for the purpose A15 = 0 EEPROM is selected (hence 0x0000) A15 = 1 SRAM is selected (hence 0x8000)

8Kx8 external code memory in 28C64 EEPROM Code memory at 0x0000 32Kx8 external code+data overlapped in 62256 SRAM. SRAM mapped at 0x8000

RS232 serial interface available for PC communication Monitor programs available

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Next Class Reverse Engineering

8051 a system with little or GivenI/O Mapped interfacingno docs, determine 8051 and the 8255 I/O device the function, schematic, etc Example Interfacing a character LCD Vendors provide poor support. Reverse Engineering is fun ! Usually No schematics are available Software is also undocumented ! On-chip code could be copy protected !!

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