Fault M d li F lt Modeling & Si Simulation l ti

Virendra Singh
Indian I tit t f S i I di Institute of Science Bangalore virendra@computer.org E0 286: Test & Verification of SoC Design Lecture - 3
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VLSI Testing

Fault Equivalence
Number of fault sites in a Boolean gate circuit = #PI + # t #gates + # (f (fanout b t branches). h ) Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also q detect f2. If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, subsets where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset. subset
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Equivalence Rules
sa0 sa0 sa1 sa1 sa0 sa1 sa0 sa1

AND
sa0 sa1

sa0 sa1 sa0 sa1

OR

sa0 sa1

WIRE

sa0 sa1 sa0 sa1 sa0 sa1

NOT

sa1 sa0

NAND
sa0 sa1

0 1 sa0 sa1 sa0 sa1

NOR

sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1

3

FANOUT
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Equivalence Example
sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 0 1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 20 Collapse ratio = ----- = 0.625 32
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sa0 sa1

sa0 sa1 sa0 sa1 sa0 sa1

sa0 sa1

Faults in red removed by equivalence collapsing

sa0 sa1

sa0 sa1

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Fault Dominance
If all tests of some fault F1 detect another fault F2, then F2 i said t d F2 th is id to dominate F1 i t F1. Dominance fault collapsing: If fault F2 do dominates F1, then F2 is removed from the ates ,t e s e o ed o t e fault list. When dominance fault collapsing is used, it is sufficient to consider only th i ffi i t t id l the input f lt of t faults f Boolean gates. See the next example. In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set. If two faults dominate each other then they are equivalent. i l t
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Dominance Example
F1 s-a-1 All tests of F2 F2 s-a-1 110 101 001 000 100 010 011

s-a-1 s-a-1

Only test of F1

s-a-1 s-a-0 A dominance collapsed fault set

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Checkpoints
Primary inputs and fanout branches of a combinational circuit are called checkpoints. Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit.
Total fault sites = 16 Checkpoints ( ) = 10

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Multiple Stuck-at Faults

A multiple stuck-at fault means that any set of lines is stuck at some combination of (0 1) stuck-at (0,1) values. The total number of single and multiple g p stuck-at faults in a circuit with k single fault sites is 3k-1. A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare. Statistically, single fault tests cover a very large number of multiple faults faults.
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Transistor (Switch) Faults

MOS transistor is considered an ideal switch and two types of faults are modeled:
Stuck-open -- a single transistor is permanently stuck in the open state state. Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage.

Detection of a stuck-open fault requires t D t ti f t k f lt i two vectors. Detection of a stuck-short fault requires the stuck short measurement of quiescent current (IDDQ).

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Stuck-Open Example
Vector 1: test for A s-a-0 (Initialization vector) pMOS FETs s 1 0 0 0 Vector 2 (test for A s-a-1)

VDD

A B

Stuckopen

Two-vector s-op test can b constructed b be t t d by ordering two s-at tests

1(Z) Good circuit states

nMOS FETs
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Faulty circuit states

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Stuck-Short Example
Test vector for A s-a-0 pMOS FETs s 1 0

VDD
Stuckshort

A B

IDDQ path in faulty circuit

Good circuit state 0 (X)

nMOS FETs
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Faulty circuit state

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Fault Model - Summary

Fault models are analyzable approximations of defects and are essential for a test methodology. For digital logic single stuck-at fault model offers best advantage of tools and experience. Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. Stuck-short and delay faults and technologydependent faults require special tests. Memory and analog circuits need other specialized fault models and tests tests.
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Fault Simulation

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Simulation Defined
Definition: Simulation refers to modeling of a design, its function and performance. A software simulator is a computer program; an emulator is a hardware simulator. Simulation is used for design verification:
Validate assumptions Verify logic Verify performance (timing) Logic or switch level Timing Circuit Fault

Types of simulation:

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Simulation for Verification

Specification Synthesis Response analysis y Design changes g Design ( (netlist) )

Computed responses

True-value simulation

Input stimuli

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Modeling Levels
Modeling level Function, behavior, RTL Logic Circuit description Programming language-like HDL Connectivity of Boolean gates, flip-flops and transistors Transistor size and connectivity, node capacitances Signal values 0, 1 0, 1, 0 1 X and Z Timing Clock boundary Zero delay Zero-delay unit-delay, multipledelay Zero-delay Application Architectural and functional verification Logic verification and test Logic verification g Timing verification Digital timing and analog g circuit verification
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Switch S it h

0, 0 1 and X

Timing Circuit

g gy Transistor technology Analog voltage data, connectivity, node capacitances Tech. Data, active/ passive component connectivity Analog voltage, voltage current

Fine-grain g timing Continuous time

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True-Value Simulation Algorithms Al ith

Compiled-code simulation p
Applicable to zero-delay combinational logic Also used for cycle-accurate synchronous sequential g circuits for logic verification Efficient for highly active circuits, but inefficient for low-activity circuits High-level (e.g., C language) models can be used Only gates or modules with input events are g g evaluated (event means a signal change) Delays can be accurately simulated for timing verification Efficient for low-activity circuits Can be extended for fault simulation
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Event-driven simulation

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Compiled-Code Algorithm
Step 1: Levelize combinational logic and encode in a compilable programming language Step 2: Initialize internal state variables (flipp ( p flops) Step 3: For each input vector Set i S t primary i input variables t i bl Repeat (until steady-state or max. iterations)
Execute compiled code

Report or save computed variables

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Thank You
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