Signed Multiplication

Sign and magnitude representation: Calculate unsigned product as |p| = |x| |y| p0(2n2) = x0(n2) y0(n2) determine sign separately as sgn(p) = sgn(x) sgn(y) p2n1 = xn1 yn1 More difcult if 2s complement is used: use 2s complement of negative multiplicand for summing up partial products sign extension is needed

Example:
Multiplicand:

(5) (+6) = (30)

Disadvantages:
1. Sign-extension for negative multiplicands not applicable for negative multipliers 2. long sequences of 1s in the multiplier large number of summands

Unsigned 0 1 0 1 1s complement 1 0 1 0 2s complement 1 0 1 1 0 1 0 0 1 0 0 0 1 0 0 1 0 1 1 0 1 1 0 1 0 0 1 0 0 0 0 0 Multiplicand Multiplier 0000 x1011 0010 x1011 0100 x1011 0000 x1011
(carry)

Solution for problem 1.: in case of a negative multiplier, negate both operands by applying the 2s complement Solution for problem 2.: analyze groups of 1s in the multiplier and replace them by a shorter and more efcient representation (Booth algorithm)

0 1 1 0

0 1 1 0

0 1 1 0

1 1 1 1 1 0 0

1 1 1 0 0 0 1 0

Product

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Booth Algorithm
Based on the observation that
n

Booth Recoding
Consider the example of encoding 56:

Booth Recoding
1. Parse multiplier from left to right (i = n1 0) 2. for each change from 0 to 1 or vice versa, encode 1: if bit i is 0 and bit i1 is 1 recode to +1 if bit i is 1 and bit i1 is 0 recode to 1 3. for bit 0, assume bit i = 1 with value 0 During the multiplication: the multiplicand is added for +1 digits the 2s complement is added for 1 digits

X2
1
i=0

= 2n

27 26 25 24 23 22 21 20 0 0 1 1 1 0 0 0 0 +1 0 0 1 0 0 0 25 + 24 + 23 = 32 + 16 + 8 = 56 26 23 = 64 8 = 56

Generate sequence of 1s in bits j to k by subtraction of two operands with single 1 each: 1000 (8) 0001 (1) 0111 (7) 01000000 (64) 00001000 (8) 00111000 (56)

This method works equally well for both unsigned and 2s complement representations

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Booth Algorithm and Bit Pairing

The Booth technique has its major advantage if 1. the operands have a large number of bits 2. multiplier contains long sequences of 1s it has its limitations if the multiplier contains only small groups of 1s or even alternating 01 pairs It can be enhanced by bit-pairing, 50% maximum number of summands handling 01 pairs efciently additional overhead for multiplicand

Bit-Pairing of Booth Recoding

Apply Booth recoding on the multiplier rst, then pair bits 1. Within a sequence: 0 0 0
Bit-Pair Booth Recoding Examples

1 +1

0 0

1 1 0 0 0 1 1 1 1 1 Good multiplier: 0 0 0 0 0 1

1 +1

+1

+1

1 +1

0 0

+1

1 +1

+1

1 +1

0 +2

1 +1

Worst-case multiplier: 0 1 0 1 0

1 +1

0 +1 +1

+1 1 +1

+1

+1

+1

0 +2

3. End of a 1s-sequence: 0 1 1 1 +1 1 1 0 2

+1

Ordinary multiplier: 1 1 0 0

1 +1

+1

1 +1

+1

+1

1 1

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Conclusions for Booth Algorithm

Booth algorithm can reduce number of nonzero summands considerably Worst case: May double the number of non-zero summands Bit-pairing can reduce the number of summands further . . . wont help if multiplier is optimal after conventional Booth recoding For the sequential shift/add hardware, bitpairing reduces the summation effort substantially, with or without Booth recoding

Division
1. Align dividend and divisor with their most signicant digits 2. test how many times n the divisor ts into the locally aligned dividend 3. n is the value of the quotient digit 4. subtract divisor n times from the locally aligned dividend 5. extend local remainder by the next less signicant digit of the dividend, thus forming a new local dividend 6. repeat steps 2. 5. until all digits of the dividend are considered 7. the local remainder after the last subtraction is the remainder of the division

Example (decimal):
1 1 9 1 3 6 6

195 13 = 15

Divisior 1 3

5 5 5 5 0

Quotient Dividend

Remainder

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0 0

+1 +1

0 0

0 0

0 0

2. Begin of a 1s-sequence:

+1

0 2

0 0

+1

0 +2

1 1

1 1

Example (binary):

19 6 = 3 rem 1

Sequential Restoring Division

A shift register keeps both the (remaining) dividend as well as the quotient with each cycle, dividend decreases by one digit & quotient increases by one digit the MSBs of the remaining dividend and the divisor are aligned in each cycle

Sequential Restoring Division

1. Load the 2n dividend into both halves of shift register, and add a sign bit to the left 2. add a sign bit to the left of the divisor 3. generate the 2s complement of the divisor 4. shift to the left 5. add 2s complement of the divisor to the upper half of the shift register including sign bit (subtract) 6. if sign of the result is cleared (positive) then set LSB of the lower half of the shift register to one else clear LSB of the lower half and add the divisor to upper half of shift register (restore) 7. repeat from 4. and perform the loop n times 8. after termination: lower half of shift register quotient upper half of shift register remainder

6 110

1 0 1

0 0 0 1 0

0 0 0 0 1 1 1 0

1 1 1 1 1 0 1 1 1 0 0 1

3 19

major difference to multiplication: 1. we do not know if we can subtract the divisor or not 2. if the subtraction failed, we have to restore the original dividend

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Sign

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0 1 0 1 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 0 1 0 1 1 1 1 1 0 1 0 0 1 1 1 0 0
ADD

6 = 13

0 1 0 0 1 0 0 0 0 1 0 0 0 0

Divisor 2s Complement

1 1

1 1 1 0 0 1 1

1 0 0
Set 1

0
Shift Left

Dividend

0 1

(Remainder) | (Quotient) SUB

Test = 0 (positive)

Shift Left

1 1
Set 1

0
SUB

1
Shift Left

Test = 0 (positive)

1 1
Set 0

0
SUB

Test = 1 (negative)

Restore

0 1 1

1 1 1

1 0 0
Set 1

0
Shift Left

0
SUB

1
DONE

Test = 0 (positive)
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