Fabrication of CMOS Devices

Vocabulary: Wafer disk of silicon, 4" to 8" in diameter, < 1mm thick, cut from ingots of single-crystal silicon which are "grown" from a pot of melted silicon. Impurities in melt determine n- or p-type material. Single-crystal means that the crystalline structure is the same throughout careful growing process ensures this. Wafers are very brittle, the larger the diameter, the more susceptible to damage. Surface of the wafer is polished to a very flat, scratch free surface. Oxidation used to deposit Silicon Dioxide (SiO2) on surface of wafer to be used as insulting material - heat wafers inside of an oxidation atmosphere such as oxygen or water vapor. Need to introduce dopants into the silicon wafer. Epitaxy grow single crystal film of the required dopant on silicon surface by heating wafer and exposing it to a source of the dopant. Deposition evaporate the dopant onto the surface, then heat the surface to drive the impurities in the wafer Ion implantation expose surface to highly energized dopant atoms - when they hit the surface, they travel below the surface and become trapped Need to control the regions in which the dopants get introduced - want to block some regions from receiving dopants. Uses masks to block the impurities in particular regions. To create mask: (a) deposit mask material over entire surface (b) cut windows in the mask to create exposed areas (c) deposit dopant (d) remove unrequired mask material

How do you pattern the mask material?

(a) Put a positive photoresist material on top of the mask material. photoresist breaks down when exposed to ultraviolet (UV) light. Positive

(b) Expose wafer to UV light. Block areas of the wafer from UV exposure via a mask on a glass plate. Exposed photoresist will be weakened. (c) Put wafer in chemical bath to wash away exposed photoresist (called "etching" or "developing" the photoresist. (d) Bake the wafer (Hard Bake). Photoresist + mask material combine to produce a material more resistant to etching then just the plain mask material. (e) Etch the mask material via a chemical bath areas not protected by the hardened photoresist will be washed away. Finished! Now have patterned mask material on wafer surface this will now block area of the surface from dopants.

Another way to pattern the mask Electron Beam Lithography which directly cuts areas in mask material. (1) Do not have to make a mask for the UV light these are expensive, also errors can occur in making the mask dimensions which can cause problems down the road. (2) Can make changes to the pattern quickly, draw very fine lines. Main disadvantage slow, electron beam has to "draw" over surfaces it wants to cut; time is proportional to complexity of mask pattern.

Back to UV masks
Two methods for using the UV masks: (1) Step and Repeat one mask the size of the chip is made, this is placed over a region of the wafer and exposed to UV light. Then, move mask to next region and repeat. (a) Only need one mask, mask cost low (b) slow (2) Full wafer mask, make a mask the size of the wafer in which the "chip" mask is repeated many times (a) Full wafer mask is expensive (b) Fast processing, can expose entire wafer at once

Where are we going with this?

In the above picture: (a) Poly Gate (labeled poly 1 above) (Gate is made of polycrystalline silicon which is made up of multiple crystal structures, not a single crystal like the substrate.) The poly is very heavily doped to be n+ so that it is a good conductor. (b) Channel implant used to adjust threshold voltage (c) Aluminum used for metal layer(s) not show in this picture (d) Field oxide is much thicker than gate oxide ("thin ox") used to isolate active areas.

VLSI Fabrication Steps

What are the Layers? and Structures?

Process Cross-sections
Mask Layouts Symbolic Layouts

Field Oxide Gate Oxide

n-well n+/p+ Diffusion Polysilicon Metal 1 Metal 2

n-well
active n+ select or n+ diffusion p+ select or p+ diffusion
Contacts (poly, n+, p+)

n+ wire or transistor

p+ wire or transistor

Polysilicon Contact Metal 1

Via Metal 1

Via Metal 2
Via 2
Via 2 Metal 2

Metal 3
Metal 3

Diffusion areas are where n+, p+ have been introduced to form source, drain, and well-contacts areas. "Active" refers to any area which will be exposed to any n+, p+ dopants, or channel areas. Channel areas formed by polysilicon ("poly") crossing diffusion area. Area under the poly is the transistor channel. Many different contact types - metal 1/diffusion, metal 1/poly, metal 1 to metal 2 (via), metal 2 to metal 3 (via 2). A structure is a combination of basic layers to form a commonly used item (nMOS transistor, pMOS transistor, diffusion contact, poly contact, etc.).

CMOS Process Enhancements

Interconnect! The more layers of interconnect, the less area a layout will take. Solution #1 - add more layers of metal Three layers of metal are very common. In advanced processes, it is not uncommon to have 4 or 5 layers of metal. Con more layers, more expensive processing, lower yields (more processing steps lower yields) Solution #2: Make the poly layer a better conductor by lowering its resistance. Typical resistance 20 to 40per square. Aside: Compute resistance by the "square" to find the total resistance end-to-end.
2

squares of poly

7 squares; if 30/sq. then Rend-to-end = 30 7 = 210. More on this later . . .

How can we make polysilicon less resistive? Combine it with a metal! (or use a metal for the gate).
Silicide n+ SiO2 n+ Silicide n+ Polysilicon Silicide n+ Silicided S/D p-substrate Self-aligned Polysilicon/ Silicide Gate (Salicide) Polysilicon

p-substrate Silicide Gate

p-substrate Polysilicon/ Silicide Gate (Polycide)

(a)

(b)

(c)

Cross-section (a): Gate is made of a silicidepolysilicon combined with tantalum (other metals can be used). Sheet resistance 1 to 5 per square Cross-section (b): Gate is a sandwich of silicide with polysilicon. Cross-section (c): Source and drain regions are also a silicide!! Allows direct connection between gate and source/drain regions without using metal interconnect - reduces area!! Referred to as "local interconnect"

Local Interconnect example

Shown below is a memory cell example. Remember, AREA is very important!!! This example illustrates use of silicided source/drain regions. Consequently, this type of interconnect reduced area by 25%.
metal VDD

Mp2

local interconnect
poly Mp1

VDD Mp2
local interconnect

local interconnect

Mp1

local interconnect (not shown)

word

bit

bit

Layout Design Rules

Visit URL address http://www.mosis.org/Technical/Designrules/scmos/ for CMOS layout design rules used during the laboratory exercises.

Circuit Elements
Resistors: 1. Doped polysilicon 20 to 40 /square 2. Undoped polysilicon can be used to make tera resistors (tera = 1012) must prevent resistor areas from being doped, i.e., additional mask needed 3. Resistive metal nichrome, k/square 4. Diffusion 100/square Difficult to build resistors to an exact value because the exact sheet resistance can vary considerably from one batch of wafers to another. So, use circuits which require resistance ratios instead of exact resistance values (if you cannot avoid using resistors in your design).

2R 2x length 1x length

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No matter what the exact resistance of each segment, the ratio will be 2/1. Use laser trimming if exact resistance is needed. Note, this option is not available in standard digital CMOS technology. Aside: for better 2R, R matching (and therefore more accurate 2R/R ratio),

x length

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Capacitors
Example: two layers of poly
poly2 contact poly1 poly2

tox
poly2 poly1

tox

poly1 contact

Cross section of capacitor's "active" area

Top view of poly-poly capacitor

MOSIS offers an "analog" process that has two layers of poly. Good capacitors are very important in analog circuits like op-amps, switched-capacitor filters, sample & hold circuits, etc. Again, very difficult to build exact capacitance values so build circuits which rely on ratios of capacitance values. Trench capacitors are used in DRAM processes. This application requires lots of capacitance, 100fF (femto = 10-15) in an extremely small area. Note, this is a 3-dimensional structure. 3D structures are becoming more important when trying to achieve ultra-high density (high-memory capacity/chip area).

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metal bit line poly word line

bit line access transistor

n+ p+

n+

SiO 2

n+ p+
word line trench capacitor VDD/2

polysilicon cell plate (connected to VDD/2)

p+

Cross section

Schematic

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Latchup
Latchup is a parasitic effect in CMOS that causes a low resistance path between VDD and GND (or VSS) which results in chip destruction or system failure (power cycle required to clear). Very bad in early CMOS processes inhibited acceptance of CMOS as a mainstream technology. CMOS Inverter cross-section with parasitic BJTs and resistors:

Illustration of how the latch-up circuit might be activated:

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Latch-up mechanism: 1. NPN turns on when substrate becomes 0.7V higher than nMOS source (emitter). This can happen when the inverter switches very rapidly and the pulse fed through C2 forward-biases the base-emitter junction of the NPN (Q2). Similarly, a pulse fed through C1 might turn-on Q1. 2. Once NPN turns on (for example), note that emitter current increases exponential with VBE (voltage drop across substrate resistor RS2). 3. Then current flows through the parasitic n-well resistors. This will eventually turn on the parasitic PNP (voltage drop across RW1 = VEB of Q1). 4. As PNP turns on, the NPN base current increases and voltage drop across RS1 also increases, further increasing the NPN emitter current (Q2 turns on harder), which further increases the PNP base current, which again further increases NPN base current, .... Positive feedback!!! Current reaches destructive levels. One way to prevent latch-up is to keep the p-substrate tied very closely (i.e., close proximity) to GND (most negative supply) to reduce substrate resistance (RS1 & RS2), and the n-well tied very closely to VDD to reduce RW1 & RW2. Rules: 1. Each well must have a substrate contact of appropriate type (n-type for nwell). 2. Place substrate contacts as close as possible to the source connection of transistors connected to the supply rails. Very conservative one well contact for every source connection to a supply rail Less conservative one well contact to every 5-to-10 transistors External I/O conditions can help trigger latch-up via undershoot or overshoot of supply voltages I/O circuit design is important in

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combating this problem. Some output drivers are all nMOS to avoid latch-up problems.

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Silicon on Insulator (SOI)

Salient features of SOI: substrate is an insulator eliminates latchup because there are no parasitic devices lower substrate capacitances offer higher speed circuits n-/p-type transistors can be placed closer to each other because there are no wells Enhanced radiation tolerance (no stray substrate currents due to radiation effects) Note: latchup immunity and radiation "hardness" are SOI's most important features Insulting substrate can be implemented using Sapphire. "Islands" of n/p material formed on insulting substrate are used to make n-type and p-type MOSFETs. Processing steps:

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1.)
nSapphire (in this example of SOI) <100> Oriented Silicon

2.)
n-

Photoresist SiO 2 Si Sapphire

3.)
nnBoron Implant

4.)
pphotoresist Phosphorous implant n-

photoresist

5.)
pn-

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The formation of n-/p-type transistors on the silicon islands is shown below. An alternative type of insulting substrate is two layers of single crystal Si with SiO2 between them.
polysilicon thin oxide n-island n-

6.)
p-

sapphire

polysilicon

7.)
pn-implant (Phosphorous) photoresist n-

thin oxide n-island

sapphire

8.)
nn+ pn+ sapphire photoresist p-implant (Boron)

9.)

n+

p-

n+

p+

n-

p+

10.)

gate p-glass source drain

gate drain source

n+

p-

n+ sapphire

p+

n-

p+

nMOSFET

pMOSFET

SOI devices mainly used in space applications because of its enhanced radiation tolerance. One problem is that the insulator substrates (wafers) are more expensive than silicon counterparts, processing techniques are not as developed yet (depending on who you talk to!).

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SOI is slowly becoming more popular.

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Electrically Alterable ROM

inter poly oxide tunnel oxide n+ n+

control gate floating gate

p-substrate

EEPROM programming done electrically, erasing done electrically EAPROM UV light used to erase By manipulating control gate and source/drain voltages, can get electrons from the channel to tunnel through the tunnel oxide and become trapped on the floating gate. When enough electrons are trapped on the floating gate, the gate is programmed and the device is on. To erase, use control gate to drive electrons off of floating gate; can do the same thing by exposure to ultra-violet light.

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Resistance

l R = t w ohms

where = resistivity, t = thickness, l = conductor length, w = conductor width Also can use
l R = Rs w

where Rs = sheet resistance (/sq.) l Independence from w is obtained by measuring sheet resistance by the "square":
w t w w t

1 rectangular block R = Rs(l/w) [] l

4 rectangular blocks R = Rs(2l/2w) = Rs(l/w) []

Typical sheet resistances for conductors:

SHEET RESISTANCE [/SQUARE] Material Intermetal (metal1-metal2) Top-metal Polysilicon Silicide Min. 0.05 0.03 15 2 Typical 0.07 0.04 20 3 Max. 0.1 0.05 30 6

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Diffusion (n+,p+) Silicided diffusion n-well

10 2 1k

25 4 2k

100 10 5k

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