Published in IET Power Electronics

Received on 22nd November 2007

Revised on 21st February 2008
doi: 10.1049/iet-pel:20070023
ISSN 1755-4535
Voltage-lift-type Cu

k converters: topology
and analysis
M. Zhu F.L. Luo
Center of Advanced Power Electronics, School of Electrical and Electronic Engineering, Nanyang Technological University,
Singapore 639798, Singapore
E-mail: zhumiao@pmail.ntu.edu.sg
Abstract: The voltage-lift (VL) technique is an effective method that could be applied in electronic circuit design.
A series of negative output dcdc converters (Voltage-lift-type Cuk converters) applying series Cuk implementing
VL techniques is introduced. Compared with the Cuk converter prototype, these converters can perform positive
to negative dcdc voltage increasing conversion with higher voltage transfer gains. They are different from other
existing dc dc step-up converters and possess several advantages, mainly including fewer switches, clear
conversion processes and a high output voltage with the small ripple. Since the proposed converters avoid
using transformers and cascade connection, the relative simple structures are benecial to potential practical
applications in future. A detailed theoretical analysis for continuous and discontinuous conduction modes is
given. Both simulation and experimental results are provided to verify the main characteristics.
1 Introduction
Dcdc step-up converters are widely used in computer
hardware and industrial applications, such as computer
periphery power supplies, car auxiliary power supplies,
servo-motor drives and medical equipment [1, 2]. The
classical Cu k converter [3] shown in Fig. 1 has many
industrial applications due to its good characteristics. This
topology provides an output voltage with an opposite
polarity to its input voltage. Inductors L and L
1
reduce
EMI problems, and the output ripple is small. Under the
different conditions of duty ratio D, it can perform the
step-down and step-up dcdc conversion due to its voltage
transfer function as
M
C uk

D
1 D
(1)
Because of the effects of parasitic elements, the practical
values of D in (1) have an upper limit and cannot be too
high (usually should not be higher than 0.9). So, the
output voltage and power transfer efciency of the Cuk
converter have been seriously restricted. With the fast
development of technologies, this disadvantage limits the
further applications of Cu k converters in some areas that
require higher voltage transfer gains such as communication
equipment, aerospace electronics, portable devices and IC
chips.
Dcdc converters may be developed by n-cell cascade
connection or by adding transformers to obtain higher
voltage transfer gains [411]. However, the resulting
problems, energy losses, multiple power switches and large
switching surges in transformers signicantly increase the
control complexity and the cost of these converters. In
recent years, advanced dcdc conversion enhancement
techniques such as switched-capacitor (SC) and voltage-lift
(VL) techniques have been greatly explored [1222]. The
main objective is to reach a high efciency, high power
density and simple structures. Since Cu k converters is a
classical topology, the combination with the Cu k prototype
and the above-mentioned enhancement techniques could
be a good solution for promoting its further application. It
is well known that the main advantage of SC techniques is
the absence of inductors, thus making it very small in size
and high in power density. However, more power switches
are required in SC-type converters than in magnetic-based
converters.
178 IET Power Electron., 2009, Vol. 2, Iss. 2, pp. 178191
& The Institution of Engineering and Technology 2009 doi: 10.1049/iet-pel:20070023
www.ietdl.org
The VL technique is an effective method that is widely
applied in electronic circuit design, especially in the radio
engineering. It can also lead to performance and
characteristics improvement of dcdc converters; however,
it differs from current SC techniques. Both inductors and
capacitors play an important role in the VL technique, and
all inner capacitors are fully charged by the power source.
Moreover, fewer power switches (usually single switch or
two synchronous switches) are included in VL-type
structures and avoid those complex multiple-switch control
schemes. So we apply the VL technique to the Cu k
prototype in this paper and develop a new series Cuk
implementing the VL technique. Consequently, a series of
novel negative output VL-type Cuk converters has been
successfully created.
The proposed VL-type Cuk converters are different from
any other existing dcdc step-up converters and possess
above-mentioned advantages as well as primary advantages
in the Cu k prototype. They are categorised into the
elementary self-lift circuit, the developed self-lift circuit,
the re-lift circuit and multiple circuits (e.g. triple-lift and
quadruple-lift circuit). All circuits perform positive to
negative dcdc voltage increasing conversion with higher
voltage transfer gains, small ripple and high efciency in
simple structures. Therefore they will be used in computer
peripheral equipment and industrial applications, especially
for high output voltage projects. The detailed analysis will
be performed in the following sections.
For any component X in this paper, its instantaneous
current and voltage are expressed as i
X
and v
X
. Its average
current and voltage during a switching cycle in the steady
state are expressed as I
X
and V
X
. All reference directions
of currents and voltages can be referred to in the corresponding
gures. For general description, each component is ideal and
the output power is equal to the input power, V
o
I
o
V
in
I
in
.
Any parameter with the subscript B indicates the boundary
values between continuous conduction mode (CCM) and
discontinuous conduction mode (DCM). The symbols 1, z
and j are dened as output voltage variation ratio, inductor
current variation ratio and diode current variation ratios,
respectively.
2 Elementary self-lift circuit
The circuit existing in the pump section is the core part for a
dcdc converter. Applying the VL technique to the pump
section can achieve its evolution. The elementary self-lift
circuit as shown in Fig. 2a is derived from the Cuk
converter prototype by adding two components (diode D
1
and capacitor C
1
) into the pump section. The equivalent
circuits during switching-on, switching-off and DCM are
shown in Fig. 2b2d, respectively. When switch S turns
on, D
1
is on, and D
f
is off. When S turns off, D
1
is off,
and D
f
is on. C
1
performs characteristics to lift the output
capacitor voltage V
Co
by the capacitor voltage V
Cs
.
Furthermore, a P-type low-pass lter C
1
2L
1
2C
o
is
constructed and combined with the pump section.
2.1 Circuit analysis in CCM
Switching diagrams with main steady-state waveforms are
shown in Fig. 3a to analyse the circuit operation, where
reference directions are referred to in Fig. 2a. In the steady
state, the average voltage across L
1
over a period is zero. Thus
V
C1
V
Co
V
o
During the switch-on period, V
C1
is equal to the voltage
across C
s
. Since C
s
and C
1
are sufciently large, we have
V
Cs
V
C1
V
o
Figure 1 Prototype of the Cuk converter
Figure 2 Elementary self-lift Cuk circuit
a Topology
b Equivalent circuit during switching-on
c Equivalent circuit during switching-off
d Equivalent circuit during DCM
IET Power Electron., 2009, Vol. 2, Iss. 2, pp. 178191 179
doi: 10.1049/iet-pel:20070023 & The Institution of Engineering and Technology 2009
www.ietdl.org
The inductor current i
L
increases during switching-on and
decreases during switching-off. The corresponding voltages
across L are V
in
and (V
Cs
V
in
) . Therefore applying the
inductor volt second balance principle to L, we have
DTV
in
(1 D)T(V
Cs
V
in
) or
DTV
in
(1 D)T(V
o
V
in
)
Hence
V
o

1
1 D
V
in
The voltage transfer gain in the CCM is
M
S

V
o
V
in

1
1 D
(2)
Therefore the input current is
I
in

1
1 D
I
o
I
L
I
Df off
(3)
C
o
acts as a low-pass lter so that
I
L1
I
o
(4)
Since the peak-to-peak current variation of i
L
, Di
L
is equal to
DTV
in
=L, the variation ratio of i
L
is
6
L

Di
L
=2
I
L

D
2M
2
S
R
fL
(5)
The peak-to-peak voltage variation ratio of V
C1
, Dv
C1
is
approximate to
Dv
C1

I
o
(1 D)T
C
1
Therefore the variation ratio of V
C1
is
1
C1

Dv
C1
=2
V
C1

1
2M
S
fRC
1
(6)
Because v
o
varies very little, the peak-to-peak current
variation of i
L1
can be calculated by the area A of a triangle
with width T/2 and the height Dv
C1
=2, which is
approximately
Di
L1

(1=2)(DV
C1
=2)(T=2)
L
1

(1 D)I
o
8f
2
L
1
C
1
Therefore the variation ratio of i
L1
is approximate to
6
L1

Di
L1
=2
I
L1

1
16M
S
f
2
L
1
C
1
(7)
The variation of i
Df
is equal to Di
L
during switching-off, so
the variation ratio of i
Df
is
j
Df
6
L

D
2M
2
S
R
fL
(8)
To simplify the calculation, we treat the ripple of i
L1
as a
triangle waveform as shown in Fig. 3a because the ripple of
i
L1
is very small. So the peak-to-peak voltage variation of
v
o
is calculated by the area B, which is approximately
Dv
o

(1=2)(Di
L1
=2)(T=2)
C
o

(1 D)I
o
64f
3
L
1
C
1
C
o
Therefore the variation ratio of v
o
is approximate to
1
S

Dv
o
=2
V
o

1
128M
S
f
3
L
1
C
1
C
o
R
(9)
Figure 3 Performance of the elementary self-lift circuit
a Waveforms with enlarged variations
b Boundary between CCM and DCM and voltage transfer gains
against Z
N
180 IET Power Electron., 2009, Vol. 2, Iss. 2, pp. 178191
& The Institution of Engineering and Technology 2009 doi: 10.1049/iet-pel:20070023
www.ietdl.org
2.2 Circuit analysis in DCM
The elementary self-lift circuit operates in the DCM, if the
current i
Df
reduces to zero during switching-off. The
condition for the DCM is j
Df
! 1, that is,
j
Df

D
2M
2
S
Z
N
! 1 (10)
where Z
N
is dened as the normalised load R/( fL).
As a special case, when i
Df
decrease to zero at t T, the
circuit operates at the boundary of CCM and DCM.
Therefore the boundary between CCM and DCM is
obtained as below
Z
NB

2M
2
S
D

2
D(1 D)
2
(11)
When Z
N
. Z
N2B
, the circuit operates in the DCM. Under
this condition, i
Df
decreases to zero at t t
1
[D m
S
(1 2
D)]T, where
DT , t
1
, T and 0 , m
S
, 1
Here, m
S
is the current lling efciency for the elementary self-
lift circuit and dened as
m
S

t
1
DT
(1 D)T
(12)
In the DCM, i
L
increases during switching-on and decreases
during the period from DT to m
S
(1 2D)T. The
corresponding voltages across L are V
in
and 2(V
Cs
2V
in
).
Thus, utilising the volt-second balance principle, we have
DTV
in
m
S
(1 D)T(V
Cs
V
in
) or
DTV
in
m
S
(1 D)T(V
o
V
in
) (13)
In addition, the transferred charges of L during switching-off
are equal to m
S
(1 D)TDi
L
=2, which compensate the total
consumed charges of the load. So we have
I
o
T
1
2
m
S
(1 D)TDi
L
or
V
o
R
T
1
2
m
S
(1 D)T
DTV
in
L
(14)
Combining (13) and (14), we can obtain the lling efciency of
the elementary self-lift circuit as:
m
S

1

1 2D
2
Z
N
_
D(1 D)Z
N
(15)
From (13), we have
V
o
1
D
m
S
(1 D)
_ _
V
in
(16)
Therefore substituting (15) into (16) yields the voltage transfer
gain in the DCM as follows:
M
SDCM

1
2
1

1 2D
2
Z
N
_
_ _
(17)
Using (2), (11) and (17), we can obtain the boundary
curve between CCM and DCM as well as voltage
transfer gains against the normalised load, which is
shown in Fig. 3b.
3 Developed self-lift circuit
The developed self-lift circuit is derived from the elementary
self-lift circuit by adding the components (D
o
S
1
) and
redesigning the connection relations of L
1
. The circuit
diagram is shown in Fig. 4(a), and the subscript S
0
is used
here to distinguish this topology from the elementary self-
lift circuit. The equivalent circuits during switching-on,
Figure 4 Developed self-lift Cuk circuit
a Topology
b Equivalent circuit during switching-on
c Equivalent circuit during switching-off
d Equivalent circuit during DCM
IET Power Electron., 2009, Vol. 2, Iss. 2, pp. 178191 181
doi: 10.1049/iet-pel:20070023 & The Institution of Engineering and Technology 2009
www.ietdl.org
switching-off and DCM are shown in Fig. 4b4d,
respectively. Static switches S and S
1
are switched
simultaneously. The lift circuit consists of C
1
2L
1
-S
1
-D
1
,
and it is a basic VL cell. When S and S
1
turn on, D
1
is on,
D
f
and D
o
are off. When S and S
1
turn off, D
1
is off, D
f
and D
o
are on. Capacitor C
1
performs its characteristics to
lift the output capacitor voltage V
Co
by the capacitor
voltage V
Cs
.
3.1 Circuit analysis in CCM
Switching diagrams with main steady-state waveforms are
shown in Fig. 5a to analyse the circuit operation, where
reference directions are referred to in Fig. 4a. The inductor
current i
L
increases during switching-on and decreases
during switching-off. The corresponding voltages across L
are V
in
and (V
Cs
V
in
), which are the same with the
condition of the foregoing elementary self-lift circuit.
Therefore we obtain
V
Cs

1
1 D
V
in
During switching-on, the voltage across C
1
is equal to V
Cs
.
Since C
s
and C
1
are sufciently large, we have
V
C1
V
Cs

1
1 D
V
in
The inductor current i
L1
increases during switching-on and
decreases during switching-off. The corresponding voltages
across L are V
Cs
and (V
Co
V
C1
). Therefore with the
sec-voltage balance principle, we have
DTV
Cs
(1 D)T(V
Co
V
C1
) or
DTV
Cs
(1 D)T(V
o
V
Cs
)
Hence,
V
o

1
(1 D)
2
V
in
The voltage transfer gain in CCM is
M
S
0
V
o
V
in

1
(1 D)
2
(18)
and the input current is
I
in

1
(1 D)
2
I
o
I
L
I
Csoff
(19)
The charges of C
o
increase during switching-off and decrease
during switching-on. We obtain
Q
Co
I
o
DT
Q
Co
I
Cooff
(1 D)T
In a switching cycle, Q
Co
Q
Co2
. Therefore
I
Cooff

D
1 D
I
o
During switching-off, i
Do
i
Co
i
o
. Therefore
I
Dooff
I
Cooff
I
o

1
1 D
I
o
(20)
During switching-off, L
1
and C
1
form a path and transfer the
stored energy through D
o
. Therefore
I
L1
I
Dooff

1
1 D
I
o
Since the peak-to-peak current variation of i
L
, Di
L
is equal
Figure 5 Performance of the developed self-lift circuit
a Waveforms with enlarged variations
b Boundary between CCM and DCM and voltage transfer gains
against Z
N
182 IET Power Electron., 2009, Vol. 2, Iss. 2, pp. 178191
& The Institution of Engineering and Technology 2009 doi: 10.1049/iet-pel:20070023
www.ietdl.org
to DTV
in
=L, the variation ratio of the current i
L
is
6
L

Di
L
=2
I
L

D
2(M
0
S
)
2
R
fL
(21)
Since the peak-to-peak current variation of i
L1
, Di
L1
is equal
to DTV
Cs
=L
1
, the variation ratio of the current i
L1
is
6
L1

Di
L1
=2
I
L1

D
2M
0
S
R
fL
1
(22)
The variation of the current i
Do
during switching-off is equal
to Di
L1
, and i
Do2off
is equal to i
L1
. Therefore the variation
ratio of i
Do
is
j
Do
6
L1

D
2M
0
S
R
fL
1
(23)
The peak-to-peak voltage variation of v
o
, Dv
o
is equal to
I
o
DT=C
o
. Therefore the variation ratio of v
o
is
1
S
0
Dv
o
=2
V
o

D
2RC
o
f
(24)
3.2 Circuit analysis in DCM
The developed self-lift circuit operates in DCM, if the
current i
Do
reduces to zero during switching-off. The
condition for DCM is j
Do
! 1, that is,
j
Do

D
2M
0
S
Z
N
! 1 (25)
where Z
N
is dened as the normalised load R/( fL
1
).
As a special case, when i
Do
decrease to zero at t T, the
circuit operates at the boundary of CCM and DCM.
Therefore the boundary between CCM and DCM is
obtained as below:
Z
NB

2M
S
0
D

2
D(1 D)
2
(26)
When Z
N
. Z
N2B
, the circuit operates in DCM. Under this
condition, i
Do
decreases to zero at t t
1
[D
m
S
0 (1 D)]T, where
DT , t
1
, T and 0 , m
S
0 , 1
Here, m
S
0 is the current lling efciency for the developed
self-lift circuit, and its denition is the same to (12).
In DCM, current i
L1
increases during switching-on and
decreases during the period from DT to m
S
(1D)T. The
corresponding voltages across L
1
are V
Cs
and
(V
Co
V
C1
). Thus, using the volt second balance
principle, we have
DTV
Cs
m
S
0 (1 D)T(V
Co
V
C1
) or
DT
1
1 D
V
in
m
S
0 (1 D)T V
o

1
1 D
V
in
_ _
(27)
Additionally, the transferred charges of L
1
during switching-
off are equal to m
S
(1 D)TDi
L1
=2, which compensate the
total consumed charges of the load. So we have
I
o
T
1
2
m
S
0 (1 D)TDi
L1
or
V
o
R
T
1
2
m
S
0 (1 D)T
DT
L
1
1
1 D
V
in
(28)
Combining (28) and (29), we obtain
m
S
0
1

1 2D
2
Z
N
_
D(1 D)Z
N
(29)
From (27), we have
V
o

1
1 D

D
m
S
0 (1 D)
2
_ _
V
in
(30)
Therefore substituting (29) into (30) yields the following
voltage transfer gain in DCM
M
S
0
DCM

1

1 2D
2
Z
N
_
2(1 D)
(31)
Using(18), (26) and(31), we obtainthe boundary curve between
CCM and DCM. The voltage transfer gains versus the
normalised load are thus shown in Fig. 5b, which is benecial
for theoretical analysis and practical engineering design.
4 Re-lift circuit
The re-lift circuit shown in Fig. 6a is derived from the
developed re-lift circuit by adding the components
(D
2
2C
2
2D
3
2L
2
). The equivalent circuits during
switching-on, switching-off and DCM are shown in
Fig. 6b6d respectively. The lift circuit consists of
C
1
2L
1
2D
2
2C
2
2D
3
2L
2
2S
1
and it can be divided
into two basic VL cells. When switches S and S
1
turn on,
D
1
, D
2
and D
3
are on, D
f
and D
o
are off. When S and S
1
turn off, D
1
, D
2
and D
3
are off, D
f
and D
o
are on.
Capacitors C
1
and C
2
perform characteristics to lift the
output capacitor voltage V
Co
by twice the capacitor voltage
V
Cs
. L
1
performs the function of a ladder joint to link the
two capacitors C
1
and C
2
and lift V
Co
.
4.1 Circuit analysis in CCM
Switching diagrams with main steady-state waveforms are
shown in Fig. 7a to analyse the circuit operation, where
IET Power Electron., 2009, Vol. 2, Iss. 2, pp. 178191 183
doi: 10.1049/iet-pel:20070023 & The Institution of Engineering and Technology 2009
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reference directions are referred to in Fig. 6a. As is illustrated
in the previous Section 3, we obtain the same formula
V
Cs

1
1 D
V
in
During switching-on, both the voltages across C
1
and C
2
are
equal to V
Cs
. Since C, C
1
and C
2
are sufciently large, we
have:
V
C1
V
C2
V
Cs

1
1 D
V
in
The voltage across L
1
is equal to V
Cs
during switching-on.
With the volt second balance principle, we get
V
L1off

D
1 D
V
Cs

D
(1 D)
2
V
in
The inductor current i
L2
increases during switching-on
and decreases during switching-off. The corresponding
voltages across L
2
are V
Cs
and (V
Co
V
C1

V
C2
V
L1off
). Therefore with the sec-voltage balance
principle, we have
DTV
Cs
(1 D)T(V
Co
V
C1
V
C2
V
L1off
) or
DT
1
1 D
V
in
(1 D)T(V
o

2
1 D
V
in
V
L1off
)
Hence
V
o

2
(1 D)
2
V
in
Figure 6 Re-lift Cuk circuit
a Topology
b Equivalent circuit during switching-on
c Equivalent circuit during switching-off
d Equivalent circuit during DCM
Figure 7 Performance of the re-lift circuit
a Waveforms with enlarged variations
b Boundary between CCM and DCM and voltage transfer gains
against Z
N
184 IET Power Electron., 2009, Vol. 2, Iss. 2, pp. 178191
& The Institution of Engineering and Technology 2009 doi: 10.1049/iet-pel:20070023
www.ietdl.org
The voltage transfer gain in CCM is
M
R

V
o
V
in

2
(1 D)
2
(32)
and the input current is
I
in

2
(1 D)
2
I
o
I
L
I
Csoff
(33)
The charges of both C
o
increase during switching-off and
decrease during switching-on. Thus, we obtain
Q
Co
I
o
DT
Q
Co
I
Cooff
(1 D)T
In a switching cycle, Q
Co
Q
Co2
. Therefore
I
Cooff

D
1 D
I
o
During switching-off, i
Do
i
Co
i
o
. Therefore
I
Dooff
I
Cooff
I
o

1
1 D
I
o
(34)
During switching-off, C
1
, L
1
, C
2
and L
2
form a path and
transfer the stored energy through D
o
. Therefore
I
L1
I
L2
I
Dooff

1
1 D
I
o
(35)
In a switching cycle, Di
L
is equal to DTV
in
=L; therefore the
variation ratio of the current i
L
is
6
L

Di
L
=2
I
L

D
2M
2
R
R
fL
(36)
Analogously, Di
L1
and Di
L2
correspond to DTV
Cs
=L
1
and
DTV
Cs
=L
2
respectively. Therefore the variation ratios of i
L1
and i
L2
are
6
L1

Di
L1
=2
I
L1

D
2M
R
R
fL
1
(37)
6
L2

Di
L2
=2
I
L2

D
2M
R
R
fL
2
(38)
The variation of the current i
Do
during switching-off is equal
to Di
L2
, so the variation ratio of i
Do
is
j
Do
6
L2

D
2M
R
R
fL
2
(39)
The peak-to-peak voltage variation of v
o
, Dv
o
, is equal to
I
o
DT=C
o
. Therefore the variation ratio of v
o
is
1
S

Dv
o
=2
V
o

D
2RC
o
f
(40)
Equations (37) and (38) indicate that the inductor current
variations during a switching cycle may be different due to the
inductance difference. Because L
1
and L
2
are in series during
switching-off, the same inductance is thus recommended in
practical circuit design. In reality, although they will be
slightly different, it will not affect the normal operation. This
is because the practical inductor current variations (ripple) will
be rather small under the high switching frequency and large
inductance conditions.
4.2 Circuit analysis in DCM
From the foregoing explanation, it is assumed that L
1
and L
2
are the same, which can simplify the boundary analysis of
CCM and DCM. The re-lift circuit operates in DCM, if
the current i
Do
reduces to zero during switching-off. The
condition for DCM is j
Do
! 1, that is,
j
Do

D
2M
R
Z
N
! 1 (41)
As a special case, when i
Do
decrease to zero at t T, the
circuit operates at the boundary of CCM and DCM.
Therefore the boundary between CCM and DCM is
obtained as below:
Z
NB

2M
R
D

4
D(1 D)
2
(42)
When Z
N
. Z
N2B
, the circuit operates in DCM. Under this
condition, i
Do
decreases to zero at t t
1
[D
m
R
(1 2D)]T, where
DT , t
1
, T and 0 , m
R
, 1
Here, m
R
is the current lling efciency for the re-lift circuit,
and its denition is the same to (12).
In DCM, because current i
L2
increases during switching-
on and decreases during the period from DT to (1 2D)m
R
T,
we thus have
V
L2off

D
(1 D)m
R
V
Cs
Current i
L1
increases during switching-on and decreases
during the period from DT to m
R
(1 2D)T. The
corresponding voltages across L
1
are V
Cs
and (V
Co

V
C1
V
C2
V
L2off
). Thus, using the volt2second balance
principle, we have
DTV
Cs
(1 D)m
R
T(V
Co
V
C1
V
C2
V
L2off
) or
DTV
Cs
(1 D)m
R
T V
o
2V
Cs

D
(1 D)m
R
V
Cs
_ _
(43)
Additionally, the transferred charges of L
2
during switching-
off are equal to m
R
(1 D)TDi
L2
=2, which compensate the
IET Power Electron., 2009, Vol. 2, Iss. 2, pp. 178191 185
doi: 10.1049/iet-pel:20070023 & The Institution of Engineering and Technology 2009
www.ietdl.org
total consumed charges of the load. So we have
I
o
T
1
2
m
R
(1 D)TDi
L2
or
V
o
R
T
1
2
m
R
(1 D)T
DTV
Cs
L
2
(44)
Combining (43) and (44), we obtain
m
R

2 2

1 D
2
Z
N
_
D(1 D)Z
N
(45)
From (43), we have
V
o
2
2D
m
R
(1 D)
_ _
V
Cs
(46)
Therefore substituting (45) into (46) yields the following
voltage transfer gain in DCM
M
RDCM

1

1 D
2
Z
N
_
1 D
(47)
Using (32), (42) and (47), we can obtain the boundary curve
between CCM and DCM. The voltage transfer gains against
the normalised load are thus shown in Fig. 7b, which is
benecial for theoretical analysis and practical engineering
design.
5 Multiple-lift circuits
5.1 General analysis
Referring to Fig. 6a, it is possible to construct multiple-lift
circuits by repeatedly adding the components (D
2
2C
2
2
L
2
2D
3
). Assuming that there are n VL cells, the
generalised multiple-lift circuit is shown in Fig. 8a with
reference directions. According to this principle, only two
synchronous switches S and S
1
are required for each
complex multiple-lift circuit, which simplify the control
scheme and decrease the cost signicantly. Hence, each
circuit has two switches, (n 1) inductors, (n 2)
capacitors and (2n 1) diodes.
When switches S and S
1
turn on, D
1
, D
2
, . . . , D
2n21
are
on; D
f
and D
o
are off. When S and S
1
turn off, D
1
, D
2
, . . . ,
D
2n21
are off; D
f
and D
o
are on. Capacitors C
1
, C
2
, . . . , C
n
lift V
Co
by n times of V
Cs
. Inductors L
1
, L
2
,. . . L
n
perform
the same function of a ladder joint to link the adjacent
capacitors. From the foregoing analysis and calculation, the
general formulas for all multiple-lift circuits can be
obtained according to the similar steps.
The generalised voltage transfer gain is
M
n
(1 D)
h(n)
n 1, 2, 3, 4, . . . (48)
Figure 8 Multiple-lift circuit possessing n voltage-lift cells
a Generalised representation
b Boundaries between CCM and DCM against the normalised load Z
N
(1, elementary self-lift circuit; 2, developed self-lift circuit; 3, re-lift
circuit; 4, triple-lift circuit; 5, quadruple-lift circuit)
186 IET Power Electron., 2009, Vol. 2, Iss. 2, pp. 178191
& The Institution of Engineering and Technology 2009 doi: 10.1049/iet-pel:20070023
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Where
h(n)
1 elementary self -lift
2 others
_
The generalised current of L is
I
L

n
(1 D)
h(n)
I
o
(49)
The generalised jth inductor current is
I
Lj

1
(1 D)
h(n)1
I
o
(50)
The following general analysis is for the developed self-lift
circuit and its corresponding multiple-lift circuits. The
generalised variation of the jth inductor current i
Lj
is
6
Lj

Di
Lj
=2
I
Lj

D
2M
R
fL
j
(51)
Analogously, the generalised variation ratio of the output
voltage v
o
is
1
Dv
o
2=2
V
o

D
2RfC
o
(52)
The generalised variation of the diode current i
Do
is
j
Do

D
2M
R
fL
N
(53)
It is assumed that all inductors existing in the VL cells are the
same. Therefore the generalised boundaries between the
CCM and the DCM for all circuits are
Z
NB

2M
D

2n
D(1 D)
2
(54)
The generalised current efciency is
m
n

n
2
2nD
2
Z
N
_
D(1 D)Z
N
(55)
The generalised voltage transfer gain in DCM is
M
DCM

n

n
2
2nD
2
Z
N
_
2(1 D)
(56)
If the generalised circuit possesses three VL cells, it is termed
the triple-lift circuit. If the generalised circuit possesses four
VL cells, it is termed the quadruple-lift circuit. The main
characteristics of these two multiple-lift circuits are given in
Table 1 for ready reference.
The boundaries between CCM and DCM of all proposed
circuits are shown in Fig. 8b. The curves of all M against Z
N
indicate that the CCM area increases from the elementary
self-lift circuit via the developed self-lift circuit, the re-lift
circuit, the triple-lift circuit to the quadruple-lift circuit.
There are minimum values of Z
N
(13.5, 13.5, 27, 40.5 and
54) at the boundaries, and all of them are under the
condition of D 1/3. It means that the condition of
D 1/3 is the most possible for these converters to enter
DCM. The corresponding extreme points are also marked
in Fig. 8b for ready reference.
5.2 Summary of proposed converters
From the foregoing analysis, we can obtain an overview and
main analytical results of proposed VL-type converters.
Equation (52) indicates that the output voltage variation
ratios are determined by the interactions caused by D, R, f
and C
o
. So increasing the capacitance of output capacitor
can effectively improve the output ripper.
In order to show the advantages of proposed circuits over
the conventional Cu k converter, voltage transfer gains V
o
/
V
in
in duty ratio D 0.33, 0.5, 0.75 and 0.8 are listed in
Table 2.
The data in Table 2 indicate that all proposed converters
can obtain higher voltage transfer gains compared with the
conventional Cu k prototype. Although both n-cell cascade
connection converters and transformer-type converters can
achieve high voltage transfer gains, their efciency h
remains low. This is because h of n-cell cascade connection
converters is given by the product of the efciencies of each
Table 1 Main characteristics of proposed multiple-lift circuits
Triple-lift circuit Quadruple-lift circuit
M 3/(1 2D)
2
4/(1 2D)
2
M
DCM
(3

9 6D
2
Z
N
)
_
=2(1 D) (2

4 2D
2
Z
N
)
_
=(1 D)
Z
NB
6/D(1 2D)
2
8/D(1 2D)
2
m 3

9 6D
2
Z
N
_
=D(1 D)Z
N
4 2

4 2D
2
Z
N
_
=D(1 D)Z
N
I
L
[3/(1 2D)
2
]I
o
[4/(1 2D)
2
]I
o
I
Lj
, j 1, . . . ,4 [1/(1 2D)]I
o
IET Power Electron., 2009, Vol. 2, Iss. 2, pp. 178191 187
doi: 10.1049/iet-pel:20070023 & The Institution of Engineering and Technology 2009
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cell belonging to the cascade connection, that is h h
1
h
2
. . . h
n
. And h of transformer-type converters would be
limited by additional losses caused by transformer magnetic
characteristics. Since all proposed converters avoid these
problems, compact structures with a good efciency might
be achieved in the practical manufacture.
5.3 Comparison with negative output
quadratic converters
Quadratic converters are a class of topologies which provide
the voltage transfer gains with quadratic dependence on D.
Three negative output quadratic converters proposed in
[12] are compared with the VL-type Cuk converters in
terms of the complexity, voltage transfer gains and voltage
stresses, which is tabulated in Table 3. It is seen that the
proposed converters can provide higher voltage transfer
gains with additional complexity. Additionally, higher
voltage stresses exist in the proposed converters, which
means the high-performance semiconductors and control
algorithm should be used to avoid the components
destruction in the practical applications.
6 Case analysis: simulation and
experimental results
To verify the foregoing theoretical analysis results, Psim
simulation package was applied to the proposed converters.
The corresponding hardware testing circuits were also
constructed to compare with the simulation results.
Table 3 Comparison between four proposed converters and quadratic converters (voltages are normalised to V
in
)
Negative output quadratic
converters [12]
Proposed converters
Elementary self-lift
circuit
Developed self-lift circuit
no. of switch 1 1 2
no. of diode 3 2 3
no. of L 2 2 3
no. of C 2 3 3
M V
o
/V
in
2D
2
/(1 2D) 21/(1 2D) 21/(1 2D)
2
stresses of diodes
(V
D
)
1 or D/(1 2D) or 1/(1 2D) 1/(1 2D) V
Df
V
D1
1/(1 2D) and
V
Do
1/(1 2D)
2
stresses of switch
(V
S
)
1/(1 2D) 1/(1 2D) V
S
1/(1 2D) and V
S1
1/(1 2D)
2
Table 2 Comparison between four proposed converters and the conventional Cuk converter
Topology I
o
V
o
M V
o
/V
in
D 0.33 D 0.5 D 0.75 D 0.8
conventional Cuk prototype I
o
[(1 2D)/D]I
in
V
o
[D/
(1 2D)]V
in
0.5 1 3 4
proposed
converters
elementary self-lift
circuit
I
o
(1 2D)I
in
V
o
[1/
(1 2D)]V
in
1.5 2 4 5
developed self-lift
circuit
I
o
(1 2D)
2
I
in
V
o
[1/(1 2
D)
2
]V
in
2.25 4 16 25
re-lift circuit I
o
[(1 2D)
2
/
2]I
in
V
o
[2/
(1 2D)
2
]V
in
4.5 8 32 50
triple-lift circuit I
o
[(1 2D
2
)/
3]I
in
V
o
[3/
(1 2D)
2
]V
in
6.75 12 48 75
quadruple-lift circuit I
o
[(1 2D)
2
/
4]I
in
V
o
[4/
(1 2D)
2
]V
in
9 16 64 100
188 IET Power Electron., 2009, Vol. 2, Iss. 2, pp. 178191
& The Institution of Engineering and Technology 2009 doi: 10.1049/iet-pel:20070023
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6.1 Simulation and experimental results
of two self-lift circuits (elementary
and developed)
Referring to Figs. 2a and 4a, both of these two circuits are under
the same simulation condition that V
in
10 V, R 100 V,
L 1 mH, L
1
500 mH, C
s
110 mF, C
1
22 mF,
C
o
47 mF, D 0.5 and f 100 kHz. All the diodes and
the switch are ideal. Since simulation is to be performed in
CCM, we use (11) and (26) to obtain the boundary values of
normalised load, Z
NB
j
D0:5
. For these two cases, both
Z
NB
j
D0:5
are equal to 16. Both the normalised load Z
N
are
equal to 2 and located at the left CCM region of their
boundary curve. Therefore it indicates that the above
parameters are appropriate for the CCM operation.
According to (2) and (18), we obtain the theoretical output
voltage values V
o
which are equal to 20 V (elementary) and
40 V (developed) respectively. From (9) and (24), the
output voltage variation ratios 1
S
and 1
S
0 are equal to
7.5e 28 and 5.3e 24 respectively. Therefore the near-zero
ripple is achieved. The simulation startup traces are shown
in Fig. 9a, where curves 1 and 2 correspond to v
o
of the
elementary self-lift circuit and the developed self-lift circuit
respectively. The simulated responses to the duty ratio
down-step change from 0.5 to 0.4 are shown in Fig. 9b.
The steady-state performance in all simulation cases is
identically matching to the theoretical analysis.
In the hardware testing circuit, we still choose the same
parameters. The n-channel MOSFET 2SK2267 is selected
as the power switches S. The drain-source on resistance is
8 mV, which is near the ideal condition. All the diodes are
realised by using MBR6045WT, the forward voltage drop
of 0.6 V. Thus, the practical output voltage is smaller than
the theoretical values due to the effects caused by parasitic
parameters. Under the condition of D 0.5, the
corresponding steady-state experimental curves are shown
in Fig. 9c. After careful measurement, we obtained that the
practical output voltage value of the elementary self-lift
circuit, V
o1
19 V (shown in Channel 1 with 10 V/Div),
and the practical output voltage value of the developed self-
lift circuit, V
o2
37 V (shown in Channel 2 with 10 V/
Div). It is seen that the measured results are close to the
theoretical analysis and simulation results. Additionally, the
experimental results of the duty ratio down change from
0.5 to 0.4 are shown in Fig. 9d. In Fig. 9d, the oscillations
in these two cases decay in a short time, and the open-loop
transient processes are quick in only few milliseconds. Both
of these two cases reach their corresponding new steady
state, which have a good agreement with the simulation
results as shown in Fig. 9b.
6.2 Simulation and experimental results
of the re-lift circuit
The circuit parameters for simulation are: V
in
10 V,
R 100 V, L 1 mH, L
1
L
2
500 mH, C
s
110 mF,
Figure 9 Simulation and experimental results of the self-lift
circuits (curve/channel 1, elementary; curve/channel 2,
developed)
a Simulated startup traces under zero initial conditions
b Simulated response to the duty ratio step change from 0.5 to
0.4
c Experimental output voltage results of steady-state
performance
d Experimental output voltage results of the duty ratio step
change from 0.5 to 0.4
IET Power Electron., 2009, Vol. 2, Iss. 2, pp. 178191 189
doi: 10.1049/iet-pel:20070023 & The Institution of Engineering and Technology 2009
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C
1
C
2
22 mF, C
o
47 mF, D 0.5 and f 100 kHz.
The other assumptions are the same with those for
above-mentioned self-lift circuits. Analogously, we use (42)
and obtain the boundary values of normalised load,
Z
NB
j
D0:5
32. The normalised load Z
N
in this case is
equal to 2 and located at the left CCM region of the
boundary curve as shown in Fig. 7b. Therefore it indicates
that above parameters are appropriate for the CCM
operation.
According to (32), we obtain the theoretical value of V
o
,
which is equal to 80 V. Since the corresponding output
voltage variation ratio 1 is equal to 5.3e-4 calculated by
(40), the near-zero ripple is achieved. The simulated
startup trace (v
o
) under zero initial conditions is shown in
Fig. 10a, and the steady-state performance in the
simulation is identically matching to the theoretical
analysis. The simulated responses (v
o
, i
L
, i
L1
and i
L2
) to
the duty ratio down-step change from 0.5 to 0.4 are shown
in Fig. 10b.
The same parameters are chosen to construct a testing
hardware circuit. Two n-channel MOSFETs are selected.
All diodes and MOSFETS are the same with those
adopted in the self-lift circuits. Under the condition of
D 0.5, the corresponding steady-state experimental curve
is shown in Fig. 10c. We obtained that the practical output
voltage value V
o
72 V (shown in Channel 1 with 20 V/
Div). Considering the power losses, we see that the
measured results are very close to the theoretical analysis
and simulation results. Additionally, the experimental
results of the duty ratio down change from 0.5 to 0.4 are
shown in Fig. 10d. The open-loop transient processes are
quick in only few milliseconds. The converter reaches the
new steady state, which has a good agreement with the
simulation results as shown in Fig. 10b.
6.3 Transient process and stability
analysis
The open-loop transient processes are very quick in only few
milliseconds as shown in Figs. 9 and 10, and they exhibit the
common characteristics existing widely in dcdc converters.
It is difcult to discuss it in this paper because of the
limitation of papers length. We would like to state the
detailed transient process and circuit stability analysis in
other papers.
7 Conclusion
This paper introduced the application and development of
the VL technique in the design of dcdc power conversion
circuits. A series of novel VL-type Cu k converters has been
proposed using the series Cu k implementing the VL
technique, which can greatly increase the output voltage
transfer gains. The proposed converters overcome the
effects of parasitic parameters and avoid taking too high a
Figure 10 Simulation and experimental results of the re-lift
circuit case
a Simulated startup traces under zero initial conditions
b Simulated response to the duty ratio step change from 0.5 to
0.4
c Experimental output voltage results of steady-state
performance
d Experimental output voltage results of the duty ratio step
change from 0.5 to 0.4
190 IET Power Electron., 2009, Vol. 2, Iss. 2, pp. 178191
& The Institution of Engineering and Technology 2009 doi: 10.1049/iet-pel:20070023
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value of the duty ratio D. They also have the characteristics of
high efciency, small ripple in simple structures. Theoretical
topology analysis achieved several important results which are
useful for potential applications. These converters could be
widely used in the areas of computer peripheral circuits,
medical equipment, semiconductor industry, especially in
applications with high output voltages. The high-
performance semiconductors and advanced control
algorithm should be helpful to avoid the high stress in
these converters.
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doi: 10.1049/iet-pel:20070023 & The Institution of Engineering and Technology 2009
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