Академический Документы
Профессиональный Документы
Культура Документы
ADDER
To Simulate VHDL Program for Adder Using ModelSim SE 6.0a tool and verify the output. APPARATUS REQUIRED: 1. ModelSim SE 6.0a 2. PC : WINDOWS / XP PROCEDURE: 1. Double click on ModelSim SE 6.0a icon in the Desktop. 2. Click file New Source VHDL. 3. Type the program in the work space window. 4. Save the program as .vhd extension in Work. 5. Go to Compile Type file name Compile Done. 6. Go to Simulate Start SimulationWorkSelect Filename Ok. 7. Go to View Debug WindowObjects. 8. Force the input by right clicking the input variables 9. Select all the variablesRight clickAdd To WaveSelected Signals. 10. Go to Simulate RunRun 100ps.
Half adder:
Truth Table
architecture dataflow of halfadder is begin sum<= a xor b; carry<= (a and b); end dataflow;
entity xor1 is port ( a : in std_logic; b : in std_logic; y : out std_logic); end xor1; architecture dataflow of xor1 is begin y<= a xor b; end dataflow; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity halfadder is port ( a,b : in std_logic; sum, carry : out std_logic); end halfadder; architecture structure of halfadder is component xor1 port(a,b: in std_logic; y: out std_logic); end component; component and1 port(a,b: in std_logic; y: out std_logic); end component; begin x1: xor1 port map(a,b,sum); a1: and1 port map(a,b,carry); end structure;
Full adder:
Truth Table
b : in std_logic; y : out std_logic); end and1; architecture dataflow of and1 is begin y<= a and b; end dataflow; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity or1 is port ( a : in std_logic; b : in std_logic; c : in std_logic; y : out std_logic); end or1; architecture dataflow of or1 is begin y<= a or b or c; end dataflow; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity xor1 is port ( a : in std_logic; b : in std_logic; c : in std_logic; y : out std_logic); end xor1; architecture dataflow of xor1 is begin y<= a xor b xor c; end dataflow; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
VIVA-VOCE Question: 1. What is a Logic Gate? 2. Write the names of Universal Gates. 3. Define half adder and full adder. 4. Define half subtractor and full subtractor. 5. What do you mean by carry propagation delay?
entity fulladder is port ( a, b, c : in std_logic; sum, carry : out std_logic); end fulladder; architecture structure of fulladder is component xor1 port(a,b,c: in std_logic; y: out std_logic); end component; component and1 port(a,b: in std_logic; y: out std_logic); end component; component or1 port(a,b,c: in std_logic; y: out std_logic); end component; signal y1,y2,y3:std_logic; begin x1: xor1 port map(a,b,c,sum); a1: and1 port map(a,b,y1); a2: and1 port map(b,c,y2); a3: and1 port map(c,a,y3); o1: or1 port map(y1,y2,y3,carry); end structure;
RESULT: Thus the half adder and full adder program using ModelSim SE 6.0a was simulated and output was verified.
4 to 1 Multiplexer
10
To Simulate VHDL Program for Multiplexer and Demultiplexer Using ModelSim SE 6.0a tool and verify the output. APPARATUS REQUIRED: 1. ModelSim SE 6.0a tool 2. PC:WINDOWS / XP PROCEDURE: 1. Double click on ModelSim SE 6.0a icon in the Desktop. 2. Click file New Source VHDL. 3. Type the program in the work space window. 4. Save the program as .vhd extension in Work. 5. Go to Compile Type file name Compile Done. 6. Go to Simulate Start SimulationWorkSelect Filename Ok. 7. Go to View Debug WindowObjects. 8. Force the input by right clicking the input variables 9. Select all the variablesRight clickAdd To WaveSelected Signals. 10. Go to Simulate RunRun 100ps.
11
12
use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mux8to1 is port(a : in std_logic_vector(7 downto 0); sel : in std_logic_vector(2 downto 0); y : out std_logic); end mux8to1; architecture behavioral of mux8to1 is begin process(sel,a) begin case sel is when"000"=> y<=a(0); when"001"=> y<=a(1); when"010"=> y<=a(2);
VIVA-VOCE Question: 1. 2. 3. 4. What is Multiplexer? What is DeMultiplexer? Give application of multiplexer? What is the difference between Decoder and Demultiplexer?
14
when"011"=> y<=a(3); when"100"=> y<=a(4); when"101"=> y<=a(5); when"110"=> y<=a(6); when"111"=> y<=a(7); when others=> end case; end process; end behavioral;
15
architecture behavioral of demux1to2 is begin y1<= i and (not(s)); y2<= i and s; end behavioral;
16
y1<= i and (not(s1)) and (not(s0)); y2<= i and (not(s1)) and ((s0)); y3<= i and (s1) and (not(s0)); y4<= i and (s1) and (s0); end behavioral;
RESULT: Thus the Multiplexer and Demultiplexer program using ModelSim SE 6.0a was simulated and output was verified.
Decoder:
18
To Simulate VHDL Program for Encoder and Decoder Using ModelSim SE 6.0a tool and verify the output. APPARATUS REQUIRED: 1. ModelSim SE 6.0a tool 2. PC:WINDOWS / XP PROCEDURE: 1. Double click on ModelSim SE 6.0a icon in the Desktop. 2. Click file New Source VHDL. 3. Type the program in the work space window. 4. Save the program as .vhd extension in Work. 5. Go to Compile Type file name Compile Done. 6. Go to Simulate Start SimulationWorkSelect Filename Ok. 7. Go to View Debug WindowObjects. 8. Force the input by right clicking the input variables 9. Select all the variablesRight clickAdd To WaveSelected Signals. 19
10.
PROGRAM: 2 to 4 Decoder:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity decoder2to4 is port ( e,i1,i2 : in std_logic; o1,o2,o3,o4 : out std_logic); end decoder2to4; OUTPUT WAVEFORM OF 2 TO 4 DECODER:
20
architecture behavioral of decoder2to4 is begin o1<= e and (not i1) and (not i2); o2<= e and (not i1) and i2; o3<= e and i1 and (not i2); o4<= e and i1 and i2; end behavioral;
3 to 8 Decoder:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity decoder3to8 is port ( e,i1,i2,i3 : in std_logic; o1,o2,o3,o4,o5,o6,o7,o8 : out std_logic); end decoder3to8; architecture behavioral of decoder3to8 is begin o1<= e and (not i1) and (not i2) and (not i3);
21
o2<= e and (not i1) and (not i2) and i3; o3<= e and (not i1) and i2 and (not i3); o4<= e and (not i1) and i2 and i3; o5<= e and i1 and (not i2) and (not i3); o6<= e and i1 and (not i2) and i3; o7<= e and i1 and i2 and (not i3); o8<= e and i1 and i2 and i3; end behavioral;
4 to 2 Encoder:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity encoder4to2 is port ( i1,i2,i3,i4 : in std_logic; o1,o2 : out std_logic); end encoder4to2;
22
architecture behavioral of encoder4to2 is begin o1<=(not (i1) and (i3) and not (i2) and not(i1)) or (i4 and not(i3) and not (i2) and not (i1)); o2<=(not (i4) and not(i3) and (i2) and not(i1)) or (i4 and not(i3) and not (i2) and not (i1)); end behavioral;
VIVA-VOCE Question: 1. What do you mean by encoder? 2. What is Decoder? 3. What do you mean by comparator? 4. Write a short note on priority encoder? 5. Distinguish between an encoder and decoder?
23
RESULT: Thus the Encoder and Decoder program using ModelSim SE 6.0a was simulated and output was verified.
24
EX.No:4 DATE :
Multiplier
AIM: To Simulate VHDL Program for Multiplier Using ModelSim SE 6.0a tool and verify the output. APPARATUS REQUIRED: 1. ModelSim SE 6.0a tool 2. PC:WINDOWS / XP PROCEDURE: 1. Double click on ModelSim SE 6.0a icon in the Desktop. 2. Click file New Source VHDL. 3. Type the program in the work space window. 4. Save the program as .vhd extension in Work. 5. Go to Compile Type file name Compile Done. 6. Go to Simulate Start SimulationWorkSelect Filename Ok. 7. Go to View Debug WindowObjects. 8. Force the input by right clicking the input variables 25
9. Select all the variablesRight clickAdd To WaveSelected Signals. 10. Go to Simulate RunRun 100ps.
26
PROGRAM:
27
RESULT: Thus the Multiplier program using ModelSim SE 6.0a was simulated and output was verified. SR Flip Flop
JK Flip Flop
28
Flip Flops
To Simulate VHDL Program for Flip Flops Using ModelSim SE 6.0a tool and verify the output. APPARATUS REQUIRED: 1. ModelSim SE 6.0a tool 2. PC:XP/WINDOWS PROCEDURE: 1. Double click on ModelSim SE 6.0a icon in the Desktop. 2. Click file New Source VHDL. 3. Type the program in the work space window. 4. Save the program as .vhd extension in Work. 5. Go to Compile Type file name Compile Done. 6. Go to Simulate Start SimulationWorkSelect Filename Ok. 29
7. Go to View Debug WindowObjects. 8. Force the input by right clicking the input variables 9. Select all the variablesRight clickAdd To WaveSelected Signals. 10. Go to Simulate RunRun 100ps.
PROGRAM:
31
T Flip Flop
32
signal ff:std_logic; begin process(j,k,clk,reset) variable jk:std_logic_vector(1 downto 0); begin jk:=j&k; if(reset='0')then ff<='0'; elsif(clk'event and clk='1')then case jk is when"01"=>ff<='0'; when"10"=>ff<='1'; when"11"=>ff<=not(ff); when others=>ff<=ff; end case; end if ; end process; q<=ff; qn<=not(ff); end behavioral;
33
34
3. 4. 5. 6.
Define Flip flop. What are the different types of flip-flop? What is the operation of D flip-flop? What is the operation of T flip-flop?
RESULT: Thus the Flip Flops using ModelSim SE 6.0a was simulated and output was verified.
36
COUNTER
To Simulate VHDL Program for Counter Using ModelSim SE 6.0a tool and verify the output. APPARATUS REQUIRED: 1. ModelSim SE 6.0a tool 2. PC:XP/WINDOWS PROCEDURE: 1. Double click on ModelSim SE 6.0a icon in the Desktop. 2. Click file New Source VHDL. 3. Type the program in the work space window. 4. Save the program as .vhd extension in Work. 5. Go to Compile Type file name Compile Done. 6. Go to Simulate Start SimulationWorkSelect Filename Ok.
37
7. Go to View Debug WindowObjects. 8. Force the input by right clicking the input variables 9. Select all the variablesRight clickAdd To WaveSelected Signals. 10. Go to Simulate RunRun 100ps.
38
architecture behavioral of upcounter is begin process(clk) variable temp: std_logic_vector (2 downto 0):="000"; begin if (rising_edge (clk)) then if clr='0' then case temp is when "000"=>temp:="001"; when "001"=>temp:="010"; when "010"=>temp:="011"; when "011"=>temp:="100"; when "100"=>temp:="101"; when "101"=>temp:="110"; when "110"=>temp:="111"; when "111"=>temp:="000"; when others=>temp:="000"; end case; else temp:="000"; 39
40
variable temp: std_logic_vector (2 downto 0):="000"; begin if (rising_edge (clk)) then if clr='0' then case temp is when "000"=>temp:="111"; when "111"=>temp:="110"; when "110"=>temp:="101"; when "101"=>temp:="100"; when "100"=>temp:="011"; when "011"=>temp:="010"; when "010"=>temp:="001"; when "001"=>temp:="000"; when others=>temp:="000"; end case; else temp:="000"; end if; end if; q<=temp; end process;
41
end behavioral;
42
43
when "0000"=>temp:="0001"; when "0001"=>temp:="0010"; when "0010"=>temp:="0011"; when "0011"=>temp:="0100"; when "0100"=>temp:="0101"; when "0101"=>temp:="0110"; when "0110"=>temp:="0111"; when "0111"=>temp:="1000"; when "1000"=>temp:="1001"; when others=>temp:="0000"; end case; else temp:="0000"; end if; end if; q<=temp; end process; end behavioral;
44
45
when others=>temp:="000"; end case; else temp:="000"; end if; end if; q<=temp; end process; end behavioral;
VIVA-VOCE Question: 1. 2. 3. 4. 5. 6. What is SR Latch? What is D Flip Flop? What is Dynamic D Flip Flop? What do you mean by latches and flip-flops? Define Flip flop. What are the different types of flip-flop?
RESULT: Thus the Counter program using ModelSim SE 6.0a was simulated and output was verified. SISO Shift Register:
46
EX.No:7 DATE :
SHIFT REGISTERS
47
AIM: To Simulate VHDL Program for Shift Registers Using ModelSim SE 6.0a tool and verify the output. APPARATUS REQUIRED: 1. ModelSim SE 6.0a tool 2. PC:XP/WINDOWS PROCEDURE: 1. Double click on ModelSim SE 6.0a icon in the Desktop. 2. Click file New Source VHDL. 3. Type the program in the work space window. 4. Save the program as .vhd extension in Work. 5. Go to Compile Type file name Compile Done. 6. Go to Simulate Start SimulationWorkSelect Filename Ok. 7. Go to View Debug WindowObjects. 8. Force the input by right clicking the input variables 9. Select all the variablesRight clickAdd To WaveSelected Signals. 10. Go to Simulate RunRun 100ps.
REGISTER:
library ieee; use ieee.std_logic_1164.all; entity reg is port(clk : in std_logic; input : in std_logic_vector(15 downto 0); output : out std_logic_vector(15 downto 0); ld : in std_logic) ; end reg; OUTPUT WAVEFORM OF REGISTER: 48
begin generic_register: process(clk, input, ld) begin if (rising_edge(clk)) then if (ld = '1') then output <= input ; end if ; end if ; end process ; end behavioral ;
8-bit Shift Register with Positive-Edge Clock, Serial In, and Serial Out:
library ieee; use ieee.std_logic_1164.all; entity siso is port(C, SI : in std_logic; SO : out std_logic); end siso; architecture archi of siso is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='1') then for i in 0 to 6 loop tmp(i+1) <= tmp(i); end loop; tmp(0) <= SI; end if; end process; SO <= tmp(7); end archi;
8-bit Shift Register with Positive-Edge Clock, Serial In, and Parallel Out:
51
library ieee; use ieee.std_logic_1164.all; entity sipo is port(C, SI : in std_logic; PO : out std_logic_vector(7 downto 0)); end sipo; architecture archi of sipo is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='1') then tmp <= tmp(6 downto 0) & SI; end if; end process; PO <= tmp; end archi; VIVA-VOCE Question: 1. 2. 3. 4. Define registers. What are the VHDL operators? What is meant by standard cell design? What is Cell Libraries?
RESULT: Thus the Shift Registers program using ModelSim SE 6.0a was simulated and output was verified.
52
Inverter Circuit:
EX.No:8 DATE :
CMOS INVERTER
53
AIM: To Design CMOS Inverter Using Multisim Software and verify the output. APPARATUS REQUIRED: 1. Multisim Software 2. PC:XP/WINDOWS
DC Operating Point:
54
55
VIVA-VOCE Question 1. 2. 3. 4. What is CMOS Technology? What are the different layers in MOS transistors? What are the different operating regions foes an MOS transistor? Name the four CMOS Technologies
RESULT: Thus the CMOS Inverter is Designed using Multisim and output was verified.
56
EX.No:9 DATE :
AIM: To Design CMOS NAND and NOR Gates Using Multisim Software and verify the output. APPARATUS REQUIRED: 1. Multisim Software 2. PC:XP/WINDOWS
DC Operating Point:
AC CHARACTERISTICS:
58
TRANSIENT CHARACTERISTICS:
59
VIVA-VOCE Question 1. Compare NMOS and PMOS. 2. Mention MOS transistor characteristics? 3. What is Cut-off region? 4. What are the three operating regions of MOS transistor?
RESULT: Thus the CMOS NAND and NOR Gates is Designed using Multisim and output was verified.
D-LATCH CIRCUIT: 60
EX.No:10
61
DATE :
CMOS D Latch
AIM: To Design CMOS D Latch using Multisim Software and verify the output. APPARATUS REQUIRED: 3. Multisim Software 4. PC:XP/WINDOWS
62
DC Operating Point:
AC CHARACTERISTICS:
63
VIVA-VOCE Question: 1. What is the operation of D flip-flop? 2. What are the different types of flip-flop?
RESULT: Thus the CMOS D Latch is Designed using Multisim and output was verified.
64
EX.No:11
65
DATE :
AIM: To implement the 4-bit full adder in FPGA using Quartus II 9.0 software. APPARATUS REQUIRED: 1. Quartus II 9.0 software 2. FPGA Kit 3. PC XP/WINDOWS PROCEDURE: 1. Double click on Quartus II 9.0 icon in the desktop 2. Click file Create a new project Enter the project name and location(c:\altera\90\quartus) 3. In new project wizard Family choose Cyclone III Package (FBGA) pin count(484) speed grade(6) available devices(EP3C16F484C6) next finish 4. File New click VHDL file ok 5. Enter the program in the work space window 6. File Save project (path: c:\altera\90\quartus\your file name) 7. Processing Start compilation 8. Assignments Pin planner(Assign input and output pin using data sheet) 9. Processing Start compilation 10. Tools Programmer 11. Click hardware setup choose USB blaster select your program and click start button 12. Implement the program in FPGA using Cyclone III and verify the result 13. RTL schematic view Tool Net list. PROGRAM: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fulladder is port ( a,b,c : in std_logic; sum, carry : out std_logic); end fulladder; architecture dataflow of fulladder is begin sum<= a xor b xor c; carry<= (a and b) or (b and c) or (a and c); end dataflow;
66
67
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity fadd4 is port(a,b : in std_logic_vector(3 downto 0); c : in std_logic; s : out std_logic_vector(3 downto 0); carry : out std_logic); end fadd4; architecture structural of fadd4 is component fulladder port(a,b,c : in std_logic; sum,carry : out std_logic); end component; signal c1,c2,c3: std_logic; begin a0: fulladder port map (a(0),b(0),c,s(0),c1); a1: fulladder port map (a(1),b(1),c1,s(1),c2); a2: fulladder port map (a(2),b(2),c2,s(2),c3); a3: fulladder port map (a(3),b(3),c3,s(3),carry); end structural;
RESULT: Thus the implementation of 4 Bit Adder using Quartus II 9.0 Software was simulated and output was verified in FPGA.
68