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State 1ransition Diagrams
1he state transition diagram
So far we have not discussed any method for
designing sequential circuits
We will only look at the design of synchronous
sequential circuits in this course
State transition diagrams are a graphical way of
representing the behaviour of a sequential
system
Lighting up
Consider the status of two LEDs counting a sequence:
Represents 01
If a one is added (input, say), the display moves to a new state
1
Represents 11
S1D
States can be represented by circles containing a symbol for the state, and
the value of the output associated with the state
The numbers represent the inputs that moved the state machine from 1
state to another state.
a, 01 b, 11
1
On an input of 1, this device
goes from state a to state b
0
2
Page 2
Counter diagram and table
e.g. state transition
diagram
for a 2 bit up counter
0 inputs leave the
state unchanged
The complete set of
states and associated
outputs can be shown
in a state transition
table
a,00 b,01
d,11 c,10
d
c
b
a
next state
i = 0
11 a d
10 d c
01 c b
00 b a
output
next state
i = 1
present
state
1
1
1
1
0
0
0 0
State assignment table
The next stage is to encode the states, there
are 4 so it can be done in 2 bits:
Given this, we can proceed to a state
assignment table, where everything is
represented in terms of 1s and 0s:
11 d
10 c
01 b
00 a
code state
1
0
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
0
next i = 0
n
1
n
0
0
1
1
0
next i = 1
n
1
n
0
1 1
1 1
0 0
0 0
output
o
1
o
0
present
p
1
p
0
1ruth 1able
By taking the inputs (present state and input) and putting them in a
truth table we can develop logic expressions for the next state and
outputs:
0 1 1 1 1 0 1
0 1 0 1 0 0 1
1 1 0 0 1 1 1
1 1 1 1 0 1 1
1 0 0 1 1 1 0
1 0 1 0 0 1 0
0 0 1 0 1 0 0
0 0 0 0 0 0 0
O
0
O
1
N
0
N
1
I P
0
P
1
a,00 b,01
d,11 c,10
1
1
1
1
0
0
0 0
This line indicates:
In state b, when the input is 1, the
next state is c and the output is 01
1ruth 1able
The next step is to develop the logic expressions for N
1,
N
0
O
1
O
0
from
the truth table, either by algebra, inspection or Karnaugh map,
whichever is easiest.
0 1 1 1 1 0 1
0 1 0 1 0 0 1
1 1 0 0 1 1 1
1 1 1 1 0 1 1
1 0 0 1 1 1 0
1 0 1 0 0 1 0
0 0 1 0 1 0 0
0 0 0 0 0 0 0
O
0
O
1
N
0
N
1
I P
0
P
1
A judicious choice of state codes
makes the outputs straightforward:
O
1
= P
1
and O
0
= P
0
Maps for N
1
and N
0
appear on the
next slide
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Page 3
K Maps
1 1 1
1 1 0
10 11 01 00
P
1
,P
0
I
1 1 1
1 1 0
10 11 01 00
P
1
,P
0
I
Fill in the maps and derive expressions for N
1
and N
0
N
1 N
0
K Maps
1 1 1
1 1 0
10 11 01 00
P
1
,P
0
I
1 1 1
1 1 0
10 11 01 00
P
1
,P
0
I
Solution:
N
1
= P
1
.P
0
.I + P
1
.I + P
1
.P
0
N
0
= P
0
.I + P
0
.I
N
1 N
0
\elcome to the machine
A General Sequential machine consists of two main blocks
edge triggered register to hold present state
logic circuits to derive the next state and outputs using the
present state and external inputs
Machine changes state on active clock edge
next state
logic circuit
clk
Next
State
Present
State
register
Present
State
Inputs
Outputs
Combinational
circuit to
determine
outputs
In some cases the next state and
output logic might be combined in
the same block of, eg PAL logic).
Speciic Implementation
In the case of our simple binary counter:
clock
On the clock edge, the
register changes to the
next stage present on
the inputs,
register
for present state
logic determining
outputs and next states
present
state
next
state
N
1
= P
1
.P
0
.I + P
1
.I + P
1
.P
0
N
0
= P
0
.I + P
0
.I
in this case
actual outputs
match present state
O
1
= P
1
and O
0
= P
0
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Page 4
\orked Lxample
The next few slides have blanks for you to fill in as
the lecture progresses.
This example takes us through the process needed to
design any sequential circuit.
The example is a two bit counter that can count up or
down, depending upon the input, U.
U = 1, count up, U = 0, count down
1he state transition diagram
Stage 1, construct the state transition diagram
showing 4 possible states (a, b, c, d), the outputs
at each stage and the two possible inputs (1 or 0)
that moved the machine from state to state:
a,00 b,01
d,11 c,10
0
1
U = 1, count up, U = 0, count down
1he state table
Complete
the state
table
11 a c d
10 d b c
01 c a b
00 b d a
Output
Next
U = 0 U = 1
Present
Allocate binary alues to states
Probably it will simplify things if the present state code
is made equal to the output code for that state.
11 00 10 11
10 11 01 10
01 10 00 01
00 01 11 00
Outpu
t
Next
U = 0 U =
1
Present
11 d
10 c
01 b
00 a
code state
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Page 5
State Assignment 1able
At this stage we
will take the
inputs as present
state (A and B),
input U and
outputs are the
next state (C and
D and the output
required P and
Q). These can
be put in a truth
table.
1 1 0 0 1 1 1
1 1 0 1 0 1 1
0 1 1 1 1 0 1
0 1 1 0 0 0 1
1 0 0 1 1 1 0
1 0 0 0 0 1 0
0 0 1 0 1 0 0
0 0 1 1 0 0 0
Q P D C U B A
Derie the logic Lxpressions
via Karnaugh maps or otherwise determine expressions for outputs
C, D, P and Q
1
0
10 11 01 00
A,B
U
1
0
10 11 01 00
A,B
U
C D
1
0
10 11 01 00
A,B
U
1
0
10 11 01 00
A,B
U
P Q
Logic Lxpression
C = A.B.U + A.B.U + A.B.U + A.B.U
D = B
P = A
Q = B
Determine the logic expressions from the K Map.
Implement the machine
B
Q
P
D
U
C
A
D Q
Q
D Q
Q
next
state
logic
circuit
A
B
C
D
A
B
clk
P
Q
Next
state
logic
circuit
Combinational logic block obtained from expressions.
Implemented here in programmable AND, fixed OR
circuit (PAL).
6
Page 6
Summary o General State Machines
A method has been presented for the design of
general state machines The stages were:
Construct a state transition diagram for the problem
construct a state table
construct a state assignment table
Implement machine