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Combinational logic refers to circuits whose output is strictly depended on the present value of the inputs. As soon as inputs are changed, the information about the previous inputs is lost, that is, combinational logics circuits have no memory. In many applications, information regarding input values at a certain instant of time is required at some future time. Although every digital system is likely to have combinational circuits, most systems encountered in practice also include memory elements, which require that the system be described in terms of sequential logic. Circuits whose outputs depends not only on the present input value but also the past input value are known as sequential logic circuits. FLIP FLOP A flip flop is a bistable electronic circuit that has two stable states i.e. its output is either high or low. The flip flop also has memory since its output will remain as set until something is done to change it. Flip-flop circuit is used for such applications as storage -stage, counter stage, or data transfer stage. R-S FLIP-FLOP It has two input terminal called the SET(S) and RESET(R) inputs. The circuit of R-S F F using NOR gates is as shown. The signal applied to the S & R terminals are control inputs(data inputs) and permit us to store 1 binary digit (bit). Determining the output states R Qn+1 = corresponding to all possible combinations of these inputs will lead to the truth table for the flip flop. Qn value of Q before conditions imposed on S & R. Qn+1 value of Q after conditions = imposed on S & R. When Q output is high (logic 1) S we say that the FF is set (a 1 is stored) & when the Q output is low (logic 0), we say that it is RESET or CLEARED and 0 is stored.

R 0 0 1 1

S 0 1 0 1

Qn + 1 Qn 1 0 ?


Qn +1 =

and =

(3) S = 0 ,R = 1, Qn + 1 = & = 1. RESET state.

(1)if S =0,R = 0,then Qn + 1 = = & = = , No change in state. (2) S = 1, R = 0, = = 0 & Qn+1 = 1. SET state. =0

(4) S=R=1 It leads to conclude that both outputs are 0 which contradicts our assumption that two outputs are complimentary.This condition is therefore not allowed.Truth Table is as shown . R S FLIP FLOP Using NAND Gates RS FF can also be formed using NAND gates. By using two inverters and two NAND gates we get the circuit which follows the same truth table as shown below.:- Qn+1

CLOCKED RS FF In a digital system which involves many gates and flip flops, it is impossible to guarantee that the S & R controls signals will arrive at the precise times required for the desired logic operations. False logic commands may be generated under certain conditions if one signal arrives before or after another. This difficulty can usually be overcome by allowing the flip-flop to change state only in synchronism with an external pulse train of period T called the clock. In this way o/p waveforms are synchronised with the clock and do not depend on the time of arrival of the S & R signals.

S.Y.P.II / II (2)SEQUENTIAL LOGIC CIRCUIT NKapoor When we speak of a clock signal, we mean a sequence of evenly spaced digital high and low signals proceeding at a fixed frequency. That is, the clock is a continuous sequence of square wave pulses. There are a number of reasons for the importance of the clock. Clearly it is essential for doing any kind of counting or timing operation. But, its most important role is in providing synchronization to the digital circuit. Each clock pulse may represent the transition to a new digital state of a so-called state machine" (simple processor) we will soon encounter. Or a clock pulse may correspond to the movement of a bit of data from one location in memory to another. A digital circuit coordinates these various functions by the synchronization provided by a single clock signal which is shared throughout the circuit. A more sophisticated example of this concept is the clock of a computer, which we have come to associate with processing speed (e.g. 330 MHz for typical current generation commercial processors.) Figure shows the a clocked R S FF.
Ck 0 1 1 1 1 R X 0 0 1 1 S X 0 1 0 1 Qn + 1 Qn Qn 1 0 ? No Change No Change SET RESET Not Allowed

block symbol

TRUTH TABLE The clock signal which accomplishes the synchronisation is inputted to each AND gate while the S & R controls signals constitute the other inputs. Thus, the inputs to the NOR gate FF can now be activated only when clock is high. In this way the S & R inputs will determine the final state of the FF, but the time at which FF may change state is determined by the clock signals. The control signals can arrive at different times without affecting the state of the o/p. For this system to operate properly the S & R inputs must arrive while the clock is in the LOW state, during which time the AND gates are disabled the truth table is as shown above. The clock RS FF is referred as LATCH The circuit for clocked R-S FF (using NAND gates) is as shown above. It follows the same Truth- Table. D-FLIP FLOP The RS FF has two data inputs R & S. To store a high bit 1 we want S =1. To store bit 0 we need R = 1. Generation of two signals to drive a FF is a disadvantage in many applications. Furthermore, the forbidden conditions of R = S = 1 may occur inadvertently. This has led to the D- FF, a circuit which needs only one Data input. Input signal is delayed by one clock cycle and hence it is called D(delay) FF.




D Ck


Ck 0 1 1

D X 0 1

Qn+1 Qn 0 1


This kind of FF prevents the value of D from reaching the Q o/p until clock pulse occurs. WORKING : (1) When Ck = 0, both the AND gates are disabled. Qn+1 = Qn . (2) When Ck = 1, both the gates are enabled. (a) If D = 1 then S = 1,R = 0 Qn = 1 (b) if D = 0 then S = 0, R = 1,Qn = 0 i.e. when the clock is high Qn takes the value of D. When the clock again goes low, Q retains or stores the last value of D. EDGE TRIGGERED D F F This kind of FF samples the data bit at a unique point in time. The output changes only during the transient operation of the FF brought about by the leading / trailing edge of the clock. Fig. shows a RC circuit at the input of D latch. By deliberate design, the RC time constant is much smaller than the clocks pulse width. Because of this, the capacitor can charge fully when the clock goes high, this exponential charging reduces a narrow positive voltage spike across the resistor and the trailing edge of the pulse results in a narrow -ve spike. The +ve spike enable the AND gate for an instant, the narrow negative spike does nothing. The fact is to activate the AND gates, during the +ve spike, equivalent to sampling the value of D for an instant. At this unique point in time D and its compliment hits the FF inputs, forcing Q to set or Reset. This kind of operation is called edge triggering because the FF responds only when the clock is in transition between its two voltage states. The triggering in fig. occurs on the +ve going edge of the clock and hence called +ve edge triggering. D S C A Ck R Ck R Qn Ck 0 D X 0 1 X Qn+1 Qn 0 1 Qn

No Change RESET SET No Change

A PRESET AND CLEAR When power is first applied, FFs come up in random states. To get some circuit started with initial state zero, an operator has to push a reset button.This ends a CLEAR or RESET signal to all FFs. Also it is necessary in some digital system to preset certain FF. Fig. shows the inclusion of both function in a D FF. A high PRESET forces Q = 1 and a high CLEAR resets Q to O. The preset and clear are called asynchronous inputs because they activate Ffs independent of the clock. On the other hand D input is a synchronous input because it has an effect only when clock edge occurs.




J K FF In the RS FF, R = 1 & S = 1 is not an allowed state. To avoid this JK FF is built. JK FF is basic building block of all counters. The clocked RS FF is converted into operation by adding an additional terminal to each of the input AND gates and providing an feedback connection from these terminals to the outputs as shown. Variable J & K are called control inputs because they determine what the FF does when a +ve clock edge arrives. Here RC time constant of the circuit is short, thus converting the rectangular the clock pulse into narrow spikes. Because of the AND gates, the circuit is +ve edge triggered. The circuit and the truth table for the JK FF is as shown below.:--

Ck 0

J 0 0 1 1

K 0 1 0 1

Qn+1 Qn 0 1

No Change RESET SET Toggles

WORKING (1) when J = 0, K = 0, both inputs AND gates are disabled and hence Qn+1 = Qn. (2) J = 0, K = 1, Upper gate is disabled, so there is no way to set the FF. (a) If Qn = 0 , the state of the FF will not change when clock pulse is applied. (b) If Qn = 1 so that FF is initially in the set state. Since lower gate is enabled & Q n = 1, K = 1 a clock pulse will cause the FF to shift to the reset state. (3) When J = 1, K = 0, lower gate is disabled and it will set the FF. (a) If Qn = 0, lower gate is disabled and upper gate is enabled therefore Q n = 1 , J = 1 & a clock pulse will cause the FF to shift to the set state. (b) If Qn = 1, the state of the FF will not change when the clock pulse is applied. Therefore with J = 1 & K = 0 FF will set. (4) When J = 1 & K = 1, it is possible to set or reset the FF. Thus the output state Q n & will determine which of the AND gate is enabled. (a) If Qn = 1, lower AND gate is enabled as a result of feedback connection and a clock pulse will reset the FF to Qn+1 = 0. (b) If Qn = 0, the upper AND gate is enabled & a clock pulse will set the JK FF to Q n+1 = 1. Each of these cases lead to Qn+1 = to describe this operation, where in each time the clock pulse arrives the state of the FF changes, We say that FF TOGGLES. This is analogous to the action of an ordinary toggle switch and it is this toggling that differentiates the JK FF from the RS FF. J-K MASTER SLAVE FLIP FLOP A very popular type of JK FF is the master slave FF. This connection provides a trigger method using a master FF stage, which is operated by the clock and inputs on one part of the clock cycle and a second or slave FF stage, which provides the output on the opposite clock cycle. JK M/S FF is as shown. The master is positive edge triggered and the slave is -ve edge triggered. Therefore J & K inputs operate the master FF, when the clock is high. At the same time the inverted clock signal disconnects the slave FF from the master FF. Thus when the

S.Y.P.II / II (5)SEQUENTIAL LOGIC CIRCUIT NKapoor clock is high, the inputs operate the master FF while the outputs remain unchanged then when the clock pulse goes low, the inputs are disconnected from the master FF and the slave FF is operated so that it follows the state of the master FF. Thus the output is transferred on the -ve edge of the clock.


Q >



WORKING (1) If J = 1, K = 0, master sets on +ve clock edge. The high Q output of master drives the J input of slave, so when the -ve clock edge hits, the slave sets, following masters. (2) If J = 0, K = 1, the master resets on the leading edge of the clock, the high Q output of the master goes to K input of the slave. Therefore on the -ve edge of the clock slave also resets. (3)If J = K = 1master toggles on the +ve clock edge and the slave then toggles on -ve clock edge. T FLIP FLOP In this case J = K = 1 for JK FF; FF is in the toggle state. Qn+1 = Qn i.e. FF 1 Vcc changes its state with each clock pulse. Hence output frequency will be half of clock frequency. J Q Ck > K


RIPPLE COUNTERS --- A three stage ripple counter using master slave JK FF is as shown. If in general there are N - FF used then maximum no. of counts possible is 2 N . In this case there are 3 FFs , therefore 23 = 8 and called as mod -8 counter. The FFs are connected to toggle and change state on the -ve going edge of clock input. The input signal whose pulses are to be counted is applied to the clock input of the first FF, and the output of each FF is connected directly to the clock input of the next FF and hence it is called ripple counter or asynchronous counter. The wave forms at the input and the three terminals are as shown. WORKING Initially all FFs are reset , therefore QA = QB = Qc = 0 , when first clock pulse is applied to FF - A, its -ve going edge changes QA to 1. Since QA is going from zero to 1 (+ve going edge) which is clock for FF B, QB remains unchanged. Similarly QC remains unchanged.




Q3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Therefore after the first clock pulse the output is 001. The -ve edge of the second clock pulse resets QA to 0 and the -ve edge from transition of QA from 1 to 0 causes the FF B to toggle. Hence QB changes to 1 and the output is 010. The -ve edge of the 3rd clock pulse again toggles FF A changing QA to 1. Therefore output reads as 011 and so on. After the 7th clock pulse output will be 111. When 8th clock pulse is applied, its -ve edge resets QA to 0. The -ve edge of QA resets QB. The -ve edge of QB resets QC to 0. Hence after the 8th clock pulse entire counter is reset and the output is 000. The frequency f of clock pulses for reliable operation of the counter is 1/ Ntp + Ts where N is no. of FF, tp propagation delay of one FF and Ts strobe pulse width. COUNT DOWN COUNTER A simple change of connection is all that is needed to make a count down count as shown. The Q output of each stage is now used as clock input to the following stage. We still use Q output as indication of the state of each stage as shown in count table. WORKING Starting with the counter reset state, the first input clock pulse causes Q 0 to toggle from 0 to 1. The clock pulse to second FF being taken from the Q 0 which goes from 1 to 0 at this time, so Q1 also toggles. The Q1 which goes from 1 to 0 causes Q2 to toggle which in turn toggles Q3 from 0 to 1. Thus the count goes from 0000 to 1111. The next input clock pulse toggles the Q0 from 1 to 0 but for second FF this is a +ve edge therefor Q 1 remains the same and for third & fourth FF no change in the clock therefore Q2 & Q3 remains same. The count now being 1110. Thus the count has decreased as a result of input clock pulse. In fact, the count will continue to decrease by one binary count for each input clock pulse applied.




Q3 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

Q2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

Q1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

Count 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UP-DOWN COUNTER A counter which can be made to count in either the forward or reverse direction is called up-down counter. The two level AND-OR gates between stages constitute a 2 input multiplexer, which controls the direction of the counter. This logic combination is equivalent to a NAND-NAND configuration. If count up control is 1 and countdown control is 0, counting is done in the upward direction, since then upper AND gate is enabled. If countdown control is 1 and count up control is 0 then lower AND gate is enabled and hence counting is done in the downward direction.

S.Y.P.II / II vcc Count up J Ck K Count down QA