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Silicon Photonics
Dries Van Thourhout OFC 2010 - Tutorial Fiber matched Intermediate Strip waveguide
H ~ 10um H ~ 3um
Si Si Si
H ~ 200nm
BOx
BOx
BOx
http://photonics.intec.ugent.be
Silicon Photonics
Dries Van Thourhout OFC 2010 - Tutorial Fiber matched Intermediate Strip waveguide
H ~ 10um H ~ 3um
Si Si Si
H ~ 200nm
BOx
BOx
BOx
http://photonics.intec.ugent.be
Disclaimer
This is a tutorial
Experts in the field are welcome but not intended public Not covering advanced topics
Material available:
Bogaerts e.a. , JSTQE 16, 3344 (2010) Gnan e.a., Electronic Lett. 44, p115 (2008)
Strip waveguide
Si
H ~ 200nm
Why Silicon ?
BOx
Silicon is transparent in telecom range Processing using very large existing equipment base !!! High index contrast compact circuits
But others also have sufficient contrast (e.g. SiN, HfO ) High thermo-optic effect Carrier plasma effect Integration with Germanium, III-V
http://photonics.intec.ugent.be
Strip waveguide
Si
H ~ 200nm
BOx
Very compact circuits Processing more compatible with electronics processing Active functionality enhanced
Increased light-material interaction Faster devices Lower power consumption Higher non-linear effects
http://photonics.intec.ugent.be
Strip waveguide
Si
H ~ 200nm
What do we need?
BOx
Passives
coupling
Actives
detectors
Integration
Photonics Research Group
applications
http://photonics.intec.ugent.be
Outline
low loss bend complex filters sources switches modulators
Passives
coupling
Actives
detectors
Integration
applications
http://photonics.intec.ugent.be
Outline
low loss bend complex filters sources switches modulators
Passives
coupling
Actives
detectors
Integration
applications
http://photonics.intec.ugent.be
Straight waveguide
Our standard waveguide: 450nm x 220nm Si
SiO2
[2um box]
Straight waveguide
Origin of losses ?
Straight waveguide
Origin of losses
Straight waveguide
Question:
Given certain optimization criteria What is optimal aspect ratio for waveguide ?
Popovic e.a. :
Optimisation for:
Low loss, Low sensitivity to dimensional variations High thermal optic effect
Standard
Width [um]
Popovic, PhD Thesis, MIT (2008) (http://dspace.mit.edu)
Dispersion
Bend waveguide
Our standard waveguide: 450nm x 220nm Si
Fabricated using 193nm DUV lithography In standard pilot line, on 200mm wafer Starting from SOI or amorphous silicon
Si SiO2
0.02dB/900
S.K. Selvaraja, JLT 27, p.4070 (2009) Y. A. Vlasov and S. J. McNab, Optics Express, p. 1622 (2004)
Dots: experimental results (outdated) Lines: FDTD calculations (dash: TE, dotted: TM)
15
Crossings
Standard Crossing
>1dB excess loss
<70dB crosstalk
>-10dB crosstalk
The Y-junction
Large losses for standard Y-junction Need improved design !!! Example
The Y-junction
Use Y-junctions to fabricate TO-switches
4 x 4 switch
18
Compact, but
Wavelength [nm]
1500 -5 1520
Transmission [dB]
-10
-15
-20
-25
Dumon e.a. , GFP 2004
Improved devices
0 -5 -10
1550
1555
1560
1565
1570
1575
1580
1570
1575
1580
23
Channels spacing globally fixed Low loss (1dB) 1 x N and N x N operation with same device Crosstalk > 25dB difficult to obtain Small channel spacings (<=100GHz) difficult
Reproducibility
18 identical AWGs
-30
-35
Possible causes
wafer
-55 1560
1562
1564
1566
1568
6mm
Fabrication uniformity
Measurements: IR Camera setup
screen Infrared Camera
6mm
Camera view
1588nm 1587nm 1586nm 1585nm 1584nm 1583nm 1582nm 1581nm 1580nm 1579nm 1578nm 1577nm 1576nm 1575nm 1574nm 1573nm 1572nm 1571nm 1570nm 1569nm 1568nm 1567nm 1566nm 1565nm 1564nm 1563nm 1562nm 1561nm 1560nm
Measurements
All rows
wavl
10
20
30
device#
Challenges: sensitivity
Fabrication:
Device uniformity
Influence of fabrication technology
248nm deep UV
-10 -15
-50 -40
193nm deep UV
Transmission [dBm]
Transmission [dB]
-60
-70
1530
1540
1550
1560
1570
1580
1590
1600
Wavelength [nm]
Wavelength [nm]
248nm very far of from specs 193nm <2nm variation over die
Wafer Uniformity
Thickness variation over incoming (SOITEC)
wafer
SiO2
[2um box]
Si
4nm variation within wafer 3nm variation wafer-to-wafer (within lot) 4nm lot-to-lot
Lot A
230
Lot B
226
Si thickness [nm]
Si thickness [nm]
3 [nm]
3 [nm]
14 16 18 20 22 24
4 0 0 2 4 6 8 10 12 14 16 18 20 22 24
# Wafer
# Wafer
Wafer Uniformity
Si
Linewidth variations
w
SiO2
[2um box]
Following etching
Less than 1% line width variation over 200mm wafer Much better than typical CMOS specs 1% is still 5nm !! Pure passive, further post processing may increase problem (e.g. stress ) SEM not accurate enough to characterize within die uniformity !!
Mean Range
Mean Range
Manufacturability
Proposed solution
1 m
shallow-etch apertures
50 m
J. Brouckaert et al. JLT 25(5), p1269 (2007)
Grating Demultiplexer
Channel spacing: Insertion loss: Channel uniformity: Crosstalk: Footprint: 20nm 7.5dB 0.6dB better than -30dB 250 x 150 m2
0 -5 -10
R~30%
1 m
Transmisson (dB)
1520
1540
1560
1580
Grating Demultiplexer
High Fresnel reflection loss at grating ?
TIR-mirror
DBR-mirror
Horst e.a., PTL 21, pp 1743 (2009) See also: Horst, OFC 2010, OWJ3 (invited)
Ring resonators
1 0.9
Normalized transmission
fit: Q = 15600500
R=1.5um Q=9000
1565 1565.5 1566
Wavelength [nm]
0.6 0.5 wavelength shift [nm] 0.4 0.3 0.2 HSA - HSA 0.1 BSA receptor 0 0 -0.1 Devos e.a., IEEE Photonics Journal, 1(4), p.225-235 (2009) 20 40 60 time [min] 80 no receptor 100 120 HuIgG - HuIgG Serum with anti-HuIgG
Serum with anti-HSA
Ring resonators
Ring resonators for label extractor
EU-project BOOM Need 0.1nm bandwidth filter Use silicon ring resonator ??
Label extractor Wavelength conversion
Tuning current
Tunable laser
Very sensitive to random back scattering Behaviour very unpredictable High losses
TM ring resonators ?
Very sensitive to random back scattering Behaviour very unpredictable High losses
TM ring resonators
Interleaver
Thermo-optic effect
Silicon strongly temperature dependent
Roughly: 80pm/K
17uW/GHz
~10us switching
-10
Bulk loss
-30
Wire loss
0.0
1.5
3.0
4.5
6.0
Low loss Broadband High coupling tolerance No facet reflections Waferscale testability Easy to fabricate
SOI wire
Single-mode fiber
Two solutions
Two widely used solutions
Inverted taper
0.4mm
0.2mm
Grating coupler
80nm
polished facet
500 mm
Comparison
0.4m m 0.2m m
80n m 500 mm
Loss (best) Loss (in real live) Broadband Misalignment tolerance Facet reflections
Waferscale testing
Fabrication Robustness Polarization
No
Additional layer Facet critical Facet preparation Need additional structures High performance applications
Yes
Easy to difficult Etch depth control Build in polarization diversity Low cost applications + Testing
Loss to substrate
90% simulated !
6.4 %
Overlay gratings
Break top-bottom symmetry
380nm teeth 220nm Si
0.0 -0.5
-1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 1510 1520 1530
1540
1550
1560
1570
Wavelength [nm]
Grating zoo
Focusing grating Metal gratings Polymer wedge for vertical coupling
Apodized grating
TE/TM interaction
TE-polarization TE-polarization Effective index
TE/TM interaction
TM-polarization
Effective index
Anticrossings TM-polarization
Solution:
Use SiO2 cover or index matching oil Vermeulen e.a. , ECIO 2010 Waveguide width [um]
Polarization diversity
Process both polarizations separately
split polarizations convert to the same polarization on the chip combine polarization back into the fiber
TE TM TE/TM TM TE/TM
two identical circuits
TE/TM TE
Polarization diversity
Polarization diversity with inverted taper
TE TM
TE
TE/TM
Watts et al, OL 30(9), p.937 (2005)
Polarization diversity
Polarization diversity with inverted taper
Vermeulen e.a. GPF 2010, paper WC6 See also: Wang & Dai, JOSA B, pp. 747-753 (2008)
x-polarization
y-polarization
z
y x
combine polarisations
2-D grating
D. Taillaert, PhD Thesis UGent, 2004
Slot waveguides Photonic crystal waveguides Interesting science But also: big headache
Non linearities
Outline
low loss bend complex filters sources switches modulators
Passives
coupling
Actives
detectors
Integration
applications
http://photonics.intec.ugent.be
Outline
low loss bend complex filters sources switches modulators
Passives
coupling
Actives
detectors
Integration
applications
http://photonics.intec.ugent.be
Detector
1. Hybrid integration
Prefabricated diode, E.g. flip-chip on top of grating coupler Cost effective for low density, medium speed
Detector
1. Hybrid integration 2. Heterogeneous integration through waferbonding
Detector
1. Hybrid integration 2. Heterogeneous integration through waferbonding 3. Implanted silicon, silicides
Detector
1. Hybrid integration 2. Heterogeneous integration through waferbonding 3. Implanted silicon, silicides 4. Germanium
Buffer layer ? Requires 1-10um Two step growth process Rapid melt growth
: Too thick !!
Ge-epitaxy
Two-step growth process:
BOx
Ge-epitaxy
Two-step growth process:
Si
Si
Si
BOx
BOx
BOx
Ge-detector
Two step growth butt coupling
Ge-detector
Rapid melt growth
1. Ge CVD deposition on SiON mask with small opening 2. Encapsulation 3. RTA induces melt + recristallisation to single crystal
Ge-detector
Rapid melt growth: results
Detector state-of-the-art
Table compiled by L. Vivien e.a. (IEF) for EU HELIOS project Extracted from D003 Silicon Photonics State-of-the-Art, public deliverable (http://www.helios-project.eu/)
Outline
low loss bend complex filters sources
Passives
coupling
modulators
Actives
detectors all functions
switches
with electronics
Integration
applications
http://photonics.intec.ugent.be
Modulation of light
How to make a modulator in silicon
p-i-n diode in forward bias Inject carriers into waveguides Strong effect (many carriers) Slow effect (~1GHz) p n
Carrier depletion
p-n diode in reverse bias Extract carriers from waveguide Weaker effect Fast effect (>40GHz)
Carrier accumulation
n p
Injection Modulator
100-200m length p-i-n diode MZI configuration
Ring Modulator
Speed ~2GB/s With preemphasis: >20GB/s
But
phase shifter
Ring modulator
Ring resonator in p-i-n junction
signal
Ground ground
Ring Waveguide
Outline
low loss bend complex filters
sources
switches modulators
Passives
coupling
Actives
detectors
Integration
applications
http://photonics.intec.ugent.be
Sources on Silicon
1. Hybrid integration
Sources on Silicon
1. Hybrid integration
2. Monolithic integration
Strained Ge-laser Er-doped Si nanocrystals III-V on silicon epitaxy
Sources on Silicon
1. Hybrid integration
2. Monolithic integration
3. Integration through waferbonding techniques
SOI-wafer Planarization Bonding
(a)
(b)
(c)
Substrate Removal
Pattern definition
III-V processing
(d)
(e)
(f)
III-V/Silicon photonics
Bonding of III-V epitaxial layers
Bonding Technology
Cross-sectional image of III-V/Silicon substrate
InP/InGaAsP epitaxial layer stack InP-InGaAsP epitaxial layer stack Si DVS-BCB SiO2 Si DVS-BCB Si WG SiO2
200nm
200nm
200nm bonding layer routinely and reliably obtained Recently : focus on thin
Business model ?
Option I : all CMOS-fab processing
200mm SOI wafer Bond III-V dies Process in CMOS fab
Need to cover full 200mm wafer (or 300mm ?) Need to adapt processes to CMOS fab
III-V etching
YES !!!
CH4/H2 RIE process in 200mm reactor Gold free contacts demonstrated (AlCu/TiN/Ti)
SiO2 hard mask
2 1 0 -1 -2 -100 -50 0 50 100
112m 56m 28m 14m 7m 3.5m AlCu/TiN/Ti/n-InP Chemistry before deposition Unannealed
InP
Voltage (V)
InGaAs
Current (mA)
L. Grenouillet e.a., CMOS compatible contacts and etching for InP-on-silicon active devices, GFP 2009, San Fransisco
WP5
FP lasers on silicon
AlGaInAs active layer 1.3m individual die processed
CH4/H2/O2 dry etching metallization + lift off process
pulsed operation:
L = 1mm = 1.3m P >20 mW max T = 40 C
20
2007
Power (mW)
15
10
Current (mA)
Confidential
93
Business model ?
Option I : all CMOS-fab processing
200mm SOI wafer
CMOS compatible III-V processing currently not commercially available ! Only if silicon is cheap !
IBM 130nm RF-CMOS cut to 3 inch wafers BCB-bonded unprocessed InP dies
Y. Royter e.a. , "Technology for Dense Heterogeneous Integration of InP HBTs and CMOS," in CS Mantech, Tampa, Florida, 2009
Business model
Die bonding
OR
Wafer bonding...
Edge effects may induce bonding effects Independent of size silicon wafer (200mm, 300mm ) Total required material may be smaller Rapid pick and place process required
Currently more reliable process Largest wafers now available 150mm, 100mm more standard Single step process
CEA-LETI
UCSB-INTEL
intec 2009 - Photonics Research Group - http://photonics.intec.ugent.be
Design options
Light centred in Silicon Light centred in III-V
Low overlap with III-V : low gain high saturation threshold Not compatible with sub400nm silicon thickness
Also:
Microdisk laser
2Rdisk top contact active layer InP t tunnel junction ts dox Si waveguide wSi SiO2
Microdisk laser
Si substrate
om contact
Whispering gallery mode Evanescent coupling to silicon 150-350uA threshold 120uW output power (CW)
45 40 35 30 25 20 15 10 5 0 0 1 2 Current [mA] 3 4 2.5 2 1.5 1 0.5 0 -0.5 Voltage [V]
-10 -20 -30 -40 -50 -60 -70 -80 1544 1564 1584 1604 1624 Fiber coupled output power [uW] Wavelength [nm] Spectral power [dBm]
Microdisk device
Very flexible device
20GHz All-optical wavelength conversion 10GHz All-optical gate Electro-optic modulation All-optical switching All-optical flip-flop
Kumar e.a. ,OFC2010, paper JWA44 Liu e.a. , Optics Letters, 33(21), p.2518 (2008)
Whats next ?
WDM optical intraconnections on chip with a fully CMOS compatible process (EU WADIMOS project http://wadimos.intec.ugent.be/)
Outline
Passives
coupling
Actives
detectors
Integration
applications
http://photonics.intec.ugent.be
Front-end: no thermal budget Integrated in CMOS flow (on SOI only) High process development cost Compound yield Little flexibility Optical layer buried
On top of CMOS (or in metal layers) Parallel process No compound yield Serial process problem with die-to- wafer Compound yield stacking (known good die)
Flexible choice of electronics and photonics Other layers possible: MEMS, antennas Optical layer on top is possible
EPIC project
Front-end: no thermal budget Integrated in CMOS flow (on SOI only) High process development cost Compound yield Little flexibility Optical layer buried
Beals e.a., SPIE Phot West 2008
MIT
CEA-Leti
3-D: on top of CMOS No thermal budget Parallel process No compound yield problem with die-to- wafer stacking (known good die) Flexible choice of electronics and photonics Other layers possible: MEMS, antennas Optical layer on top is possible
IMEC
Top chip
Cu nail
Bottom chip
Cu pad
detectors
Time to integrate and find the right application with electronics Integration
applications
http://photonics.intec.ugent.be
ePIXfab
Silicon photonics in CMOS fab
Cheap for volume production Expensive and difficult access for research and prototyping
Solution ? ePIXfab
Multi-project wafer shuttles allow cost sharing Joint initiative of IMEC and LETI Supported by EU-commission Open for research and prototyping
www.epixfab.eu
wafers distributed
Supported by PhotonFAB
Coordinator:
Pieter Dumon pieter.dumon@imec.be
Acknowledgements
Thanks to