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CSCI 510/610: Advanced Computer Architecture Implementing a Datapath in Verilog A Lab Manual

George M. Georgiou and Scott McWilliams

Computer Science Department California State University, San Bernardino 1 October 2003
Revision: 1.12, April 4, 2004

The development of this lab manual has been supported in part by a Course Development Grant from the Teaching Resource Center, CSUSB.

Contents

Contents List of Code Listings List of Figures

1 2 3

I
1

Lab Manual

The MIPS datapath in Verilog: The IF stage Lab 11 1.1 Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lab 15 The ID pipeline stage. Lab 21

2 3

The EX pipeline stage Lab 31 3.1 Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lab 35 The MEM pipeline stage. The WB pipeline stage Testing the MIPS datapath Lab 41 Lab 51 Lab 61 Bib 1

4 5 6

Bibliography

List of Code Listings

1.1 1.2 1.3 3.1 3.2 3.3 6.1 6.2

Verilog code for the multiplexer. . . . . . . . . . . . . . . . . . . . The testbench for the multiplexor in gure 1.5 on page Lab 14 . . . The testbench for the incrementer in gure 1.6 on page Lab 14 . . The testbench for the 5-bit multiplexor in gure 3.3 on page Lab 33 The testbench for the ALU control in gure 3.4 on page Lab 34 . . The testbench for the ALU in gure 3.5 on page Lab 34 . . . . . . Binary code for testing the MIPS datapath. . . . . . . . . . . . . . . Initial data for memory. . . . . . . . . . . . . . . . . . . . . . . . .

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Lab 13 Lab 16 Lab 17 Lab 36 Lab 37 Lab 39 Lab 62 Lab 62

List of Figures

1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9

The revised MIPS datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The IF stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The instruction memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The incrementer by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The IF/ID pipeline register (latch) . . . . . . . . . . . . . . . . . . . . . . . . . . The output when running the testbench for the multiplexer (listing 1.2 on page Lab 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The output when running the testbench for the incrementer (listing 1.3 on page Lab 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The ID stage . . . . . . . . . . . . . . . . . . . . . . . ALUOp Control Bit and Function Code Sets (after [4]) The sign-extend unit . . . . . . . . . . . . . . . . . . The control unit . . . . . . . . . . . . . . . . . . . . . The register le . . . . . . . . . . . . . . . . . . . . . The ID/EX pipeline register (latch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lab 12 Lab 12 Lab 13 Lab 13 Lab 14 Lab 14 Lab 14 Lab 15 Lab 15 Lab 22 Lab 22 Lab 23 Lab 23 Lab 24 Lab 24 Lab 32 Lab 32 Lab 33 Lab 34 Lab 34 Lab 34 Lab 35 Lab 35 Lab 38 Lab 38 Lab 42 Lab 42 Lab 43 Lab 43

2.1 2.2 2.3 2.4 2.5 2.6 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8

The EX stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ALUOp Control Bit and Function Code Sets (after [4]) . . . . . . . . . . . . . . . The multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The ALU control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The EX/MEM pipeline register (latch) . . . . . . . . . . . . . . . . . . . . . . . . The output when running the testbench for the 5-bit multiplexer (listing 3.1 on page Lab 36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 The output when running the testbench for the ALU control (listing 3.2 on page Lab 37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 The output when running the testbench for the ALU (listing 3.3 on page Lab 39) . 4.1 4.2 4.3 4.4 The MEM stage . . . . . . . . . . . . The and gate . . . . . . . . . . . . . . The data memory unit . . . . . . . . . The MEM/WB pipeline register (latch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LIST OF FIGURES

LIST OF FIGURES

5.1 5.2

The WB stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lab 51 The multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lab 52

Part I

Lab Manual

LAB

The MIPS datapath in Verilog: The IF stage

Objective: To implement and test the Instruction Fetch (IF) pipeline stage of the MIPS ve stage pipeline.

The series of labs in this manual has ultimate objective to implement and simulate in Verilog the MIPS pipeline datapath Figure 6.30 in Paterson and Hennessys textbook [4]. The model will be structural (as opposed to behavioral), but with one exception: basic units, such as multiplexors and ALUs, may implemented as behavioral models. This approach reinforces the object-oriented style of programming, while at the same time relieving from the burden of structurally dening the basic units, which can be quite tedious, time consuming, and beyond the scope of this lab series. The slightly revised MIPS datapath to be implemented is in gure 1.1 on page Lab 12. For this week, you will implement the IF stage and test the fetching of instructions from memory. The IF stage isolated from the rest of the datapath can be seen in gure 1.2 on page Lab 12. The names of the pipeline registers are IF ID, ID EX, EX MEM, MEM WB. For now, you will need only IF ID and EX MEM. The instruction memory has 128 32-bit words. Later it will be expanded. All instructions and the PC are 32-bit wide. (Simply the 7 least signicant bits (27 = 128) are used for the time being.) Implement the instruction memory, 2x1 MUX, and Incrementer-by-4 as separate modules. For the time being consider that the 1-bit signal PCSrc comes from a 1-bit register, PC choose. Initialize IF ID IR (The instruction eld of IF/ID) to 32 zeros. Initialize IF ID NPC to 32 zeros. Initialize PC choose and EX MEM NPC to zeros. They will not change during this simulation. Initialize the rst 10 words of memory (with addresses 0, 4, 8, etc.) with the following HEX values:

Lab 11

LAB 1

The MIPS datapath in Verilog: The IF stage

PCSrc

ID/EX 2

\
0

WB M EX

EX/MEM WB WB M MEM/WB WB

IR

[31:26]
Control

M ux

\
4

IF/ID

Add 1 IR IR PC
Address Add result Reg i Wr t e Branch AL rc US

Add

[25:21] [20:16]

M mWr e i t e

Read reg 1 Read data 1 Zero Read reg 2 0

ALU
ALU result Address Read data

Mux

Instruction memory

IR

Registers
Write reg Read data 2 Write data

Data memory
Write data Me ad mRe

IR

[15:0]

16

32
Sign extend

IR

[5:0]

ALU control

IR IR

[20:16] [15:11]

ALUOp

Mux

RegDst

Figure 1.1: The revised MIPS datapath

PCSrc From EX/MEM latch

Component 1
1

Mu x

IF/ID

Component 2 1

Add

To ID/EX latch

PC Component 3 Component 4

Address

Instruction memory

IR

Component 5

Figure 1.2: The IF stage

Lab 12

M ux

Me o mtReg 1

LAB 1

The MIPS datapath in Verilog: The IF stage

module mux ( a , b , s e l , y ) ; input [31:0] a, b ; input sel ; output [31:0] y ; assign y = sel ? a : b; endmodule Listing 1.1: Verilog code for the multiplexer.

A00000AA 10000011 20000022 30000033 40000044 50000055 60000066 70000077 80000088 90000099 Turn in the source code and the printout of the clock cycle number, the contents of the PC (in decimal), IF ID IR (in hex), and IF ID NPC (in decimal) for 10 cycles of simulation. Be ready to demonstrate. Note: The code in listing 1.1 implements the multiplexer in the IF stage as a combinational circuit.

32

32

npc

PC

PC

Figure 1.3: The program counter (PC)

addr

32

Address

Instruction memory

32

data

Figure 1.4: The instruction memory

Lab 13

LAB 1

The MIPS datapath in Verilog: The IF stage

sel \
1 32

Mx u

32

32

Figure 1.5: The multiplexer

32

pcin

\
32

Add \
1

pcout

Figure 1.6: The incrementer by 1

32

32

npc

npcout

32

32

instr

instrout

Figure 1.7: The IF/ID pipeline register (latch)

Lab 14

LAB 1

1.1. TESTBENCHES

1.1

Testbenches

Testbenches help us verify that the design is correct. In this subsection we show two testbenches: One in listing 1.2 on page Lab 16 for the multiplexer of gure 1.5 on page Lab 14 and one in listing 1.3 on page Lab 17 for the incrementer of gure 1.6 on page Lab 14 . The results of the running the testbench are in gure 1.8 and in gure 1.9, respectively. In the latter, and in other testbench runs in the labs that follow, the standard messages of the runs will be largely omitted. Beginning Compile Beginning Phase I Compiling source file: muxtest.v Compiling included source file mux.v Continuing compilation of source file muxtest.v Finished Phase I Entering Phase II... Finished Phase II Entering Phase III... Finished Phase III Highest level modules: test_mux Compile Complete . Running... At t = 11 sel = 1 A = 00000000 B = 55555555 Y = 00000000 At t = 31 sel = 1 A = 00000000 B = ffffffff Y = 00000000 At t = 36 sel = 1 A = a5a5a5a5 B = ffffffff Y = a5a5a5a5 At t = 41 sel = 0 A = a5a5a5a5 B = dddddddd Y = dddddddd At t = 46 sel = x A = a5a5a5a5 B = dddddddd Y = XXXXXXXX 0 Errors, 0 Warnings Compile time = 0.00000, Load time = 0.00000, Execution time = 0.00000 Normal exit

Figure 1.8: The output when running the testbench for the multiplexer (listing 1.2 on page Lab 16)

Running... Time = 11 A=3 IncrOut=4 Time = 21 A=15 IncrOut=16 Time = 31 A=64 IncrOut=65

Figure 1.9: The output when running the testbench for the incrementer (listing 1.3 on page Lab 17)

Lab 15

LAB 1

1.1. TESTBENCHES

/ / Filename / / Description // i n c l u d e mux . v module t e s t m u x ; / / Wire P o r t s w i r e [ 3 1 : 0 ] Y;

: t e s t mux . v : T e s t i n g t h e 32 b i t m u x module of t h e IF s t a g e of t h e p i p e l i n e .

/ / Register Declarations r e g [ 3 1 : 0 ] A, B ; reg sel ; MUX mux1 ( Y, A, B, s e l ) ; i n i t i a l begin A = 32 hAAAAAAAA; B = 32 h55555555 ; s e l = 1 b1 ; #10 ; A = 32 h00000000 ; #10 s e l = 1 b1 ; #10 ; B = 32 hFFFFFFFF ; #5 ; A = 32 hA5A5A5A5 ; #5 ; s e l = 1 b0 ; B = 32 hDDDDDDDD; #5 ; s e l = 1 bx ; end a l w a y s @(A o r B o r s e l ) #1 $ d i s p l a y ( At t = %0d s e l = %b A = %h B = %h Y = %h , $ t i m e , s e l , A, B, Y) ; endmodule // test / / i n s t a n t i a t e t h e mux

Listing 1.2: The testbench for the multiplexor in gure 1.5 on page Lab 14

Lab 16

LAB 1

1.1. TESTBENCHES

/ / Filename / / Description // include i n c r . v module t e s t ( ) ;

: t e s t i n c r . v : T e s t f o r i n c r . v , an i n c r e m e n t e r by 1 (32 b i t i n p u t )

/ / P o r t Wires wire [ 3 1 : 0 ] IncrOut ; / / Register Declarations r e g [ 3 1 : 0 ] A; INCR i n c r 1 ( I n c r O u t , A) ; i n i t i a l begin #10 A = 3; #10 ; A = 15; #10 A = 64; #5 ; end a l w a y s @(A) #1 $ d i s p l a y ( Time = %0d \ tA=%0d \ t I n c r O u t =%0d , $ t i m e , A, IncrOut ) ; endmodule // test / / i n s t a n t i a t e the incrementer

Listing 1.3: The testbench for the incrementer in gure 1.6 on page Lab 14

Lab 17

LAB

The ID pipeline stage.

Objective: To implement and test the Instruction Decode (ID) pipeline stage and integrate it with the IF stage.

This is part of a series of labs to implement the MIPS Datapath (gure 1.1 on page Lab 12) as a behavioral model in Verilog and simulate it. For this week, you will implement the ID stage gure 2 on page Lab 22, integrate it together with the IF stage of last week, and test both together. The parent module PIPELINE instantiates I FETCH (from the previous lab) and I DECODE. The module I DECODE instantiates the modules CONTROL, REG, S EXTEND, and ID EX The CONTROL module has input the opcode eld of the IF ID instr and output is the 9-bit control bits which are shown in gure 2.2 on page Lab 22. The register le REG, which has 32 general purpose registers, and has input the rs and rt elds of IF ID instr, MEM WB Writereg, MEM WB Writedata, and RegWrite (for the time being it can be from anywhere). Outputs are the contents of register rs and register rt. The combinational module S EXTEND receives as input the 16-bit immediate eld of IF ID instr and output is the 32 bit sign-extended value. The ID EX module includes the pipeline register ID/EX and inputs the outputs of the CONTROL, REG, S EXTEND modules, as well as the IF ID NPC, IF ID Instr[20-16] and IF ID Instr[15-11]. Outputs are the control bits (9 bits) NPC, Reg[rs], Reg[rt], signExtended (32 bit), Instr[20-16], and Instr[15-11]. Testing: Initialize memory to the following hex values, beginning with location 0, and label and print out the outputs of the ID EX register. The control bits should be binary and all other values should be decimal. Simulate for sufcient cycles so that all instructions go through the ID EX register.

Lab 21

LAB 2

The ID pipeline stage.

ID/EX
2

\
IR [31:26] Control 3

WB M EX

WB

\
4

M RegDst ALUOp ALUSrc

Component 1

From IF/ID latch RegWrite

To EX adder

IR [25:21] IR [20:16] Read reg 2 Read reg 1 Read data 1 To EX ALU

Registers
From MEM/WB latch Write reg Read data 2 Write data To EX Mux 0 and EX/MEM latch

From WB mux

Component 2

IR [15:0] From IF/ID latch

16

32 Sign extend

\
Component 3
IR [20:16]

IR

To EX Mux 0 IR [15:11] To EX Mux 1

Component 4

Figure 2.1: The ID stage

Figure 2.2: ALUOp Control Bit and Function Code Sets (after [4])

Lab 22

LAB 2

The ID pipeline stage.

002300AA 10654321 00100022 8C123456 8F123456 AD654321 13012345 AC654321 12012345 Turn in the source code and the printout of the clock cycle number and outputs off the ID EX register, as in testing above. Be ready to demonstrate.

16

Sign extend

32

Figure 2.3: The sign-extend unit

\ opcode
6 3

WB M EX controlbits

Control \
4

Figure 2.4: The control unit

Lab 23

LAB 2

The ID pipeline stage.

regwrite
1

rs rt rd

\
5

Read reg 1 Read data 1 Read reg 2

32

\
5

Registers
Write reg
32

32

Read data 2 Write data

writedata

Figure 2.5: The register le

2 WB M EX

ctlwb_out ctlm_out ctlex_out

\
3

\
3

wb_ctlout m_ctlout ex_ctlout

\
4

\
4

\
32

\
32

npc

\
32

\
32

npcout

readdat1

\
32

\
32

rdata1out

readdat2 signext_out instr_2016 instr_1511

\
32

\
32

rdata2out s_extendout instrout_2016 instrout_1511

\
5

\
5

\
5

\
5

Figure 2.6: The ID/EX pipeline register (latch)

Lab 24

LAB

The EX pipeline stage

Objective: To implement and test the Execution (EX) pipeline stage and integrate it with the IF and ID stages.

This is part of a series of labs to implement the MIPS Datapath (gure 1.1 on page Lab 12) as a behavioral model in Verilog and simulate it. For this week, you will implement the EX stage gure 3 on page Lab 32, integrate it together with the IF and ID stages of the previous week, and test three of them together. The parent module PIPELINE instantiates I FETCH (from the previous lab) and I DECODE. CHANGE: Please note that the Shift left 2 unit that exists in Figure 6.30 in Paterson and Hennessys book [4], is eliminated in gure 1.1 on page Lab 12. Now there is direct line from the input of Shift left 2 to its output. The parent module PIPELINE instantiates I FETCH, and I DECODE, and I EXECUTE. The module I EXECUTE instantiates the following modules ADDER for the branch target address computation. The ALU CONTROL. Inputs are ALUop bits and the function bits. The specication is found in gure 1 on page Lab 13. The instructions to be implemented are specied in the gure 3.2 on page Lab 32, and they are add, subtract, and, or, set less than. If the input information does not correspond to any valid instruction, ALUop = 11 and ALU output is 32 xs. BOTTOM MUX. Notice that the inputs and output are 5 bits. ALU MAX. Notice that you may instantiate the previously made MUX in the IF stage. ID MEM, the pipeline register. In the I FETCH module we have resetmargins=true reg reg [31:0] EX MEM PCSrc ; EX MEM NPC ;

Move the above to the EX MEM module, since EX MEM exists now, and make them as inputs to the I FETCH module.

Lab 31

LAB 3

The EX pipeline stage

EX/MEM
From ID/EX latch

WB M

MEM/WB latch MemRead MemWrite MEM Branch

From ID/EX latch

From ID/EX latch

Component 1

Add result

To IF mux

Add

Component 2
From ID/EX latch

Component 3
0

Zero

To MEM Branch To MEM Data memory and MEM/WB latch

ALU
ALU result

1 From ID/EX latch ALUSrc To MEM Data memory

Component 4
IR [5:0] From ID/EX latch IR [20:16] From ID/EX latch 0 6

Mu x

ALU control

Mu x

Component 5
IR [15:11] From ID/EX latch

ALUOp To MEM/WB latch

Component 6

RegDst

Figure 3.1: The EX stage

Figure 3.2: ALUOp Control Bit and Function Code Sets (after [4])

Lab 32

LAB 3

The EX pipeline stage

Testing: Initialize memory to the following hex values, beginning with location 0, and label and print out the outputs of the ID EX and EX MEM registers. The control bits should be binary and all other values should be decimal. Simulate for sufcient cycles so that all instructions go through the EX MEM register. 002300AA 10654321 00100022 8C123456 8F123456 AD654321 13012345 AC654321 12012345 Be ready to use initialize memory with a given different set of instructions. Turn in the source code and the printout of the clock cycle number and outputs of the ID EX register and the EX MEM register. Be ready to demonstrate.

sel
1

Mx u

Figure 3.3: The multiplexer

Lab 33

LAB 3

The EX pipeline stage

funct

ALU control

select

alu_op

Figure 3.4: The ALU control unit

32

zero result

ALU
32

32

\
3

control
Figure 3.5: The ALU

32

add_in1

\
32

\
Add

add_out

32

add_in2

Figure 3.6: The adder

Lab 34

LAB 3

3.1. TESTBENCHES

2 WB M

ctlwb_out ctlm_out adder_out

\
3

\
3

wb_ctlout m_ctlout add_result

\
32

\
32

\
1

\
1

aluzero

\
32

\
32

zero

aluout

\
32

\
32

alu_result

readdat2
5

\
5

rdata2out

muxout

five_bit_muxout

Figure 3.7: The EX/MEM pipeline register (latch)

3.1

Testbenches

Testbenches and their corresponding outputs are given for the 5-bit multiplexer (gure 3.3 on page Lab 33 and listing 3.1 on page Lab 36), the ALU control unit (gure 3.4 on page Lab 34 and listing 3.2 on page Lab 37), and the ALU (gure 3.5 on page Lab 34 and listing 3.3 on page Lab 39). The results of running the testbench for the multiplexer are in gure 3.8, for the ALU control unit in gure 3.9 on page Lab 38, and for the ALU in gure 3.10 on page Lab 38. Running... At t = 11 sel = 1 A = At t = 31 sel = 1 A = At t = 36 sel = 1 A = At t = 41 sel = 0 A = At t = 46 sel = x A = 0 Errors, 0 Warnings Normal exit

00000 00000 00101 00101 00101

B B B B B

= = = = =

10101 11111 11111 11101 11101

Y Y Y Y Y

= = = = =

00000 00000 00101 11101 xx101

Figure 3.8: The output when running the testbench for the 5-bit multiplexer (listing 3.1 on page Lab 36)

Lab 35

LAB 3

3.1. TESTBENCHES

/ / Filename / / Description //

: t e s t 5b i t m u x . v : T e s t i n g t h e 5 b i t m u x module o f t h e EX s t a g e o f t h e p i p e l i n e .

i n c l u d e 5 b i t mux . v module t e s t ( ) ; / / Wire P o r t s w i r e [ 4 : 0 ] Y; / / Register Declarations reg [ 4 : 0 ] A, B ; reg sel ; MUX5 mux1 ( Y, A, B, s e l ) ; i n i t i a l begin A = 5 b01010 ; B = 5 b10101 ; s e l = 1 b1 ; #10 ; A = 5 b00000 ; #10 s e l = 1 b1 ; #10 ; B = 5 b11111 ; #5 ; A = 5 b00101 ; #5 ; s e l = 1 b0 ; B = 5 b11101 ; #5 ; s e l = 1 bx ; end a l w a y s @(A o r B o r s e l ) #1 $ d i s p l a y ( At t = %0d s e l = %b A = %b B = %b Y = %b , $ t i m e , s e l , A, B, Y) ; endmodule // test / / i n s t a n t i a t e t h e mux

Listing 3.1: The testbench for the 5-bit multiplexor in gure 3.3 on page Lab 33

Lab 36

LAB 3

3.1. TESTBENCHES

/ / Filename : t e s t a l u c o n t r o l . v / / Description : T e s t i n g t h e ALU c o n t r o l module // o f t h e EX s t a g e o f t h e p i p e l i n e . i n c l u d e a l u c o n t r o l . v module t e s t ( ) ; / / Wire P o r t s wire [ 2 : 0 ] s e l e c t ; / / Register Declarations reg [1:0] alu op ; reg [5:0] funct ; ALU CONTROL a l u c o n t r o l 1 ( s e l e c t , a l u o p , f u n c t , ) ; i n i t i a l begin a l u o p = 2 b00 ; f u n c t = 6 b100000 ; $ m o n i t o r ( ALUOp = %b \ t f u n c t = %b\ t s e l e c t = %b , a l u o p , f u n c t , select ) ; #1 a l u o p = 2 b01 ; f u n c t = 6 b100000 ; #1 a l u o p = 2 b10 ; f u n c t = 6 b100000 ; #1 f u n c t = 6 b100010 ; #1 f u n c t = 6 b100100 ; #1 f u n c t = 6 b100101 ; #1 f u n c t = 6 b101010 ; #1 $finish ; end endmodule / / test

Listing 3.2: The testbench for the ALU control in gure 3.4 on page Lab 34

Lab 37

LAB 3

3.1. TESTBENCHES

Running... ALUOp = 00 funct = 100000 select ALUOp = 01 funct = 100000 select ALUOp = 10 funct = 100000 select ALUOp = 10 funct = 100010 select ALUOp = 10 funct = 100100 select ALUOp = 10 funct = 100101 select ALUOp = 10 funct = 101010 select Exiting VeriLogger at simulation 0 Errors, 0 Warnings Normal exit

= 010 = 110 = 010 = 110 = 000 = 001 = 111 time 7000

Figure 3.9: The output when running the testbench for the ALU control (listing 3.2 on page Lab 37)

Running... A = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx B = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ALUOp = 011 result = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ALUOp = 100 result = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ALUOp = 010 result = 00000000000000000000000000010001 ALUOp = 111 result = 00000000000000000000000000000000 ALUOp = 011 result = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ALUOp = 110 result = 00000000000000000000000000000011 ALUOp = 001 result = 00000000000000000000000000001111 ALUOp = 000 result = 00000000000000000000000000000010 Exiting VeriLogger at simulation time 8000 0 Errors, 0 Warnings Normal exit

Figure 3.10: The output when running the testbench for the ALU (listing 3.3 on page Lab 39)

Lab 38

LAB 3

3.1. TESTBENCHES

/ / Filename / / Description include alu . v module t e s t ( ) ;

: t e s t a l u . v : T e s t module f o r t h e ALU

/ / Register Declarations r e g [ 3 1 : 0 ] A,B ; reg [02:0] c o n t r o l ; / / Wire P o r t s wire [ 3 1 : 0 ] r e s u l t ; wire zero ; i n i t i a l begin A <= b1010 ; B <= b0111 ; c o n t r o l <= b011 ; $ d i s p l a y ( A = %b \ tB = %b , A, B ) ; $ m o n i t o r ( ALUOp = %b \ t r e s u l t = %b , c o n t r o l , r e s u l t ) ; #1 c o n t r o l <= b100 ; #1 c o n t r o l <= b010 ; #1 c o n t r o l <= b111 ; #1 c o n t r o l <= b011 ; #1 c o n t r o l <= b110 ; #1 c o n t r o l <= b001 ; #1 c o n t r o l <= b000 ; #1 $finish ; end ALU ALU1 ( r e s u l t , z e r o , A, B, c o n t r o l ) ; endmodule / / test

Listing 3.3: The testbench for the ALU in gure 3.5 on page Lab 34

Lab 39

LAB

The MEM pipeline stage.

Objective: To implement and test the Memory (MEM) pipeline stage and integrate it with the IF, ID, and EX stages.

This is part of a series of labs to implement the MIPS Datapath (gure 1.1 on page Lab 12) as a behavioral model in Verilog and simulate it. For this week, you will implement the MEM stage gure 4 on page Lab 42, and integrate it together with the IF, ID, and EX stages of previous weeks, and test all of them together. The parent module PIPELINE instantiates I FETCH (from the previous lab) and I DECODE. The parent module PIPELINE instantiates I FETCH, I DECODE, I EXECUTE, MEM, and WB modules. The module MEMORY instantiates the following modules: D MEM: the data memory module. Data memory has 256 32-bit words. MEM WB: The pipeline register MEM/WB. The I FETCH module should receive inputs write data, write register and RegWrite from the MEM modules. Testing: Initialize memory to the following hex values, beginning with location 0, and label and print out the outputs of the ID EX, EX MEM, and MEM registers. The control bits should be binary and all other values should be decimal. Simulate for sufcient cycles so that all instructions go through the MEM WB register. 002300AA 10654321 00100022 8C123456 8F123456 AD654321 13012345 AC654321 12012345 Be ready to use initialize memory with a given different set of instructions. Turn in the source code and the printout of the clock cycle number and outputs the ID EX register, the EX EM register, and the MEM WB register. Be ready to demonstrate.

Lab 41

LAB 4

The MEM pipeline stage.

MEM/WB
From EX/MEM latch

WB

RegWrite MemtoReg

Branch From EX/MEM latch From EX ALU zero PCSrc

Component 1
MemWrite

From EX/MEM latch

Address Read data To WB mux 1

Component 2
From EX/MEM latch

Data memory
Write data

MemRead To WB mux 0

From EX mux

To ID Registers

Component 3

Figure 4.1: The MEM stage

m_ctlout zero

AND

PCSrc

Figure 4.2: The and gate

Lab 42

LAB 4

The MEM pipeline stage.

MemWrite
1

32

Address

Address Read data

32

Read_data

Data memory
32

Write_data

Write data

MemRead

Figure 4.3: The data memory unit

2 WB

control_wb_in Read_data_in

\
32

\
32

mem_control_wb Read_data

\
32

\
32

ALU_result_in

\
5

\
5

mem_ALU_result

Write_reg_in

mem_Write_reg

Figure 4.4: The MEM/WB pipeline register (latch)

Lab 43

LAB

The WB pipeline stage

Objective: To implement and test the Write-back (WB) pipeline stage and integrate it with the IF, ID, EX, and MEM stages.

This is part of a series of labs to implement the MIPS Datapath (gure 1.1 on page Lab 12) as a behavioral model in Verilog and simulate it. For this week, you will implement the WB stage gure 5, and integrate it together with the IF, ID, EX, and MEM stages of previous weeks, and test all of them together.
MemtoReg

From MEM/WB latch

Mu x

Component 1
From MEM/WB latch 0

To ID Registers

Figure 5.1: The WB stage The parent module PIPELINE instantiates I FETCH (from the previous lab) and I DECODE. The parent module PIPELINE instantiates I FETCH, I DECODE, I EXECUTE, MEM, and WB modules. The module WB instantiates the following module: MUX, the multiplexer at the output of MEM/WB. Instantiate the multiplexer at the IF stage. The WB module receives inputs from the MEM WB module MemeReg, ReadData, ALUResult, and gives output WriteData.

Lab 51

LAB 5

The WB pipeline stage

Testing: Initialize memory to the following hex values, beginning with location 0, and label and print out the outputs of the ID EX, EX MEM, and MEM registers. The control bits should be binary and all other values should be decimal. Simulate for sufcient cycles so that all instructions go through the MEM WB register. 002300AA 10654321 00100022 8C123456 8F123456 AD654321 13012345 AC654321 12012345 Be ready to use initialize memory with a given different set of instructions. Turn in the source code and the printout of the clock cycle number and outputs the ID EX register, the EX EM register, and the MEM WB register. Be ready to demonstrate.

MemtoReg \
1 32

mem_Read_data

Mx u

32

wb_data

32

mem_ALU_result

Figure 5.2: The multiplexer

Lab 52

LAB

Testing the MIPS datapath

Objective: To implement and test the MIPS datapath which was built in the previous labs.

This is part of a series of labs to implement the MIPS Datapath (gure 1.1 on page Lab 12) as a behavioral model in Verilog and simulate it. For this week you will test the datapath with the given binary program in listing 6.1 on page Lab 62. Save it to le named risc.txt. Also the initial contents of memory are given in listing 6.2 on page Lab 62. Save it to a le named data.txt.

How to read data in the instruction memory (in the instruction memory module):
i n i t i a l begin $readmemb ( r i s c . t x t ,MEM) ; f o r ( i =0; i< 24; i = i +1) $ d i s p l a y (MEM[ i ] ) ; end Similarly for the data memory module: i n i t i a l begin $readmemb ( d a t a . t x t ,MEM) ; f o r ( i =0; i< 6 ; i = i +1) $ d i s p l a y (MEM[ i ] ) ; end You must add the NOP instruction in the control module. Its opcode is 100000 and the output of the control unit should be all zeros. Make sure that r0 is initialized to zero. For testing, display registers r1, r2, and r3 from the ID/EX module. Register r1 should have values 1, 3, 6, 12, ... Simulate for 24 cycles.

Lab 61

LAB 6

Testing the MIPS datapath

/ / Program t h a t a d d s t h e numbers ( 1 + 2 ) / / And p l a c e s 12 i n r e g i s t e r 1 100011 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 100011 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 100011 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000000 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000000 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000000 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000000 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

+ 3 + 6 + 0 = 12 / / LW r 1 , / /LW r 2 , / /LW r 3 , / / NOP / / NOP / / ADD r 1 , / / NOP / / NOP / / NOP / / ADD r 1 , / / NOP / / NOP / / NOP / / ADD r 1 , / / NOP / / NOP / / NOP / / NOP / / ADD r 1 , / / NOP / / NOP / / NOP / / NOP / / NOP 1( r0 ) 2( r0 ) 3( r0 )

r 1 , r2

r 1 , r3

r 1 , r1

r 1 , r0

Listing 6.1: Binary code for testing the MIPS datapath.

/ / Contents of 0000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0

data 0000 0000 0000 0000 0000 0000

memory 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

0000 0000 0000 0000 0000 0000

0000 0001 0010 0011 0100 0101

// // // // // //

Data Data Data Data Data Data

0 1 2 3 4 5

Listing 6.2: Initial data for memory.

Lab 62

Bibliography

[1] Michael D. Ciletti. Modeling, synthesis, and rapid prototyping with the Verilog HDL. PrenticeHall, 1999. [2] Dr. Daniel C. Hyde. CSCI 320 Computer Architecture Handbook on Verilog HDL. Bucknell University, 1997. [3] IEEE - Institute of Electrical and Electronics Engineers. IEEE 1364-1995 Verilog Language Reference Manual, 1995. [4] David A. Patterson and John L. Hennessy. Computer Organization & Design: The Hardware/Software Interface (Second Edition). Morgan Kaufmann, San Mateo, 1998. [5] D. Thomas and P. Moorby. The Verilog Hardware Description Language. Kluwer Academic, 1991.

Bib 1