Dfsdffds

14-Bit, 125 MSPS/105 MSPS, 1.
8 V Dual Analog-to-Digital Converter
AD9648
FEATURES
1.8 V analog supply operation 1.8 V CMOS or LVDS outputs SNR = 74.5 dBFS @ 70 MHz SFDR = 91 dBc @ 70 MHz Low power: 78 mW/channel ADC core @ 125 MSPS Differential analog input with 650 MHz bandwidth IF sampling frequencies to 200 MHz On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = 0.35 LSB Serial port control options Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment
FUNCTIONAL BLOCK DIAGRAM

AVDD AGND SDIO SCLK CSB
SPI
CMOS/LVDS OUTPUT BUFFER
ORA D13A D0A DCOA
VIN+A ADC VINA
PROGRAMMING DATA
VREF SENSE VCM RBIAS VINB ADC VIN+B REF SELECT
MUX OPTION
AD9648
DRVDD
CMOS/LVDS OUTPUT BUFFER
ORB D13B D0B DCOB
DIVIDE 1 TO 8
DUTY CYCLE STABILIZER
MODE CONTROLS
CLK+ CLK
SYNC
DCS
PDWN DFS OEB

09975-001
APPLICATIONS
Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR
NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES.
Figure 1.
PRODUCT HIGHLIGHTS
1. The AD96481 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or LVDS logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments. The AD9648 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9650/ AD9269/AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9628/AD9231 12-bit ADCs, and the AD9608/AD9204 10-bit ADCs, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.
2.
3.
4.
This product is protected by a U.S patent.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 2011 Analog Devices, Inc. All rights reserved.
AD9648 TABLE OF CONTENTS

Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 DC Specifications ........................................................................... 4 AC Specifications ........................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications ................................................................ 8 Timing Specifications .................................................................. 9 Absolute Maximum Ratings.......................................................... 12 Thermal Characteristics ............................................................ 12 ESD Caution ................................................................................ 12 Pin Configurations and Function Descriptions ......................... 13 Typical Performance Characteristics ........................................... 19 AD9648-125 ................................................................................ 20 AD9648-105 ................................................................................ 22 Equivalent Circuits ......................................................................... 24 Theory of Operation ...................................................................... 25 ADC Architecture ...................................................................... 25 Analog Input Considerations.................................................... 25 Voltage Reference ....................................................................... 27 Clock Input Considerations ...................................................... 28 Channel/Chip Synchronization ................................................ 30 Power Dissipation and Standby Mode .................................... 30 Digital Outputs ........................................................................... 31 Timing ......................................................................................... 31 Built-In Self-Test (BIST) and Output Test .................................. 32 Built-In Self-Test (BIST) ............................................................ 32 Output Test Modes ..................................................................... 32 Serial Port Interface (SPI) .............................................................. 33 Configuration Using the SPI ..................................................... 33 Hardware Interface..................................................................... 34 Configuration Without the SPI ................................................ 34 SPI Accessible Features .............................................................. 34 Memory Map .................................................................................. 35 Reading the Memory Map Register Table............................... 35 Memory Map Register Table ..................................................... 36 Memory Map Register Descriptions ........................................ 39 Applications Information .............................................................. 41 Design Guidelines ...................................................................... 41 Outline Dimensions ....................................................................... 42 Ordering Guide .......................................................................... 42
REVISION HISTORY
7/11Revision 0: Initial Version
Rev. 0 | Page 2 of 44
AD9648 GENERAL DESCRIPTION

The AD9648 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and onchip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Output logic levels of 1.8 V CMOS or LVDS are supported. Output data can also be multiplexed onto a single output bus. The AD9648 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (40C to +85C). This product is protected by a U.S. patent.
AD9648 SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1.
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) 1 Integral Nonlinearity (INL)1 MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation Error at 1.0 mA INPUT REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance2 Input Resistance (Differential) Input Common-Mode Voltage Input Common-Mode Range POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD1 IDRVDD (1.8 V CMOS)1 IDRVDD(1.8 V LVDS)1 Temp Full Full Full Full Full 25C Full 25C Full Full Full Full Full Full 25C Full Full Full Full Full 0.98 Min 14 AD9648-105 Typ Max Min 14 AD9648-125 Typ Max Unit Bits
0.8 4.20 0.5 2.3
Guaranteed 0.3 1.3 0.5
+0.2 +4.2 +1.2 +2.3
0.8 5.1 0.5 2.3
Guaranteed 0.3 1.3 0.5
+0.2 +5.1 +1.2 +2.3
1.0 0.01 0.5 2 50 1.00 2 0.98 2 5 7.5 0.9 0.5 1.3 0.5 1.02 0.98
0.58
1.0 0.01 0.5 2 50 1.00 2 0.98 2 5 7.5 0.9 1.3 1.02 0.58 4.0
% FSR % FSR LSB LSB LSB LSB % FSR % FSR ppm/C ppm/C V mV LSB rms V p-p pF k V V
4.0
Full Full Full Full Full
1.7 1.7
1.8 1.8 81 19.2 63.5
1.9 1.9 86
1.7 1.7
1.8 1.8 95 22.5 65.0
1.9 1.9 100
V V mA mA mA
AD9648
Parameter POWER CONSUMPTION DC Input Sine Wave Input (DRVDD = 1.8 V CMOS Output Mode) Sine Wave Input (DRVDD = 1.8 V LVDS Output Mode) Standby Power3 Power-Down Power
1 2 3
Temp Full Full Full Full Full
Min
AD9648-105 Typ 135.4 172.3 180.4 108 2.0
Max
Min
AD9648-125 Typ 155.5 202.5 211.5 120 2.0
Max
Unit mW mW mW mW mW
181.3 189.4
211.5 220.5
Measure with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Input capacitance refers to the effective capacitance between one differential input pin and AGND. Standby power is measured with a dc input and with the CLK pins active (1.8 V CMOS mode).
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 2.
Parameter1 SIGNAL-TO-NOISE-RATIO (SNR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz Temp 25C 25C 25C Full 25C 25C 25C 25C 25C Full 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C Full 25C 25C Min AD9648-105 Typ Max 75.4 75.2 74.8 73.8 73.8 71.0 74.3 74.0 73.4 73.0 72.8 69.6 12.0 12.0 11.8 11.8 11.3 98 90 93 86 92 81 90 84 72.8 72.8 70.3 11.9 11.9 11.8 11.8 11.4 96 90 91 82 73.0 73.9 71.5 73.9 73.4 73.3 Min AD9648-125 Typ Max 75.0 74.7 74.5 Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc
AD9648
Parameter1 SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz TWO-TONE SFDR fIN = 29 MHz (7 dBFS ), 32 MHz (7 dBFS ) CROSSTALK2 ANALOG INPUT BANDWIDTH
1 2
Temp 25C 25C 25C Full 25C 25C 25C 25C 25C Full 25C 25C 25C Full 25C
Min
AD9648-105 Typ Max 98 90 93
Min
AD9648-125 Typ Max 96 90 91
Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB MHz
86 92 81 98 96 96 91 92 90 84 95 650
82 90 84 97 97 97 90 92 90 84 95 650
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Crosstalk is measured at 100 MHz with 1.0 dBFS on one channel and no input on the alternate channel.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 3.
Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Current Low Level Input Current Input Capacitance Input Resistance LOGIC INPUT (CSB)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance Temp Min AD9628-105/125 Typ Max CMOS/LVDS/LVPECL 0.9 0.3 AGND - 0.3 0.9 10 10 8 1.22 0 10 40 26 2 4 10 3.6 AVDD + 0.2 1.4 +10 +10 12 DRVDD + 0.2 0.6 +10 132 Unit
Full Full Full Full Full Full Full Full Full Full Full Full Full Full
V V p-p V V A A pF k V V A A k pF
AD9648
Parameter LOGIC INPUT (SCLK/DFS/SYNC)2 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 1.8 V) Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT/OUTPUT (SDIO/DCS)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (OEB, PDWN)2 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 1.8 V) Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS CMOS ModeDRVDD = 1.8 V High Level Output Voltage IOH = 50 A IOH = 0.5 mA Low Level Output Voltage IOL = 1.6 mA IOL = 50 A LVDS ModeDRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Output Offset Voltage (VOS), ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode
1 2
Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
Min 1.22 0 92 10
AD9628-105/125 Typ Max DRVDD + 0.2 0.6 135 +10 26 2
Unit V V A A k pF V V A A k pF V V A A k pF
1.22 0 10 38 26 5 1.22 0 90 10 26 5
DRVDD + 0.2 0.6 +10 128
DRVDD + 0.2 0.6 134 +10
Full Full Full Full Full Full Full Full
1.79 1.75 0.2 0.05 290 1.15 160 1.15 345 1.25 200 1.25 400 1.35 230 1.35
V V V V mV V mV V
Pull up. Pull down.
AD9648
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 4.
Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate1 DCS Enabled DCS Disabled CLK PeriodDivide-by-1 Mode (tCLK) CLK Pulse Width High (tCH) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) DATA OUTPUT PARAMETERS CMOS Mode (DRVDD = 1.8 V) Data Propagation Delay (tPD) DCO Propagation Delay (tDCO)2 DCO to Data Skew (tSKEW) LVDS Mode (DRVDD = 1.8 V) Data Propagation Delay (tPD) DCO Propagation Delay (tDCO)2 DCO to Data Skew (tSKEW) CMOS Mode Pipeline Delay (Latency) LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Wake-Up Time (Power Down)3 Wake-Up Time (Standby) Out-of-Range Recovery Time
1 2 3
Temp Full Full Full Full Full Full Full
Min
AD9648-105 Typ Max 1000
Min
AD9648-125 Typ Max 1000
Unit MHz MSPS MSPS ns ns ns ps rms
20 10 9.52 4.76 1.0 0.07
105 105
20 10 8 4 1.0 0.07
125 125
Full Full Full Full Full Full Full Full Full Full Full
1.8 2.0 1.2
2.9 3.1
0.1
4.4 4.4 +1.0
1.8 2.0 1.2
2.9 3.1
0.1
4.4 4.4 +1.0
ns ns ns ns ns ns Cycles Cycles s ns Cycles
2.4
2.4
2.4
2.4
0.20
+0.03 16 16/16.5 350 250 2
+0.25
0.20
+0.03 16 16/16.5 350 250 2
+0.25
Conversion rate is the clock rate after the divider. Additional DCO delay can be added by writing to Bits[2:0] in SPI Register 0x17 (see Table 18). Wake-up time is defined as the time required to return to normal operation from power-down mode.
AD9648
TIMING SPECIFICATIONS
Table 5.
Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Description Limit Unit
SYNC to rising edge of CLK+ setup time SYNC to rising edge of CLK+ hold time
0.24 0.40
ns typ ns typ
Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge
2 2 40 2 2 10 10 10 10
ns min ns min ns min ns min ns min ns min ns min ns min ns min
Timing Diagrams
N1 N VIN N+1 N+2
tA
N+3
N+4 N+5
tCH
CLK+ CLK
tCLK
tDCO
DCOA/DCOB
tSKEW
09975-002
CH A/CH B DATA
N 17
N 16
N 15
N 14
N 13
N 12
tPD
Figure 2. CMOS Default Output Mode Data Output Timing
AD9648
N1 N VIN N+1 N+2
tA
N+3
N+4 N+5
tCH
CLK+ CLK
tCLK
tDCO
DCOA/DCOB
tSKEW
CH A DATA CH A CH B CH A CH B CH A N 16 N 15 N 14 N 13 N 12 CH B CH A N 11 N 10 CH B N9 CH A N8
09975-003
tPD
CH B DATA CH B CH A CH B CH A CH B CH A CH B N 16 N 15 N 14 N 13 N 12 N 11 N 10 CH A N9 CH B N8
Figure 3. CMOS Interleaved Output Mode Data Output Timing
N1 N VIN
tA
N+3 N+1
N+4 N+5
N+2
tCH
CLK+ CLK
tCLK
tDCO
DCO+ DCO
tSKEW tPD
CH A N 12 CH B N 12 CH A N 11 CH B N 11 CH A N 10 CH B N 10 CH A N9 CH B N9 CH A N8
D0+ (LSB) PARALLEL INTERLEAVED MODE D0 (LSB) D13+ (MSB) D13 (MSB) D1+/0+ (LSB) CHANNEL MULTIPLEXED MODE CHANNEL A D1/D0 (LSB) D13+/D12+ (MSB) D13/D12 (MSB) D1+/D0+ (LSB) CHANNEL MULTIPLEXED MODE CHANNEL B D1/D0 (LSB) D13+/D12+ (MSB) D13/D12 (MSB)
CH A N 12
CH B N 12
CH A N 11
CH B N 11
CH A N 10
CH B N 10
CH A N9
CH B N9
CH A N8
CH A0 N 12
CH A1 N 12
CH A0 N 11
CH A1 N 11
CH A0 N 10
CH A1 N 10
CH A0 N9
CH A1 N9
CH A0 N8
CH A12 N 12
CH A13 N 12
CH A12 N 11
CH A13 N 11
CH A12 N 10
CH A13 N 10
CH A12 N9
CH A13 N9
CH A12 N8
CH B0 N 12
CH B1 N 12
CH B0 N 11
CH B1 N 11
CH B0 N 10
CH B1 N 10
CH B0 N9
CH B1 N9
CH B0 N8
CH B12 N 12
CH B13 N 12
CH B12 N 11
CH B13 N 11
CH B12 N 10
CH B13 N 10
CH A12 N9
CH A13 N9
CH A12 N8
Figure 4. LVDS Modes for Data Output Timing
09975-004
AD9648
CLK+
tSSYNC
SYNC
tHSYNC
09975-005
Figure 5. SYNC Input Timing Requirements
AD9648 ABSOLUTE MAXIMUM RATINGS

Table 6.
Parameter Electrical1 AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VINA/VINB to AGND CLK+, CLK to AGND SYNC to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB PDWN D0A/D0B through D13A/D13B to AGND DCOA/DCOB to AGND Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient)
1
THERMAL CHARACTERISTICS
Rating 0.3 V to +2.0 V 0.3 V to +2.0 V 0.3 V to AVDD + 0.2 V 0.3 V to AVDD + 0.2 V 0.3 V to AVDD + 0.2 V 0.3 V to AVDD + 0.2 V 0.3 V to AVDD + 0.2 V 0.3 V to DRVDD + 0.2 V 0.3 V to DRVDD + 0.2 V 0.3 V to DRVDD + 0.2 V 0.3 V to DRVDD + 0.2 V 0.3 V to DRVDD + 0.2 V 0.3 V to DRVDD + 0.2 V 0.3 V to DRVDD + 0.2 V 40C to +85C 150C 65C to +150C
The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB increases the reliability of the solder joints and maximizes the thermal capability of the package. Table 7. Thermal Resistance
Package Type 64-Lead LFCSP 9 mm 9 mm (CP-64-4)
1 2 3
Airflow Velocity (m/sec) 0 1.0 2.5
JA1, 2 22.3 19.5 17.5
JC1, 3 1.4 N/A N/A
JB1, 4 N/A 11.8 N/A
JT1,2 0.1 0.2 0.2
Unit C/W C/W C/W
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air).
Typical JA is specified for a 4-layer PCB with a solid ground plane. As shown Table 7, airflow improves heat dissipation, which reduces JA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces JA.
ESD CAUTION
The inputs and outputs are rated to the supply voltage (AVDD or DRVDD) + 0.2 V but should not exceed 2.1 V.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AD9648 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VINB AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VINA VIN+A AVDD AVDD
CLK+ CLK SYNC NC NC D0B (LSB) D1B D2B D3B DRVDD D4B D5B D6B D7B D8B D9B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
AD9648
PARALLEL CMOS TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PDWN OEB CSB SCLK/DFS SDIO/DCS ORA D13A (MSB) D12A D11A D10A D9A DRVDD D8A D7A D6A D5A
NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
D10B D11B DRVDD D12B D13B (MSB) ORB DCOB DCOA NC NC D0A (LSB) DRVDD D1A D2A D3A D4A
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 6. Parallel CMOS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Parallel CMOS Mode)

Pin No. Mnemonic ADC Power Supplies 10, 19, 28, 37 DRVDD 49, 50, 53, 54, AVDD 59, 60, 63, 64 4, 5, 25, 26 NC 0 AGND, Exposed Pad ADC Analog 51 52 62 61 55 56 58 57 1 2 Digital Input 3 Type Supply Supply Description Digital Output Driver Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). No Connect. Do not connect to these pins. The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin () for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin () for Channel B. Voltage Reference Input/Output. Reference Mode Selection. External Reference Bias Resistor. Common-Mode Level Bias Output for Analog Inputs. ADC Clock InputTrue. ADC Clock InputComplement. Digital Synchronization Pin. Slave mode only.
Ground
VIN+A VINA VIN+B VINB VREF SENSE RBIAS VCM CLK+ CLK SYNC
Input Input Input Input Input/Output Input Input/Output Output Input Input Input
09975-006
AD9648
Pin No. Mnemonic Digital Outputs 27 D0A (LSB) 29 D1A 30 D2A 31 D3A 32 D4A 33 D5A 34 D6A 35 D7A 36 D8A 38 D9A 39 D10A 40 D11A 41 D12A 42 D13A (MSB) 43 ORA 6 D0B (LSB) 7 D1B 8 D2B 9 D3B 11 D4B 12 D5B 13 D6B 14 D7B 15 D8B 16 D9B 17 D10B 18 D11B 20 D12B 21 D13B (MSB) 22 ORB 24 DCOA 23 DCOB SPI Control 45 SCLK/DFS 44 SDIO/DCS 46 CSB ADC Configuration 47 OEB 48 PDWN Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input/Output Input Input Input Description Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A Overrange Output. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B Overrange Output Channel A Data Clock Output. Channel B Data Clock Output. SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select (Active Low). Output Enable Input (Active Low). Pin must be enabled via SPI. Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby.
AD9648
AVDD AVDD VIN+B VINB AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VINA VIN+A AVDD AVDD
CLK+ CLK SYNC NC NC NC NC D0 (LSB) D0+ (LSB) DRVDD D1 D1+ D2 D2+ D3 D3+
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PIN 1 INDICATOR
AD9648
INTERLEAVED PARALLEL LVDS TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PDWN OEB CSB SCLK/DFS SDIO/DCS OR+ OR D13+ (MSB) D13 (MSB) D12+ D12 DRVDD D11+ D11 D10+ D10
D4 D4+ DRVDD D5 D5+ D6 D6+ DCO DCO+ D7 D7+ DRVDD D8 D8+ D9 D9+
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 7. Interleaved Parallel LVDS Pin Configuration (Top View)
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)

Pin No. Mnemonic ADC Power Supplies 10, 19, 28, 37 DRVDD 49, 50, 53, 54, AVDD 59, 60, 63, 64 4, 5, 6, 7 NC 0 AGND, Exposed Pad ADC Analog 51 VIN+A 52 VINA 62 VIN+B 61 VINB 55 VREF 56 SENSE 58 RBIAS 57 VCM 1 CLK+ 2 CLK Digital Input 3 SYNC Digital Outputs 9 D0+ (LSB) 8 D0 (LSB) 12 D1+ 11 D1 Type Supply Supply Description Digital Output Driver Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). No Connect. Do not connect to these pins. The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin () for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin () for Channel B. Voltage Reference Input/Output. Reference Mode Selection. External Reference Bias Resistor. Common-Mode Level Bias Output for Analog Inputs. ADC Clock InputTrue. ADC Clock InputComplement. Digital Synchronization Pin. Slave mode only. Channel A/Channel B LVDS Output Data 0True. Channel A/Channel B LVDS Output Data 0Complement. Channel A/Channel B LVDS Output Data 1True. Channel A/Channel B LVDS Output Data 1Complement.
Ground
Input Input Input Input Input/Output Input Input/Output Output Input Input Input Output Output Output Output
09975-007
AD9648
Pin No. Mnemonic 14 D2+ 13 D2 16 D3+ 15 D3 18 D4+ 17 D4 21 D5+ 20 D5 23 D6+ 22 D6 27 D7+ 26 D7 30 D8+ 29 D8 32 D9+ 31 D9 34 D10+ 33 D10 36 D11+ 35 D11 39 D12+ 38 D12 41 D13+ (MSB) 40 D13 (MSB) 43 OR+ 42 OR 25 DCO+ 24 DCO SPI Control 45 SCLK/DFS 44 SDIO/DCS 46 CSB ADC Configuration 47 OEB 48 PDWN Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input/Output Input Input Input Description Channel A/Channel B LVDS Output Data 2True. Channel A/Channel B LVDS Output Data 2Complement. Channel A/Channel B LVDS Output Data 3True. Channel A/Channel B LVDS Output Data 3Complement. Channel A/Channel B LVDS Output Data 4 True. Channel A/Channel B LVDS Output Data 4Complement. Channel A/Channel B LVDS Output Data 5True. Channel A/Channel B LVDS Output Data 5Complement. Channel A/Channel B LVDS Output Data 6True. Channel A/Channel B LVDS Output Data 6Complement. Channel A/Channel B LVDS Output Data 7True. Channel A/Channel B LVDS Output Data 7Complement. Channel A/Channel B LVDS Output Data 8True. Channel A/Channel B LVDS Output Data 8Complement. Channel A/Channel B LVDS Output Data 9True. Channel A/Channel B LVDS Output Data 9Complement. Channel A/Channel B LVDS Output Data 10True. Channel A/Channel B LVDS Output Data 10Complement. Channel A/Channel B LVDS Output Data 11True. Channel A/Channel B LVDS Output Data 11Complement. Channel A/Channel B LVDS Output Data 12True. Channel A/Channel B LVDS Output Data 12Complement. Channel A/Channel B LVDS Output Data 13True. Channel A/Channel B LVDS Output Data 13Complement. Channel A/Channel B LVDS Overrange OutputTrue. Channel A/Channel B LVDS Overrange OutputComplement. Channel A/Channel B LVDS Data Clock OutputTrue. Channel A/Channel B LVDS Data Clock OutputComplement. SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select (Active Low). Output Enable Input (Active Low). Pin must be enabled via SPI. Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby.
AD9648
AVDD AVDD VIN+B VINB AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VINA VIN+A AVDD AVDD
CLK+ CLK SYNC NC NC NC NC B D1/D0 (LSB) B D1+/D0+ (LSB) DRVDD B D3/D2 B D3+/D2+ B D5/D4 B D5+/D4+ B D7/D6 B D7+/D6+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PIN 1 INDICATOR
AD9648
CHANNEL MULTIPLEXED LVDS TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PDWN OEB CSB SCLK/DFS SDIO/DCS OR+ OR A D13+/D12+ (MSB) A D13/D12 (MSB) A D11+/D10+ A D11/D10 DRVDD A D9+/D8+ A D9/D8 A D7+/D6+ A D7/D6
B D9/D8 B D9+/D8+ DRVDD B D11/D10 B D11+/D10+ B D13/D12 (MSB) B D13+/D12+ (MSB) DCO DCO+ A D1/D0 (LSB) A D1+/D0+ (LSB) DRVDD A D3/D2 A D3+/D2+ A D5/D4 A D5+/D4+
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 8. Channel Multiplexed LVDS Pin Configuration (Top View)
Table 10 Pin Function Descriptions (Channel Multiplexed Parallel LVDS Mode)

Pin No. Mnemonic ADC Power Supplies 10, 19, 28, 37 DRVDD 49, 50, 53, 54, AVDD 59, 60, 63, 64 4, 5, 6, 7 NC 0 AGND, Exposed Pad Type Supply Supply Description Digital Output Driver Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). Do Not Connect. The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin () for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin () for Channel B. Voltage Reference Input/Output. Reference Mode Selection. External Reference Bias Resistor. Common-Mode Level Bias Output for Analog Inputs. ADC Clock InputTrue. ADC Clock InputComplement. Digital Synchronization Pin. Slave mode only.
Ground
ADC Analog 51 52 62 61 55 56 58 57 1 2 Digital Input 3
VIN+A VINA VIN+B VINB VREF SENSE RBIAS VCM CLK+ CLK SYNC
Input Input Input Input Input/Output Input Input/Output Output Input Input Input
09975-008
AD9648
Pin No. Mnemonic Digital Outputs 8 B D1/D0 (LSB) 9 B D1+/D0+ (LSB) 11 B D3/D2 12 B D3+/D2+ 13 B D5/D4 14 B D5+/D4+ 15 B D7/D6 16 B D7+/D6+ 17 B D9/D8 18 B D9+/D8+ 20 B D11/D10 21 B D11+/D10+ 22 B D13/D12 (MSB) 23 B D13+/D12+ (MSB) 26 A D1/D0 (LSB) 27 A D1+/D0+ (LSB) 29 A D3/D2 30 A D3+/D2+ 32 A D5+/D4+ 31 A D5/D4 34 A D7+/D6+ 33 A D7/D6 36 A D9+/D8+ 35 A D9/D8 39 A D11+/D10+ 38 A D11/D10 41 A D13+/D12+ (MSB) 40 A D13/D12 (MSB) 43 OR+ 42 OR 25 DCO+ 24 DCO SPI Control 45 SCLK/DFS 44 SDIO/DCS 46 CSB ADC Configuration 47 OEB 48 PDWN Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input/Output Input Input Input Description Channel B LVDS Output Data 1/Data 0Complement. Channel B LVDS Output Data 1/Data 0True. Channel B LVDS Output Data 3/Data 2Complement. Channel B LVDS Output Data 3/Data 2True. Channel B LVDS Output Data 5/Data 4Complement. Channel B LVDS Output Data 5/Data 4True. Channel B LVDS Output Data 7/Data 6Complement. Channel B LVDS Output Data 7/Data 6True. Channel B LVDS Output Data 9/Data 8Complement. Channel B LVDS Output Data 9/Data 8True. Channel B LVDS Output Data 11/Data 10Complement. Channel B LVDS Output Data 11/Data 10True. Channel B LVDS Output Data 13/Data 12Complement. Channel B LVDS Output Data 13/Data 12True. Channel A LVDS Output Data 1/Data 0Complement. Channel A LVDS Output Data 1/Data 0True. Channel A LVDS Output Data 3/Data 2Complement. Channel A LVDS Output Data 3/Data 2True. Channel A LVDS Output Data 5/Data 4Complement. Channel A LVDS Output Data 5/Data 4True. Channel A LVDS Output Data 7/Data 6Complement. Channel A LVDS Output Data 7/Data 6True. Channel A LVDS Output Data 9/Data 8Complement. Channel A LVDS Output Data 9/Data 8True. Channel A LVDS Output Data 11/Data 10Complement. Channel A LVDS Output Data 11/Data 10True. Channel A LVDS Output Data 13/Data 12Complement. Channel A LVDS Output Data 13/Data 12True. Channel A/Channel B LVDS Overrange OutputTrue. Channel A/Channel B LVDS Overrange OutputComplement. Channel A/Channel B LVDS Data Clock OutputTrue. Channel A/Channel B LVDS Data Clock OutputComplement. SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select (Active Low). Output Enable Input (Active Low). Pin must be enabled via SPI. Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby.
AD9648 TYPICAL PERFORMANCE CHARACTERISTICS

AD9648-125 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.
0
20
125MSPS 9.7MHz AT 1dBFS SNR = 74.4dB (75.4dBFS) SFDR = 95.4dBc
20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
40
40
60
60
80
80
100
100
09975-014
10
20
30
40
50
60
10
20
30
40
50
60
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Single-Tone FFT with fIN = 9.7 MHz

0

0 125MSPS 200.5MHz AT 1dBFS SNR = 70.9dB (71.9dBFS) SFDR = 83.6dBc
125MSPS 30.5MHz AT 1dBFS SNR = 74.0dB (75.0dBFS) 20 SFDR = 86.0dBc
20
AMPLITUDE (dBFS)
40
AMPLITUDE (dBFS)
40
60
60
80
80
100
100
09975-022
120
10
20
30
40
50
60
FREQUENCY (MHz)
FREQUENCY (MHz)

0
AMPLITUDE (dBFS)
40
60
80
100
10
20
30
40
50
60
FREQUENCY (MHz)

09975-023
120
09975-025
10
20
30
40
50
60
120
09975-024
120
120
AD9648
AD9648-125
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.
0 15
10
SFDR (dBc)
SFDR/IMD3 (dBc/dBFS)
30
30
AMPLITUDE (Hz)
45 60 75
2F1 F2
IMD3(dBc)
50
90 105 120 135
2F2 F1 2F1 + F2
70
90
SFDR (dBFS) IMD3 (dBFS)

80 70 40 30 60 50 INPUT AMPLITUDE (dBFS) 20 10
09975-065
09975-021
6M
12M 18M 24M 30M 36M 42M 48M 54M 60M FREQUENCY (MHz)
Figure 14. Two-Tone FFT with fIN1 = 29 MHz and fIN2 = 32 MHz
09975-067
110 90
Figure 17. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 29 MHz and fIN2 = 32 MHz
120
100 95
SFDR (dBc)
100
SFDR (dBc)
90
SNR/SFDR (dBFS/dBc)
85 80 75 70 65 60 55
09975-069
SNR/SFDR (dBFS/dBc)
80
SNR (dBFS)
SNR (dBFS)
60
40
20
50
50
100
150
200
250
15
25
35
ANALOG INPUT FREQUENCY (MHz)
45 55 65 75 85 SAMPLE RATE (MSPS)
95
105 115 125
Figure 15. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale
120 SFDRFS 100
SNR/SFDR (dBFS/dBc)
100 120
Figure 18. SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz
SFDR (dBc)
SNR/SFDR (dBFS)
80
SNRFS
80
SNR (dBFS)
60 SFDR 40 SNR 20
60
40
20
80
70
60
50
40
30
20
10
09975-068
0 90
15
25
35
45
INPUT AMPLITUDE (dBFS)
55 65 75 85 SAMPLE RATE (MSPS)
95
105 115 125
Figure 16. SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
09975-020
AD9648
2 1.5 1
2.0 1.5 1.0
DNL ERROR (LSB)
INL ERROR (LSB)
0.5 0 0.5 1.0 1.5 2.0
0.5 0 -0.5 1.0 1.5 2.0
09975-019
2000
4000
6000
8000
10000 12000 14000 16000
2000
4000
6000
8000
10000 12000 14000 16000
OUTPUT CODE
OUTPUT CODE
Figure 20. DNL Error with fIN = 9.7 MHz

450,000 400,000 350,000
Figure 22. INL Error with fIN = 9.7 MHz
NUMBER OF HITS
300,000 250,000 200,000 150,000 100,000 50,000 0
N+1
N+2
N+3
N+4
N+5
N+6
N6
N5
N4
N3
N2
N1
OUTPUT CODE
Figure 21. Shorted Input Histogram
09975-074
09975-018
AD9648
AD9648-105
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.
0
20
20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
40
40
60
60
80
80
100
100
09975-014
10
20
30
40
50
10
20
30
40
50
FREQUENCY (MHz)
FREQUENCY (MHz)

0

0 105MSPS 200.5MHz AT 1dBFS SNR = 69.5dB (70.5dBFS) SFDR = 82.6dBc
20
20
AMPLITUDE (dBFS)
40
AMPLITUDE (dBFS)
40
60
60
80
80
100
100
0 10 20 30 40 50
09975-015
120
FREQUENCY (MHz)
10
20
30
40
50
FREQUENCY (MHz)

0
AMPLITUDE (dBFS)
40
60
80
100
10
20
30
40
50
FREQUENCY (MHz)
09975-013
120
09975-017
120
09975-016
120
120
AD9648
100 95
120
SFDR (dBc)
90
SFDRFS
100
SNR/SFDR (dBFS/dBc)
85 80 75 70 65 60
SNR/SFDR (dBFS/dBc)
80
SNRFS
SNR (dBFS)
60
SFDR
40
SNR
20
55
09975-075
50
100
150
200
250
80
70
60
50
40
30
20
10
ANALOG INPUT FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 28. SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale
120
Figure 31. SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
120
100
SFDR (dBc)
100
SFDR (dBc)
SNR/SFDR (dBFS/dBc)
80
SNR (dBFS)
SNR/SFDR (dBFS/dBc)
80
SNR (dBFS)
60
60
40
40
20
20
09975-012
15
25
35
45
55
65
75
85
95
105
15
25
35
45
55
65
75
85
95
105
SAMPLE RATE (MSPS)
SAMPLE RATE (MSPS)
2.0 1.5 1.0
2.0 1.5 1.0
DNL ERROR (LSB)
INL ERROR (LSB)
0.5 0 0.5 1.0 1.5 2.0
0.5 0 0.5 1.0 1.5 2.0
09975-010
2000
4000
6000
8000
10000 12000 14000 16000
2000
4000
6000
8000
10000 12000 14000 16000
OUTPUT CODE
OUTPUT CODE
Figure 30. DNL Error with fIN = 9.7 MHz
Figure 33. INL Error with fIN = 9.7 MHz
09975-009
09975-011
09975-077
50
0 90
AD9648 EQUIVALENT CIRCUITS

DRVDD
AVDD
VINx
SCLK/DFS, SYNC, OEB, AND PDWN

09975-039
350 30k
09975-045
Figure 34. Equivalent Analog Input Circuit
Figure 38. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit
AVDD
CLK+
15k 0.9V 15k CLK 5

09975-040
SENSE
375
Figure 35. Equivalent Clock Input Circuit
Figure 39. Equivalent SENSE Circuit
DRVDD
DRVDD AVDD 350 30k
PAD
CSB
09975-043
09975-047
Figure 36. Equivalent Digital Output Circuit

AVDD
Figure 40. Equivalent CSB Input Circuit
DRVDD 30k SDIO/DCS 350 30k

09975-042
AVDD
VREF
09975-048
375 7.5k
Figure 37. Equivalent SDIO/DCS Input Circuit
Figure 41. Equivalent VREF Circuit
09975-044
AD9648 THEORY OF OPERATION

The AD9648 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fS/2 frequency segment from dc to 200 MHz, using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 300 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion. In nondiversity applications, the AD9648 can be used as a baseband or direct downconversion receiver, where one ADC is used for I input data and the other is used for Q input data. Synchronization capability is provided to allow synchronized timing between multiple channels or multiple devices. Programming and control of the AD9648 is accomplished using a 3-bit SPI-compatible serial interface.
ANALOG INPUT CONSIDERATIONS

The analog input to the AD9648 is a differential switchedcapacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance.
CPAR
VIN+x H
CSAMPLE
S S S S
CSAMPLE
VINx
ADC ARCHITECTURE
The AD9648 architecture consists of a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the CMOS/LVDS output buffers. The output buffers are powered from a separate (DRVDD) supply, allowing digital output noise to be separated from the analog core. During power-down, the output buffers go into a high impedance state.
CPAR
H
H
09975-049
Figure 42. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between sample-and-hold mode (see Figure 42). When the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, therefore, achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article Transformer-Coupled Front-End for Wideband A/D Converters (Volume 39, April 2005) for more information. In general, the precise values depend on the application.
AD9648
Input Common Mode
The analog inputs of the AD9648 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide a dc bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 43. An on-board, common-mode voltage reference is included in the design and is available from the VCM pin. The VCM pin must be decoupled to ground by a 0.1 F capacitor, as described in the Applications Information section.
100 SFDR (dBc) 90 80 SNR (dBFS)
R 2V p-p 49.9 R VINx 0.1F C
driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.
200 VIN 76.8 90 33 VINx AVDD
ADA4938
0.1F 120 200
10pF
ADC
VIN+x VCM
09975-050
09975-051
33
Figure 44. Differential Input Configuration Using the ADA4938-2
For baseband applications below ~10 MHz where SNR is a key parameter, differential transformer-coupling is the recommended input configuration. An example is shown in Figure 45. To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer.
VIN+x
SNR/SFDR (dBFS/dBc)
70 60 50 40 30 20 10
09975-072
ADC
VCM
Figure 45. Differential Transformer-Coupled Configuration
0 0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion. At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9648. For applications above ~10 MHz where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 46). An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver. An example is shown in Figure 47. See the AD8352 data sheet for more information.
R 25 VIN+x C
INPUT COMMON-MODE VOLTAGE (V)
Figure 43. SNR/SFDR vs. Input Common-Mode Voltage, fIN = 70 MHz, fS = 125 MSPS
Differential Input Configurations

Optimum performance is achieved while driving the AD9648 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9648 (see Figure 44), and the
0.1F 2V p-p PA S S P 0.1F 25 0.1F
0.1F R VINx
ADC
VCM
09975-053
Figure 46. Differential Double Balun Input Configuration

VCC 0.1F ANALOG INPUT 0 16 1 2 CD RD RG 3 4 ANALOG INPUT 5 0.1F 0 14 0.1F 0.1F 8, 13 11 0.1F 0.1F R 200 VIN+x C 0.1F 200 R VINx VCM
09975-054
AD8352
10
ADC
Figure 47. Differential Input Configuration Using the AD8352

AD9648
In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 11 displays the suggested values to set the RC network. However, these values are dependent on the input signal and should be used only as a starting guide. Table 11. Example RC Network
Frequency Range (MHz) 0 to 70 70 to 200 R Series ( Each) 33 125 C Differential (pF) 22 Open
1.0F
the reference amplifier switch is connected to the internal resistor divider (see Figure 49), setting VREF to 1.0 V.
VIN+A/VIN+B VINA/VINB
ADC CORE
VREF 0.1F SELECT LOGIC SENSE 0.5V

09975-055
Single-Ended Input Configuration

A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input commonmode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 48 shows a typical single-ended input configuration.
10F AVDD 1k 1V p-p 49.9 0.1F 1k C R
09975-052
ADC
Figure 49. Internal Reference Configuration
VIN+x
AVDD 1k 10F 0.1F 1k
ADC
VINx
If the internal reference of the AD9648 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 50 shows how the internal reference voltage is affected by loading.
0
REFERENCE VOLTAGE ERROR (%)
0.5
Figure 48. Single-Ended Input Configuration
VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the AD9648. The VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the best practices PCB layout of the reference.
1.0 INTERNAL VREF = 1.00V 1.5
2.0
2.5
Internal Reference Connection

A comparator within the AD9648 detects the potential at the SENSE pin and configures the reference into two possible modes, which are summarized in Table 12. If SENSE is grounded,
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (mA)
09975-078
3.0
Figure 50. VREF Accuracy vs. Load Current
Table 12. Reference Configuration Summary

Selected Mode Fixed Internal Reference Fixed External Reference SENSE Voltage (V) AGND to 0.2 AVDD Resulting VREF (V) 1.0 internal 1.0 applied to external VREF pin Resulting Differential Span (V p-p) 2.0 2.0
AD9648
External Reference Operation
The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 51 shows the typical drift characteristics of the internal reference in 1.0 V mode.
4 3 2 VREF ERROR (mV)
Clock Input Options

The AD9648 has a very flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 53 and Figure 54 show two preferred methods for clocking the AD9648 (at clock rates up to 1 GHz prior to internal CLK divider). A low jitter clock source is converted from a singleended signal to a differential signal using either an RF transformer or an RF balun. The RF balun configuration is recommended for clock frequencies between 125 MHz and 1 GHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9648 to approximately 0.8 V p-p differential.
VREF ERROR (mV)
1 0 1 2 3 4 5
09975-079
6 40
20
20 40 TEMPERATURE (C)
60
80
Figure 51. Typical VREF Drift
This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9648 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance.
Mini-Circuits ADT1-1WT, 1:1 Z 0.1F CLOCK INPUT 50 100 0.1F 0.1F SCHOTTKY DIODES: HSMS2822 XFMR 0.1F CLK+
CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9648 sample clock inputs, CLK+ and CLK, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK pins via a transformer or capacitors. These pins are biased internally (see Figure 52) and require no external bias.
AVDD
Figure 53. Transformer-Coupled Differential Clock (Up to 200 MHz)
1nF CLOCK INPUT 50
0.1F CLK+ 0.1F
ADC
CLK SCHOTTKY DIODES: HSMS2822
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1nF
0.9V CLK+ CLK
Figure 54. Balun-Coupled Differential Clock (Up to 1 GHz)
2pF
2pF
09975-058
Figure 52. Equivalent Clock Input Circuit
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When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7.5 k load (see Figure 41). The internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V.
ADC
CLK
AD9648
If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 55. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance.
0.1F CLOCK INPUT 0.1F CLOCK INPUT 50k 50k AD951x PECL DRIVER 240 240 100 0.1F CLK
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Input Clock Divider

The AD9648 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. The AD9648 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling.
0.1F CLK+
ADC
Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9648 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9648. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on, as shown in Figure 58. Jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 20 MHz, nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal.
80 SNR (DCS ON)
Figure 55. Differential PECL Sample Clock (Up to 1 GHz)
A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 56. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance.
0.1F CLOCK INPUT 0.1F CLOCK INPUT 50k 50k AD951x LVDS DRIVER 100 0.1F CLK
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0.1F CLK+
ADC
Figure 56. Differential LVDS Sample Clock (Up to 1 GHz)
In some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass the CLK pin to ground with a 0.1 F capacitor (see Figure 57).
VCC 0.1F CLOCK INPUT 501 1k 1k AD951x CMOS DRIVER OPTIONAL 0.1F 100 CLK+
ADC
CLK
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75 70 SNR (DCS OFF) 65 60 55 50 45
0.1F
150 RESISTOR IS OPTIONAL.
Figure 57. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
SNR (dBFS)
40
45
50
55
60
65
POSITIVE DUTY CYCLE (%)
Figure 58. SNR vs. DCS On/Off
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40 35
AD9648
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fINPUT) due to jitter (tJRMS) can be calculated by SNRHF = 10 log[(2 fINPUT tJRMS)2 + 10 ( SNRLF /10) ] In the previous equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications are particularly sensitive to jitter, as illustrated in Figure 59.
80 75 0.05ps
primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current (IDRVDD) can be calculated as IDRVDD = VDRVDD CLOAD fCLK N where N is the number of output bits (30, in the case of the AD9648). This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency of fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal. Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 60 was taken in CMOS mode using the same operating conditions as those used for the Power Supplies and Power Consumption specifications in Table 1, with a 5 pF load on each output driver.
100
70 0.2ps
SNR (dBFS)
65
60 55 50 3.0ps 1 10 100
0.5ps
220 200 180

IAVDD
1.0ps 1.5ps
SUPPLY CURRENT (A)
90 80 70 60
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45 FREQUENCY (MHz)
1k
140
50
TOTAL POWER
40 30 20
120 100 80
Figure 59. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9648. To avoid modulating the clock signal with digital noise, keep power supplies for clock drivers separate from the ADC output driver supplies. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. See the AN-501 Application Note and the AN-756 Application Note, available on www.analog.com for more information. The AD9648 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The SYNC input is internally synchronized to the sample clock; however, to ensure there is no timing uncertainty between multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in Table 5. Drive the SYNC input using a single-ended CMOS-type signal.
IDRVDD
10 0
60
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25
45
65
85
105
40 125
ENCODE RATE (MSPS)
Figure 60. AD9648-125 Power and Current vs. Clock Rate (1.8 V CMOS Output Mode)
90 80 70
200 180 160
SUPPLY CURRENT (A)
CHANNEL/CHIP SYNCHRONIZATION
60
IAVDD
50
120
40 30 20 10 0
TOTAL POWER
100 80
IDRVDD
60 40
25
45
65
85
105
POWER DISSIPATION AND STANDBY MODE

As shown in Figure 60, the analog core power dissipated by the AD9648 is proportional to its sample rate. The digital power dissipation of the CMOS outputs are determined
ENCODE RATE (Msps)
Figure 61. AD9648-105 Power and Current vs. Clock Rate (1.8 V CMOS Output Mode)
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POWER (mW)
140
POWER (mW)
2.0ps 2.5ps
160
AD9648
The AD9648 is placed in power-down mode either by the SPI port or by asserting the PDWN pin high. In this state, the ADC typically dissipates less than 2 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9648 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map section for more details. As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. Table 13. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin AGND DRVDD SCLK/DFS Offset binary (default) Twos complement SDIO/DCS DCS disabled DCS enabled (default)
Digital Output Enable Function (OEB)

The AD9648 has a flexible three-state ability for the digital output pins. The three-state mode is enabled through the SPI interface and can subsequently be controlled using the OEB pin or through the SPI. Once enabled via SPI (Bit 7) in Register 0x101, and the OEB pin is low, the output data drivers and DCOs are enabled. If the OEB pin is high, the output data drivers and DCOs are placed in a high impedance state. This OEB function is not intended for rapid access to the data bus. Note that OEB is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. When using the SPI interface, the data outputs and DCO of each channel can be independently three-stated by using the output disable bit (Bit 4) in Register 0x14.
DIGITAL OUTPUTS
The AD9648 output drivers can be configured to interface with either 1.8 V CMOS or 1.8 V LVDS logic families. The default output mode is CMOS, with each channel output on separate busses as shown in Figure 2. In CMOS output mode, the CMOS output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies and may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. The CMOS output can also be configured for interleaved CMOS output mode via the SPI port. In interleaved CMOS mode, the data for both channels is output onto a single output bus to reduce the total number of traces required. The timing diagram for interleaved CMOS output mode is shown in Figure 3. The interleaved CMOS output mode is enabled globally onto both output channels via Bit 5 in Register 0x14. The unused channel output can be disabled by selecting the appropriate Device Index (Bit 1 or Bit 0) in Register 0x05, then writing a 1 to local (channel specific) output port disable bit in Register 0x14. The output data format can be selected to be either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 13). Table 14. Output Data Format
Input (V) VIN+ VIN VIN+ VIN VIN+ VIN VIN+ VIN VIN+ VIN Condition (V) < VREF 0.5 LSB = VREF =0 = +VREF 1.0 LSB > +VREF 0.5 LSB
TIMING
The AD9648 provides latched data with a pipeline delay of 16 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9648. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9648 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)

The AD9648 provides two data clock output (DCO) signals intended for capturing the data in an external register. In CMOS output mode, the data outputs are valid on the rising edge of DCO, unless the DCO clock polarity has been changed via the SPI. In LVDS output mode, the DCO and data output switching edges are closely aligned. Additional delay can be added to the DCO output using SPI Register 0x17 to increase the data setup time. In this case, the Channel A output data is valid on the rising edge of DCO, and the Channel B output data is valid on the falling edge of DCO. See Figure 2, Figure 3, and Figure 4 for a graphical timing description of the output modes.
Offset Binary Output Mode 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1111
Twos Complement Mode 10 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1111
OR 1 0 0 0 1
AD9648 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

The AD9648 includes a built-in test feature designed to enable verification of the integrity of each channel, as well as to facilitate board level debugging. A built-in self-test (BIST) feature that verifies the integrity of the digital datapath of the AD9648 is included. Various output test options are also provided to place predictable values on the outputs of the AD9648.
OUTPUT TEST MODES

The output test options are described in Table 18 at Address 0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
BUILT-IN SELF-TEST (BIST)

The BIST is a thorough test of the digital portion of the selected AD9648 signal path. Perform the BIST test after a reset to ensure the part is in a known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output. At the datapath output, CRC logic calculates a signature from the data. The BIST sequence runs for 512 cycles and then stops. Once completed, the BIST compares the signature results with a predetermined value. If the signatures match, the BIST sets Bit 0 of Register 0x24, signifying the test passed. If the BIST test fails, Bit 0 of Register 0x24 is cleared. The outputs are connected during this test, so the PN sequence can be observed as it runs. Writing the value 0x05 to Register 0x0E runs the BIST. This enables Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence generator, Bit 2 (initialize BIST sequence) of Register 0x0E. At the completion of the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN sequence can be continued from its last value by writing a 0 in Bit 2 of Register 0x0E. However, if the PN sequence is not reset, the signature calculation does not equal the predetermined value at the end of the test. At that point, the user needs to rely on verifying the output data.
AD9648 SERIAL PORT INTERFACE (SPI)

The AD9648 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 62 and Table 5. Other modes involving the CSB are available. The CSB can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. All data is composed of 8-bit words. Data can be sent in MSBfirst mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK/DFS pin, the SDIO/DCS pin, and the CSB pin (see Table 15). The SCLK/DFS (a serial clock) is used to synchronize the read and write data presented from and to the ADC. The SDIO/DCS (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB (chip select bar) is an active low control that enables or disables the read and write cycles. Table 15. Serial Port Interface Pins
Pin SCLK SDIO Function Serial clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles.
CSB
tDS tS
CSB
tHIGH tDH tLOW
tCLK
tH
SCLK DONT CARE
DONT CARE
SDIO DONT CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DONT CARE
Figure 62. Serial Port Interface Timing Diagram
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AD9648
HARDWARE INTERFACE
The pins described in Table 15 comprise the physical interface between the user programming device and the serial port of the AD9648. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9648 to prevent these signals from transitioning at the converter inputs during critical sampling periods. Some pins serve a dual function when the SPI interface is not being used. When the pins are strapped to DRVDD or ground during device power-on, they are associated with a specific function. Table 16 describes the strappable functions supported on the AD9648. When the device is in SPI mode, the PDWN and OEB Pins (if enabled) remain active. For SPI control of output enable and power-down, the OEB and PDWN pins should be set to their default states. Table 16. Mode Selection
Pin SDIO/DCS SCLK/DFS OEB PDWN External Voltage DRVDD (default) AGND DRVDD AGND (default) DRVDD AGND (default) DRVDD AGND (default) Configuration Duty cycle stabilizer enabled Duty cycle stabilizer disabled Twos complement enabled Offset binary enabled Outputs in high impedance Outputs enabled Chip in power-down or standby Normal operation
SPI ACCESSIBLE FEATURES

Table 17 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9648 part-specific features are described in detail following Table 18, the external memory map register table. Table 17. Features Accessible Using the SPI
Feature Name Mode Clock Offset Test I/O Output Mode Output Phase Output Delay Description Allows the user to set either power-down mode or standby mode Allows the user to access the DCS, set the clock divider, set the clock divider phase, and enable the sync Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set the output mode including LVDS Allows the user to set the output clock polarity Allows the user to vary the DCO delay
CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, and the PDWN pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, and power-down feature control. In this mode, the CSB chip select bar should be connected to AVDD, which disables the serial port interface.
AD9648 MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel index and transfer registers (Address 0x05 and Address 0xFF) and the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x102). The memory map register table (see Table 18) lists the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x05, the device index register, has a hexadecimal default value of 0x03. This means that in Address 0x05 Bits[7:2] = 0, and Bits[1:0] = 1. This setting is a default channel index setting. The default value results in both ADC channels receiving the next write command. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining registers, are documented in the Memory Map Register Description section. is open (for example, Address 0x13), this address location should not be written to.
Default Values
After the AD9648 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 18.
Logic Levels
An explanation of logic level terminology follows: Bit is set is synonymous with bit is set to Logic 1 or writing Logic 1 for the bit. Clear a bit is synonymous with bit is set to Logic 0 or writing Logic 0 for the bit.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor thresholds, can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 18 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 18 affect the entire part or the channel features for which independent settings are not allowed between channels.
Open Locations
All address and bit locations that are not included in Table 18 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x05). If the entire address location
AD9648
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 18 are not currently supported for this device. Table 18. Memory Map Registers
Addr Register Bit 7 (Hex) Name (MSB) Chip Configuration Registers 0x00 SPI port Open config (global) Bit 6 LSB first Bit 5 Soft reset Bit 4 1 Bit 3 1 Bit 2 Soft reset Bit 1 LSB first Bit 0 (LSB) Open Default Value (Hex) 0x18 Comments The nibbles are mirrored so LSB-first mode or MSB-first mode registers correctly, regardless of shift mode Unique chip ID used to differentiate devices; read only Unique speed grade ID used to differentiate devices; read only Bits are set to determine which device on the chip receives the next write command; applies to local registers only Synchronously transfers data from the master shift register to the slave Determines various generic modes of chip operation
0x01
Chip ID (global)
8-bit chip ID[7:0] AD9648 = 0x88
Read only
0x02
Chip grade (global)
Open
Speed grade ID 100 = 105 MSPS 101 = 125 MSPS
Open
Read only
Channel Index and Transfer Registers 0x05 Device Open Open index (global)
Open
Open
Open
Open
Data Channel B
Data Channel A
0x03
0xFF
Transfer (global)
Open
Open
Open
Open
Open
Open
Open
Transfer
0x00
ADC Functions 0x08 Power modes (local)
Open
Open
External powerdown pin function 0 = PDWN 1 = standby Open
Open
Open
Open
0x09
Global clock (global)
Open
Open
Open
Open
Open
Internal power-down mode 00 = normal operation 01 = full power-down 10 = standby 11 = digital reset Open Duty cycle stabilizer 0= Disabled 1= enabled
0x00
0x01
AD9648
Addr (Hex) 0x0B Register Name Clock divide (global) Bit 7 (MSB) Open Bit 6 Open Bit 5 Open Bit 4 Open Bit 3 Open Bit 2 Bit 1 Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 Chop Open Open 0= disabled 1= enabled Bit 0 (LSB) Default Value (Hex) 0x00 Comments The divide ratio is value plus 1
0x0C
Enhancement control (global)
Open
Open
Open
Open
Open
0x00
Chop mode enabled if Bit 2 is enabled
0x0D
Test mode (local)
User test mode control 00 = single pattern mode 01 = alternate continuous/repeat pattern mode 10 = single once pattern mode 11 = alternate once pattern mode
Reset PN long gen
Reset PN short gen
0x0E
0x10
0x14
BIST enable (global) Customer offset adjust (local) Output mode
Open
Open
Open
Open
Open
Output test mode 0000 = off (default) 0001 = midscale short 0010 = positive FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN long sequence 0110 = PN short sequence 0111 = one/zero word toggle 1000 = user test mode 1111 = ramp output Initialize Open BIST enable BIST sequence
0x00
When this register is set, the test data is placed on the output pins in place of normal data
0x00
Offset adjust in LSBs from +127 to 128 (twos complement format)
0x00
0x15
Output adjust
Output port logic type (global) 00 = CMOS, 1.8 V 10 = LVDS, ANSI 11 = LVDS, reduced range Open Open
Output Interleave enable (global)
Output port disable (local)
Open (global)
Output invert (local)
Output format 00 = offset binary 01 = twos complement 10 = Gray code
0x00
Configures the outputs and the format of the data Determines CMOS output drive strength properties Allows selection of clock delays into the input clock divider
0x16
Clock phase control (global)
Invert DCO clock 0 = not inverted 1= inverted
Open
CMOS 1.8 V DCO drive strength 00 = 1 01 = 2 10 = 3 11 = 4 Open Open
Open
Open
Open
0x17
Output delay (global)
DCO clock delay 0= disabled 1= enabled
Open
Data delay 0= disabled 1= enabled
Open
Open
CMOS 1.8 V data drive strength 00 = 1 01 = 2 10 = 3 11 = 4 Input clock divider phase adjust relative to the encode clock 000 = no delay 001 = one input clock cycle 010 = two input clock cycles 011 = three input clock cycles 100 = four input clock cycles 101 = five input clock cycles 110 = six input clock cycles 111 = seven input clock cycles Delay selection 000 = 0.56 ns 001 = 1.12 ns 010 = 1.68 ns 011 = 2.24 ns 100 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns
0x00
0x00
0x00
This sets the fine output delay of the output clock but does not change internal timing
AD9648
Addr (Hex) 0x18 Register Name VREF select (global) Bit 7 (MSB) Open Bit 6 Open Bit 5 Open Bit 4 Open Bit 3 Open Bit 0 Bit 2 Bit 1 (LSB) Internal VREF digital adjustment 000 = 1.0 V p-p 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.6 V p-p 100 = 2.0 V p-p B2 B1 B0 Default Value (Hex) 0x04 Comments Select and/ or adjust VREF
0x19
0x1A
0x1B
0x1C
User Pattern 1 LSB (global) User Pattern 1 MSB (global) User Pattern 2 LSB (global) User Pattern 2 MSB MISR LSB MISR MSB Overrange control (global)
B7
B6
B5
B4
B3
0x00
B15
B14
B13
B12
B11
B10
B9
B8
0x00
B7
B6
B5
B4
B3
B2
B1
B0
0x00
B15
B14
B13
B12
B11
B10
B9
B8
0x00
0x24 0x25 0x2A
Open
Open
Open
MISR LSB[7:0] MISR MSB[15:8] Open Open
Open
Open
0x2E
Output assign (local) Sync control (global) Sample rate override User I/O Control Register 2
Open
Open
Open
Open
Open
Open
Open
Overrange output 0= disabled 1= enabled 0 = ADC A 1 = ADC B (local) Open
0xFF 0xFF 0x01
Userdefined Pattern 1 LSB Userdefined Pattern, 1 MSB Userdefined Pattern 2 LSB Userdefined Pattern, 2 MSB Read only Read only Overrange control settings
0x3A
Open
Open
Open
Open
Open
Sync next only
Sync enable
ADC A = 0x00 ADC B = 0x01 0x00
Assign an ADC to an output channel Sets the global sync options
0x100
Open
Sample rate override enable Open Open
0x101
0x102
User I/O Control Register 3
Output enable bar (OEB) pin enable Open
Resolution 010 = 14 bits 100 = 12 bits 110 = 10 bits Open
Open
Open
Sample rate 011 = 80 MSPS 100 = 105 MSPS 101 = 125 MSPS Open Disable SDIO pulldown
0x00
0x00
OEB and SDIO pin controls
Open
Open
Open
VCM powerdown
Open
0x00
AD9648
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. interleaving feature. Channel A is sent on least significant bits (LSBs), and Channel B is sent on most significant bits (MSBs). The even bits are sent coincident with a high DCO clock, and the odd bits are sent coincident with a low DCO clock. For CMOS outputs, setting Bit 5 enables interleaving in CMOS DDR mode. On ADC Output Port A, Channel A is sent coincident with a low DCO clock, and Channel B is coincident with a high DCO clock. On ADC Output Port B, Channel B is sent coincident with a low DCO clock, and Channel A is coincident with a high DCO clock. Clearing Bit 5 disables the interleaving feature, and data is output in CMOS SDR mode. Channel A is sent to Port A, and Channel B is sent to Port B.
Power Modes (Register 0x08) Bits[7:6]Open

Bit 5External Power-Down Pin Function If set, the external PDWN pin initiates power-down mode. If clear, the external PDWN pin initiates standby mode. Bits[4:2]Open
Bits[1:0]Internal Power-Down Mode

In normal operation (Bits[1:0] = 00), both ADC channels are active. In power-down mode (Bits[1:0] = 01), the digital data path clocks are disabled while the digital data path is reset. Outputs are disabled. In standby mode (Bits[1:0] = 10), the digital data path clocks and the outputs are disabled. During a digital reset (Bits[1:0] = 11), the digital data path clocks are disabled while the digital data path is held in reset. The outputs are enabled in this state. For optimum performance, it is recommended that both ADC channels be reset simultaneously. This is accomplished by ensuring that both channels are selected via Register 0x05 prior to issuing the digital reset instruction.
Bit 4Output Port Disable

Setting Bit 4 high disables the output port for the channels selected in Bits[1:0] of the device index register (Register 0x05). Bit 3Open Bit 2Output Invert Setting Bit 2 high inverts the output port data for the channels selected in Bits[1:0] of the device index register (Register 0x05). Bits[1:0]Output Format 00 = offset binary 01 = twos complement 10 = Gray code
Enhancement Control (Register 0x0C) Bits[7:3]Open Bit 2Chop Mode

For applications that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct-conversion receivers, chopping in the first stage of the AD9628 is a feature that can be enabled by setting Bit 2. In the frequency domain, chopping translates offsets and other low frequency noise to fCLK/2 where it can be filtered.
Sync Control (Register 0x3A) Bits[7:3]Open Bit 2Clock Divider Next Sync Only
If the clock divider sync enable bit (Address 0x3A, Bit 1) is high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable bit resets after it syncs.
Bit 1Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 is high. This is continuous sync mode.
Bits[1:0]Open Output Mode (Register 0x14) Bits[7:6]Output Port Logic Type

00 = CMOS, 1.8 V 10 = LVDS, ANSI 11 = LVDS, reduced range
Bit 0Open Transfer (Register 0xFF)

All registers except Register 0x100 are updated the moment they are written. Setting Bit 0 of this transfer register high initializes the settings in the ADC sample rate override register (Address 0x100).
Bit 5Output Interleave Enable

For LVDS outputs, setting Bit 5 enables interleaving. Channel A is sent coincident with a high DCO clock, and Channel B is coincident with a low DCO clock. Clearing Bit 5 disables the
Sample Rate Override (Register 0x100)

This register is designed to allow the user to downgrade the device. Any attempt to upgrade the default speed grade results in a chip power-down. Settings in this register are not initialized until Bit 0 of the transfer register (Register 0xFF) is written high.
AD9648
User I/O Control 2 (Register 0x101) Bit 7OEB Pin Enable
If the OEB pin enable bit (Bit 7) is set, the OEB pin is enabled. If Bit 7 is clear, the OEB pin is disabled (default).
User I/O Control 3 (Register 0x102) Bits[7:4]Open Bit 3VCM Power-Down

Bit 3 can be set high to power down the internal VCM generator. This feature is used when applying an external reference.
Bits[6:1]Open Bit 0SDIO Pull-Down

Bit 0 can be set to disable the internal 30 k pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus.
Bits[2:0]Open
AD9648 APPLICATIONS INFORMATION

DESIGN GUIDELINES
Before starting design and layout of the AD9648 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain pins. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged to prevent solder wicking through the vias, which can compromise the connection. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. For detailed information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com.
Power and Ground Recommendations

When connecting power to the AD9648, it is recommended that two separate 1.8 V supplies be used. Use one supply for analog (AVDD); use a separate supply for the digital outputs (DRVDD). For both AVDD and DRVDD several different decoupling capacitors should be used to cover both high and low frequencies. Place these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length. A single PCB ground plane should be sufficient when using the AD9648. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved.
VCM
The VCM pin should be decoupled to ground with a 0.1 F capacitor.
LVDS Operation
The AD9648 defaults to CMOS output mode on power-up. If LVDS operation is desired, this mode must be programmed, using the SPI configuration registers after power-up. When the AD9648 powers up in CMOS mode with LVDS termination resistors (100 ) on the outputs, the DRVDD current can be higher than the typical value until the part is placed in LVDS mode. This additional DRVDD current does not cause damage to the AD9648, but it should be taken into account when considering the maximum DRVDD current for the part. To avoid this additional DRVDD current, the AD9648 outputs can be disabled at power-up by taking the PDWN pin high. After the part is placed into LVDS mode via the SPI port, the PDWN pin can be taken low to enable the outputs.
Reference Decoupling
The VREF pin should be externally decoupled to ground with a low ESR, 1.0 F capacitor in parallel with a low ESR, 0.1 F ceramic capacitor.
SPI Port
The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9648 to keep these signals from transitioning at the converter inputs during critical sampling periods.
Exposed Paddle Thermal Heat Slug Recommendations

It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD9648 exposed paddle, Pin 0.
AD9648 OUTLINE DIMENSIONS

9.00 BSC SQ 0.60 MAX 0.60 MAX
49 48 64 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 8.75 BSC SQ 0.50 BSC EXPOSED PAD
(BOTTOM VIEW)
6.35 6.20 SQ 6.05
0.50 0.40 0.30
33 32
16 17
0.25 MIN 7.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
SEATING PLANE
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 63. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters
ORDERING GUIDE
Model1 AD9648BCPZ-105 AD9648BCPZ-125 AD9648BCPZRL7-105 AD9648BCPZRL7-125 AD9648-125EBZ
1
Temperature Range 40C to +85C 40C to +85C 40C to +85C 40C to +85C
Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-64-4 CP-64-4 CP-64-4 CP-64-4
Z = RoHS Compliant Part.
091707-C
AD9648 NOTES
AD9648 NOTES
2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09975-0-7/11(0)

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14-Bit, 125 MSPS/105 MSPS, 1.

8 V Dual Analog-to-Digital Converter

FUNCTIONAL BLOCK DIAGRAM

ORA D13A D0A DCOA

VIN+A ADC VINA

VREF SENSE VCM RBIAS VINB ADC VIN+B REF SELECT

CMOS/LVDS OUTPUT BUFFER

ORB D13B D0B DCOB

DUTY CYCLE STABILIZER

PDWN DFS OEB

This product is protected by a U.S patent.

AD9648 TABLE OF CONTENTS

AD9648 GENERAL DESCRIPTION

0.8 4.20 0.5 2.3

Guaranteed 0.3 1.3 0.5

+0.2 +4.2 +1.2 +2.3

0.8 5.1 0.5 2.3

Guaranteed 0.3 1.3 0.5

+0.2 +5.1 +1.2 +2.3

Full Full Full Full Full

1.8 1.8 81 19.2 63.5

1.8 1.8 95 22.5 65.0

1.9 1.9 100

Temp Full Full Full Full Full

AD9648-105 Typ 135.4 172.3 180.4 108 2.0

AD9648-125 Typ 155.5 202.5 211.5 120 2.0

AD9648-105 Typ Max 98 90 93

AD9648-125 Typ Max 96 90 91

AD9628-105/125 Typ Max DRVDD + 0.2 0.6 135 +10 26 2

DRVDD + 0.2 0.6 +10 128

DRVDD + 0.2 0.6 134 +10

Full Full Full Full Full Full Full Full

Pull up. Pull down.

Temp Full Full Full Full Full Full Full

AD9648-105 Typ Max 1000

AD9648-125 Typ Max 1000

Unit MHz MSPS MSPS ns ns ns ps rms

20 10 9.52 4.76 1.0 0.07

1.8 2.0 1.2

4.4 4.4 +1.0

1.8 2.0 1.2

4.4 4.4 +1.0

ns ns ns ns ns ns Cycles Cycles s ns Cycles

+0.03 16 16/16.5 350 250 2

+0.03 16 16/16.5 350 250 2

ns min ns min ns min ns min ns min ns min ns min ns min ns min

Figure 3. CMOS Interleaved Output Mode Data Output Timing

Figure 4. LVDS Modes for Data Output Timing

Figure 5. SYNC Input Timing Requirements

AD9648 ABSOLUTE MAXIMUM RATINGS

Airflow Velocity (m/sec) 0 1.0 2.5

JA1, 2 22.3 19.5 17.5

JC1, 3 1.4 N/A N/A

JB1, 4 N/A 11.8 N/A

JT1,2 0.1 0.2 0.2

Unit C/W C/W C/W

AD9648 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 6. Parallel CMOS Pin Configuration (Top View)

Table 8. Pin Function Descriptions (Parallel CMOS Mode)

Figure 7. Interleaved Parallel LVDS Pin Configuration (Top View)

Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)

Figure 8. Channel Multiplexed LVDS Pin Configuration (Top View)

Table 10 Pin Function Descriptions (Channel Multiplexed Parallel LVDS Mode)