Department of Electrical Engineering Politeknik Port Dickson

PROGRAMME : DTK6-S1, DTK6-S2 CODE & COURSE NAME : E5163- INTEGRATEED CIRCUIT DESIGN TITLE : MOS Transistor Fabrication IC Design Methodology ASSIGNMENT :2 MATRIX NO. : NAME: DATE : 27 September 2011

I STRUCTIO : A SWER ALL QUESTIO S.

1. Explain the NMOS transistor fabrication process sequence based on wafer cross-section diagram shown in Figure 1.
Source Gate Drain Polysilicon SiO2

n+ p

n+ bulk Si

Figure 1 (12 marks, CLO2, JSP3.1, M)

2. Draw the physical structure of a Twin-tub CMOS transistor. (3 marks, CLO2, JSP3.2, L)

Department of Electrical Engineering Politeknik Port Dickson

PROGRAMME : DTK6-S1, DTK6-S2 CODE & COURSE NAME : E5163- INTEGRATEED CIRCUIT DESIGN TITLE : MOS Transistor Fabrication IC Design Methodology ASSIGNMENT :2 MATRIX NO. : NAME: DATE : 27 September 2011

I STRUCTIO : A SWER ALL QUESTIO S.

3. Explain the characteristic of a Twin-tub CMOS transistor. (3 marks, CLO2, JSP3.2, M)

** Any 3 related explanation.

(3 marks)

The starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer (~1015/cm3, 10 -cm) on top. n-well and the p-well are formed in epitaxial layer. Suitable for high-performance chips. Since the substrate is lightly doped, there is less chance for latch-up because of the high resistivity.

4. What is the purpose of Well Tap and Substrate Tap in the physical structure of a CMOS inverter? (2 marks, CLO2, JSP3.3, L)

A P-type substrate "tap" is connected to VSS and an N-type n-well tap is connected to VDD to prevent Latchup. (2 marks)
5. Explain the parasitic capacitance problem that exists in CMOS transistor operation. (5 marks, CLO2, JSP3.3, M)

(2 marks) ** Any 3 related explanation. (3 marks) Parasitic capacitance is the unavoidable and usually unwanted capacitance that exists between Gate-Source and Get-Drain simply because of their proximity to each other. At low frequencies parasitic capacitance can usually be ignored, but in high frequency circuits it is a major problem. The parasitic capacitance between the base and collector of transistors and other active devices is the major factor limiting their high frequency performance. It could result in false switching in high frequency circuits.

Department of Electrical Engineering Politeknik Port Dickson

PROGRAMME : DTK6-S1, DTK6-S2 CODE & COURSE NAME : E5163- INTEGRATEED CIRCUIT DESIGN TITLE : MOS Transistor Fabrication IC Design Methodology ASSIGNMENT :2 MATRIX NO. : NAME: DATE : 27 September 2011

I STRUCTIO : A SWER ALL QUESTIO S.

6. Draw the physical structure of Silicon On Insulator (SOI). (3 marks, CLO2, JSP3.2, L)

(3 marks)
7. Explain the characteristic of Silicon on insulator (SOI) CMOS transistor. (3 marks, CLO2, JSP3.2, M)

Completely isolated nMOS and pMOS transistors side-by-side on an insulating substrate. higher integration density complete avoidance of the latch-up problem lower parasitic capacitances compared to n-well or twin-tub CMOS.
(5 marks, CLO2, JSP3.3, M)

8. Explain the latch-up problem that exists in CMOS transistor operation.

Latchup is a type of short circuit which can occur in an improperly designed circuit. It is an unintentional creation of a low resistance path between the VDD and GND triggering a parasitic structure which disrupts proper functioning of the part and possibly even leading to its destruction due to overcurrent. The parasitic structure is usually equivalent to a thyristor (or SCR), a PNPN structure which acts as a PNP and an NPN transistor stacked next to each other. During a latchup when one of the transistors is conducting, the other one begins conducting too. They both keep each other in saturation for as long as the structure is forward-biased and some current flows through it - which usually means until a power-down.

Department of Electrical Engineering Politeknik Port Dickson

PROGRAMME : DTK6-S1, DTK6-S2 CODE & COURSE NAME : E5163- INTEGRATEED CIRCUIT DESIGN TITLE : MOS Transistor Fabrication IC Design Methodology ASSIGNMENT :2 MATRIX NO. : NAME: DATE : 27 September 2011

I STRUCTIO : A SWER ALL QUESTIO S. A power cycle is required to correct this situation.

9. Define Application-Specific Integrated Circuit (ASICs). (2 marks, CLO3, JSP4.1, L)

Application Specific Integrated Circuit or ASIC is a chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. (2 marks)
10. Discuss the advantages and disadvantages of Specific-Custom IC over Standard IC. (6 marks, CLO3, JSP4.1, H)

i. Specific-custom IC have better performance, but they have higher manufacturing costs and lack the flexibility. If there is a change in the application, it is hard to reflect the change in the design. (3 marks) ii. Standard IC, on the other hand, are not optimized for a specific applications and hence do not provide satisfactory performance for most of the applications. (3 marks)
11. Compare the differences between Semi-Custom methodology and Full-Custom methodology. (6 marks, CLO3, JSP4.2, JSP4.3, H)

** Any 3 related answer for Semi-Custom. (3 marks) ** Any 3 related answer for Full-Custom. (3 marks) Semi-Custom Larger chip size. Less number of mask. Shorter design time. Poor performance. Full-Custom Smaller chip size. More number of mask. Longer design time. High performance.

12. Describe Standard Cell Library. (5 marks, CLO3, JSP4.5, L)

A Standard Cell Library is a collection of low-level logic functions such as AND, OR, INVERT, flipflops, latches, and buffers. These cells are realized as fixed-height, variable-width full-custom cells. The key aspect with these libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process of automated digital layout. The cells are typically optimized full-custom layouts, which minimize delays and area.

Department of Electrical Engineering Politeknik Port Dickson

PROGRAMME : DTK6-S1, DTK6-S2 CODE & COURSE NAME : E5163- INTEGRATEED CIRCUIT DESIGN TITLE : MOS Transistor Fabrication IC Design Methodology ASSIGNMENT :2 MATRIX NO. : NAME: DATE : 27 September 2011

I STRUCTIO : A SWER ALL QUESTIO S.

13. Discuss the advantages and disadvantages of Standard cells methodology. (6 marks, CLO3, JSP4.5, H)

Advantages: (3 marks) 1. Short design turn-around time as the cells are predefined and need only to be laid out and connected. 2. The standard cell method allows each cell to be optimized individually. Thus, higher performance designs can be created, because each cell can be optimized for maximum speed and minimum area.

Disadvantages: (3 marks) 1. Wasted chip area will be high, the area occupied by the wiring channels can exceed 50% of the internal chip. However, this problem can be greatly reduced by using multiple metal layers in chip designs. 2. Since the cells are not prefabricated ahead of time, there is no savings in fabrication time.
14. Discuss at least 2 methods to increase the percentage of gate usage in gate array design. (4 marks, CLO3, JSP4.4, M)

(4 marks) i. Increase number of gates by increasing functionality. ii. Decrease number of available gates by providing just enough gates for interconnection.
15. Explain the advantages and disadvantages of full-custom methodology. (6 marks, CLO3, JSP4.2, M)

Advantages of Full-Custom Methodology: (3 marks) Improve performance Reduce power consumption Mix Analog and Digital Designs Design optimization through IC manufacturing process Development Tools support HDL and Schematic design approach Disadvantages of Full-Custom Methodology: Inflexible design Deployed systems can not be upgraded Mistakes in product development are costly Updates requires a redesign Complex and expensive development tools (3 marks)

Department of Electrical Engineering Politeknik Port Dickson

PROGRAMME : DTK6-S1, DTK6-S2 CODE & COURSE NAME : E5163- INTEGRATEED CIRCUIT DESIGN TITLE : MOS Transistor Fabrication IC Design Methodology ASSIGNMENT :2 MATRIX NO. : NAME: DATE : 27 September 2011

I STRUCTIO : A SWER ALL QUESTIO S.

16. Explain the gate-array design floor plan with aid of a diagram. (7 marks, CLO3, JSP4.4, M)

rows of uncommitted cells

routing channel
(3 marks) A gate-array (MPGAs) consists of transistors prefabricated on a wafer in the form of a regular 2-D array. Initially the transistors in an array are not connected to one another. In order to realize a circuit on a gate-array, metal connections must be placed using the usual process of masking (personalizing). (4 marks)

17. Describe the design methodology selection criteria. (5 marks, CLO3, JSP4.6, H) Methodology depends on: Type of chip Size of chip design time constraints Cost/performance Available tools