JVC Plasma Troubleshooting Manual

PDP Troubleshooting
PD-42WV74 GM-X50U PD-42X776 PD-42X795
PD-42WX84 GM-V42UG PD-42V475/485 PD-50X795
Page 1 notes.
The models that apply to this course are the following, PD-42WV74, PD-42WX84, GM-X50U, GMV42UG, PD-42X776, PD-42V475/485, PD-42X795, PD-50X795.
Course Contents
Plasma Basics Panel Trouble Shooting Without the CPU Service Cautions Power Supply And Y-Main Adjustment Info HDMI/DVI Reset Info
Page 3 notes.
The topics covered will be Plasma Basics (review), Panel Trouble Shooting Without the CPU, Service Cautions, Trouble Shooting techniques, Power Supply and Y-Main Adjustment Information, and HDMI/DVI reset Info.
Plasma Basics: Pixel

Voltage breakdown Movement of electrons. Ionization of the gas Multiplication of electrons Plasma Xe excitation. UV radiation. Phosphor excitation. Visible light emission.
Display electrodes are Horizontal and address electrodes are vertical

5
Page 5 notes. ********Plasma: This is one of the four states of matter (The other three are solid, liquid and gas). Plasma consists of a gas of positively charged and negatively charged particles with approximately equal concentrations of both so that the total gas is approximately charged neutral. A plasma can be produced from a gas if enough energy is added to cause the electrically neutral atoms of the gas to split into positively and negatively charged atoms and electrons. One pixel; imagine a cube with phosphorus coating at the bottom and filled with Xenon gas. When we apply a voltage on the two electrodes (shown as 1) the gas ionizes. When the gas ionizes as in area 3, UV radiation occurs. This action is similar to a CRT. If this radiation is forced to hit the phosphor (4), light emits. This is the basic principle of one plasma cell. One red, one green, and one blue cell together forms one pixel or Plasma cell. The diagram shown illustrates light emission for a single color. Besides the green, the red and blue are shown and they function likewise. Sequence of events: When a voltage is applied, between the Scan and Sustain electrodes (identify) (electrode marked 1), movement of electrons occurs (identify as area marked 3). This causes multiplication of electrons by gas ionization: This state of gas is known as Plasma. This excitation produces UV radiation. At this point, if we apply a voltage to the phosphor (Address electrode marked 5), it attracts electrons causing Phosphor Excitation and therefore, Visible Light emission. The electrodes we apply excitation voltage to are known as scan and sustain electrodes (1). To simplify, a voltage is applied to the scan and sustain electrodes (1). Then xenon gas excitation occurs. Once the electrons are multiplied due to ionization, emission occurs. Now a voltage (5) is applied to the phosphor for attracting the electron and producing the light. This is how the light output occurs in a Plasma environment. The brightness of the pixel is a function of timing the potentials on the scan, sustain and address electrodes. Now that we have seen, how one cell emits light, let us see how we made a video display panel with this. 6
Plasma Basic: Panel

Cells are arranged vertically to form red, green, and blue stripes Transparent electrodes are used to apply voltage Both sides are protected by glass substrate
Page 7 notes.
A plasma display unit is a panel that consists of many tiny cells filled with a neon xenon. Gas as explained in the previous slide. Let us see how they are arranged to get a panel. Same color cells are arranged in vertical row. When we look from the front, we can see stripes. The ionization voltage is applied through the scan and sustain electrodes positioned horizontally over each row of cells. We already discussed that when voltage is applied between two electrodes inside a cell, ultraviolet radiation occurs and now voltage corresponding to incoming video is applied to the corresponding address line which is located perpendicular to the scan and sustain electrodes. This is called matrixing. This applied address voltage excites the phosphors lining in the cells and light is produced. Let us look how a voltage is applied to these cells.
Plasma Basics: Electrodes

Transparent Scan and Sustain electrodes on the front Data electrodes on the back Controlling the scan, and data, pulse duration, we can control the light output
Page 9 notes.
This is yet another way of illustrating the arrangement. Vertical cells are shown as the vertical phosphor bars. Horizontal electrodes are transparent electrodes and are across the screen under the front glass. They are virtually transparent and do not affect light output. When the scan and sustain voltage is applied, ionization occurs inside each cell, the address electrode is energized to excite the phosphor. We all know about phosphor characteristics. Light output from phosphor depends on two things, that is, the amount of electrons and the time of excitation. Depending on how long the phosphor is excited, the brightness changes. Since we have a matrix of horizontal and vertical electrodes, each cell can be controlled independently. How did this display become so attractive for video industry? One reason is the ability to produce large enough displays. Now they are up to 50 displays and larger are possible. Another is the characteristic is the low atmosphere gas filled chamber. There is no warm-up time. There are no convergence or registration issues. High light output, good color saturation and high contrast ratio are other advantages.
10
Plasma Basics: Overall

Pixels: Formed by two sheets of glass with ribs Electrodes: Three electrodes, one at the rear and a pair at the front Turn ON: Approximately 200 V applied between address and Y (scan) electrodes causes gas ionization and light emission Sustain: Approximately 50 V is applied between the Y (scan) and X (sustain) electrode to hold the light emission Turn OFF: Remove the sustain voltage and reverse the address voltage.
11
Page 11 notes.
Here is one more representation of the design of the plasma panel. It is a more practical and realistic view. The plasma panel is composed of two sheets of glass with the bottom glass having series of ribs filled with color phosphors in a particular order. The top glass with embedded electrodes seals upon that and helps form a pixel. Inside the sealed pixel, is a mixture of rare gases- typically argon and neon, although sometimes xenon has been used. Actually with this construction, a small electric capacitor has been created, with one electrode on the rear (Address) and a pair on the front (Sustain and Scan). These 3 electrodes control the capacitor charge, sustain and discharge functions intrinsic to the plasma imaging process. The plasma imaging cycle can be broken into following steps. initially, the pixel is at its resting (Off ) state. while a voltage is applied to the addressing electrodes ( pixel ). When the applied voltage reaches a certain level- say 200+ volts - the resistance in the pixel is overcome, and an electrical discharge is made across the electrodes. Once this discharge occurs, the mixture of rare gases is ionized into a plasma state, which means the gas mixture can now conduct electricity, an intense burst of ultraviolet ( UV ) light is emitted. This burst of UV energy stimulates the color phosphors, in turn makes them glow brightly. Once the pixel is switched On (Scan and Sustain), a much lower voltage sustains the UV emissions and keeps the phosphors glowing. This sustain voltage is typically in the 50 volts range. Eventually, the pixel will need to be turned off to rest the phosphors. This is done by removing the sustain voltage first, then reversing the charge in the pixel through the addressing electrodes to achieve precise and complete turn-off. At this point, the pixel is back to its resting state. 12
Plasma Basics: The Image
SF1
1 2 .. .. 480 .
SF2
SF3
SF4
SF5
SF6
SF7
SF8
scan line
i rig O sub-field
I al n
ag
address
1T 2T 4T 8T 16T 32T 64T 128T
sustain
1TV field (time)

13
Page 13 notes.
Here we can see how each individual image is built. Each image corresponds to 1 TV field and within that time period there are 8 sub-fields of different duration in order to obtain the correct brightness for each pixel. This works out to 479.52 address and 479.52 sustains every second with 200 volts being applied during the address time period of the sub-field between the scan and address electrodes and 50 volts being applied during the sustain time period of the sub field between the sustain and scan electrodes. Keep in mind that every pixel needs to be addressed during each subfield.
14
Y (Scan) Electrode
X (Sustain) Electrode
Address Electrode
15
Page 15 notes.
In this slide we can see that we have a XVGA or WXGA screen resolution panel. Lets say for example that we want to light up only two pixels represented by the yellow circles. Putting it simply, first the two pixels would be lit by the Address part of the 8 section TV Field process, this is represented by the orange arrows from the Y (Scan) Electrode and the red arrows from the Address Electrodes (this will make the pixel glow). In the Sustain part of the 8 section TV Field process the pixels that are now glowing are kept glowing by the Scan Electrode ( orange arrows) applying signal while the total panel X (Sustain) Main signal (white arrows) is sent out. During the Sustain period the entire panels X Electrode is energized while only the applicable Y Electrodes are energized. Remember that this entire process will happen about 8 times per tv field and about 480 times a second.
16
Y (Scan) Electrode
X (Sustain) Electrode
Address Electrode 17
Page 17 notes.
This is the representation of a WVGA screen resolution panel. The same process applies but with only the lower Address Buffer. The exception to the WVGA = one row of Address Buffers rule is the PD42X776, which is XVGA resolution with only 1 row of address buffers.
18

To Y-Main (Scan) LVDS Input
n I p u t C o n n e c to r o f Lo g i P o w e r c S o u rc e
To X-Main (Sustain)
E xt rn a l I te r a l e /n n S e l c to n S w i c h e i t
M em ory C ont l roler
F ront P rocessor
D at C l ck a o G enerat r(60M H z) o
To Address (Logic) Buffers 19
Page19 notes.
Here is the a typical pdp Logic Board. The major sections being the Front Processor and Memory Controller sections along with the individual X, Y, and Address outputs. This is the board that processes the video signal provided by any A/V input assemblies into the LVDS input connector along with the X,Y, and Address output signals that will illuminate individual pixels to the proper intensity on the pdp panel to create each image 59.94 times a second.
20
Plasma Basics: Panel Overview

Upper Y Buffer Y-Main (Scan) Video SMPS SMPS Logic Main Voltage X-Main (Sustain) label
Scan(Y) Electrodes
Power Outputs from SMPS
Y-Main Data
Address Buffer Data
X-Main Data
Lower Y Buffer
Address Buffer(E)
Address Electrodes
Address Buffer(F)
Address Buffer(G)
Sustain(X) Electrodes 21
Page 21 notes.
This is the typical layout of a pdp panel once the rear cover and any A/V input boards, mounting supports, speakers, etc are removed. It should be noted that once you are familiar with the locations of these major parts you will find that any other pdp panel will be surprisingly similar in layout and function. It should be noted that Address Buffers on different panels may be labeled with different letters.
22
Plasma Basics: Board Functions

SMPS (Switching Mode Power Supply) : Supplies voltage and current to operate the complete assembly.
X-Main (Driver) Board : According to the timing provided from Logic board, switches the FETs and generates the driving waveform which is provided to X electrode of Panel. Y-Main (Driver) Board : According to the timing provided from Logic board, switches the FETs and generates the driving waveform which is provided to Y electrode of Panel sequentially through Scan Driver IC of Scan Buffer. Logic Main Board : Processes the image signal and generates Address, X, and Y driving output signal. Address Buffer Board(E,F) : Transfers the data and control signal to the Address electrodes of the PDP. Y (Scan) Buffer(Upper,Lower) : Transfers the scan waveform to the Y electrode, which consists of Upper Board and Lower Board assemblies. 23
Page 23 notes.
These are the functions of the major circuit boards that operate the pdp panel.
24
Service Precautions
25
Page 25 notes.
The next several frames may have specifics that pertain to certain models but in general will be applied to any pdp panel you may be servicing.
26
Service Precautions
The drive circuit operates at 350V. In-order to remove PWB after power off, wait approximately 5 minutes for the capacitors to discharge
On the connectors, one of the wires is a different color. This is not always pin1. Refer to the pin ID on PWBA.
27
Page 27 notes.
The Power Factor Control on the Switch Mode Power Supply has an operating voltage of 350 volts. When powering off the unit and before removing any connectors, it is recommended that a five minute wait is used to allow the residual capacitor charges to drain off. It is also important to know that not all connectors use the black wire to identify the connection as Pin 1. ALWAYS look at the silk-screen printing on the BOARD to identify pin 1 of any of the connectors in this unit.
28
Service Precautions
Do not apply power with any of these connectors disconnected on a one by one basis. Operation with any of these disconnected individually could result in damage to the X or Y Main PWBAs.
29
Page 29 notes.
Powering on the unit with the connectors identified here disconnected can cause damage to the unit. While this damage may not occur immediately, it will after a short time. This caution should be observed at all times to avoid damage to the X-Main and Y-Main boards. The damage can be caused by improper loading of the panel and reverse voltages from the panel being introduced to the boards. It should be noted that if connectors providing power to the X-main, Y-Main, and Address Buffer Boards are all disconnected it is acceptable to apply power. This procedure will be used later in the course to test the power supply.
30
Service Precautions
Do not power on with Flexible cable (Panel XDrive) disconnected. This could cause Main SMPS damage
Tuner
When servicing the Receiver (Tuner) with cover open, before applying power, disconnect the DVI modules power connector.
31
Page 31 notes. Additionally, powering on the unit with the X-Main drive connectors disconnected could cause damage to the Video SMPS or the X-Main due to improper loading of the SMPS. When these connectors must be taken out, remember that the flex cables themselves have locating and squaring holes in them that hold them in place on the X-Main board sockets. It is also possible to miss the hole, or insert incorrectly. If they are not inserted correctly and secured, damage to the Video SMPS can occur. Shown in the green circle is the tuner/receiver disassembly (refer to the service manual). The caution here is that you must be sure to disconnect the power to the DVI (HDCP) module. NEVER remove the cover of the unit while it is plugged in. This will deauthorize the DVI module and render it incapable of passing High Definition Content Protected information..
32
Service Precautions
This caution applies to the PD42X475.
33
Page 33 notes.
This note of caution was taken from the service manual for the PD-42V475. There is no caution in the manuals for the PD-42X776S, PD-42X795S, or the PD-50X795 which have DVI/HDMI connections either in the PDP section or in the external tuner box so the caution should still apply, although a method to reset these modules may exist. If the sensor cannot be located please disconnect the power connector from the circuit board or module if the unit must be powered up with the rear cover removed (preferred method). Again do not remove the rear cover with the power connected or connect the power if the above caution is not followed when working on the PD-42V475. the DVI/HDMI will be disabled otherwise.
34
Service Precautions
When replacing Logic Main PWB, we must use the old ROMs. These ROMs contain panel adjustment information such as Gamma, Shading, etc.
When replacing Y-Main PWB, readjust the potentiometers exactly as in the existing PWB. These adjustments could affect picture quality.
35
Page 35 notes.
******************Very important.****************** Logic main replacement and Y-Main replacement precautions. As stated in the slide, when replacing the Logic Main board, be sure to move the old EEPROMs from the defective Logic Main board to the new board. Failure to do so may result in poor or no operation. These EEPROMs are socketed devices and they can be easily moved. When replacing the Y-Main board, observe the physical positions of the adjustment pots on the old board and adjust the new boards pots to the same physical configuration. Leaving them unadjusted could cause deterioration in picture performance.
36
Service Precautions
Always clean the FFC and connectors while reassembling PWBs.
37
Page 37 notes.
******Because some of the signals used in digital transmission are low current and low voltage in nature, any naturally occurring corrosion could affect electrical contacts. For this reason, when servicing the product, clean the flat flexible cables and the contacts as much as possible. Do not use abrasive materials. Gentle motion and the use of alcohol for cleaning should be sufficient.**********
38
Service Precautions
X-Main disassembly. Free the flexible connection from the tabs before removing the flexible cable X-Main reassembly: Confirm that the flexible is seated and locked properly before applying power.
39
Page 39 notes.
*****Do not jerk on the X-main connector during removal.***** It is locked with two tabs under the FPC. While disassembling, first press the flexible wiring away from you to free it from the tabs. Then gently remove the FPC. Conversely, while reassembling, make sure the tabs are locked in place and seated and the flex cable is properly inserted before locking. Powering the unit without these connectors could damage the units XMain board or the SMPS.
40
Panel troubleshooting without CPU.
1. Remove the shield cover
2. Remove the bracket
3. Remove the Speaker connector
4. Carefully raise the Video process Assembly

41
Page 41 notes. In order to access the Y-main triggering points and the Logic Main PWBA, the JVC interface box must be removed. If this assembly is to be removed, remember that it is possible to return some of the connectors to an incorrect location. To avoid problems, mark the connector bodies and their matching connectors with a swipe of a magic marker. That way, when you reassemble, you need only to match up the marks. Besides the connectors, there is one ground wire that is attached to the Logic Main board. Remove this black wire by taking out the retaining screw, but always remember to reattach it on reassembly. Left un-attached, it may come in contact with voltages and damage other parts. In the case of the PD-42WV74 and the PD-42WX84 the JVC boards are held in place by four small screws. Two of these screws also hold the top shield. Remove the bracket as in step two. This bracket is held in place with small machine-type screws. These screws are fragile and if over-torqued, the heads will snap off and you will have to remove the remains and re-tap the hole. Do not over-tighten these screws when re-assembling. Remove the connector from the audio board that leads to the units speakers at the bottom, and the two cables that go to the side speakers.. Carefully lift the JVC unit up and use the test point on the logic main for triggering the scope. Please note that depending on the model you are working on the disassembly instructions will be different, please consult the appropriate service manual for the instructions. 42
Logic Main Dip Switches

ON SD
When operating with LVDS signal connected, set the Logic-Main-PWB DIP Switches are set to External mode ( 2 and 4 are set to ON)
In test mode (without LVDS signal, change the DIP switch settings to Internal mode (3 ON, all other are off) Refer to Panel troubleshooting
43
Page 43 notes. In all units, there are some boards that belong to JVC and some that belong to the original equipment manufacturer. Shown here are the positions for the DIP switches in both normal (external) and test (internal) operations. The internal mode is used when the two JVC boards are not in the assembly and connected. Unless you are troubleshooting without the A/V Input PWBAs (JVC boards), do not leave the switch in Internal mode. When using the internal mode, it is not possible to use signal input. However, the plasma display will light up to a grayish or white screen. This is an aid to determining panel defects. When testing is completed, be sure to return the DIP switches to their normal positions, that is with switch 2 and 4 in the ON position The PD-50X795 and GM-X50U do not have an internal mode and this function will not be available. 44
On the Logic Main PWB, set DIP switches as follows S1:-OFF, S2:-OFF, S3:-ON, S4:-OFF This is Internal Sync mode
45
Page 45 notes.
Here is the general location of the dip switches on the Logic Main Board. Some Logic Main Boards will have the switches located in a slightly different location on the Logic Main Board depending on the model and board versions, others will have jumpers. For the units with the dip switches the settings for internal/external sync mode are the same for all models. The GM-X50U and PD-50X795 will not look like this and will not have any switches or jumpers.
46

Normal Settings Internal Sync Settings
If the Logic PWBA has jumpers instead of switches, these are the settings.
47
Page 47 notes.
This logic PWBA may be found in the PD-42WX84 models. It has jumpers instead of dip switches. The picture here shows the correct settings for internal sync mode and the settings for normal (video input) mode. Remember to place the jumpers back to the normal/external/video sync mode once the repair is completed and before the unit is re-assembled.
48

Pin numbers 1. STB5V (orange) 2. GND 3. SW 5V 4. GND 5. Therm Det 6. ACDET 7. PWR ON 8. Panel PWR
From the CPU PWB, disconnect the power control wire connectors CN00Q and CN00E Pin 1 is the Orange Colored wire
49
Page 49 notes.
With the use of the internal sync mode, we will have to configure some connections to be able to power the display unit for troubleshooting. The pin functions are called out at the right of the picture. To set up for the Internal Sync mode, we will concern ourselves with pins 3, 7 and 8. No video input will be required when testing the panel with this method. This method should be used with PD-42WV74, PD42WX84, and GM-V42UG models.
50
Short Pin 3 and Pin 8 so that the switched 5V can turn on the panel.
51
Page 51 notes.
This is CN00Q with pins 3 and 8 shorted. A short piece of hook-up wire is used. Do this carefully so as not to damage the connector. This will satisfy the connection needed to combine the Switched 5 volts with Panel Power.
52
Connect a hook up wire from the main power on pin. Grounding this pin will turn on the power
53
Page 53 notes.
A hookup wire is added to connector CN00Q Pin 7. Do not connect it anywhere at this time. This wire is used in a later step.
54
Apply power to the AC input

55
Page 55 notes.
Once the previous steps have been performed, the unit will be able to operate independently of the umbilical cable from the tuner box. Notice in this and previous pictures that the JVC boards are still in place. This is an option if you wish to troubleshoot without removing this assembly. AC power can be applied here, and if the JVC boards have been completely removed, AC power can be directly applied to the panels SMPS with a simple two pin connector attached to a properly polarized AC cord. This is the step where AC power is supplied to the panel.
56

Pin numbers 1. STB5V 2. GND 3. SW 5V 4. GND 5. Therm Det 6. ACDET 7. PWR ON 8. Panel PWR
Attach the hook-up wire to a ground point to turn on the power When power turns on, the SW5 will turn on the panel Make all measurements, adjustments, etc. Before closing, set the DIP switches to their normal positions
57
Page 57 notes.
Once AC power has been applied, the wire attached to Pin 7 of CN00Q can be attached to a metal chassis ground point. When the power turns on, the jumpered Switched 5 volts to Panel Power will turn on the panel. At this step, whatever measurements and adjustments to the panel can be accomplished. When all testing has been completed, and before reattaching the JVC boards, remember to return the DIP switches to: 1 and 3 OFF, 2 and 4 ON. The unit will not pass signal if left in the INTERNAL SYNC mode.
58

Pin numbers
1. STB5V 2. GND 3. AC_CLOCK 4. GND 5. TEMP_DET 6. AC_DET 7. POWER 8. PANEL_POWER
New style PS with large aluminum heat sink plate.

For models with the newer style (JVC) Power Supply, the cable from CN9001 of the Main Regulator PWBA ASSY will be followed and removed at the opposite end, then 1 and 8 will jumped. AC will then be applied. 59
Page 59 notes.
This is the method in which to operate the panel in internal sync mode with the PD-42V475/485, PD-X795, and PD-X776. This particular picture is of the PD-V475 which has an internal tuner. The PD-42X776 will look the same while the PD-50X795 will be similar to the PD-42WV74 and PD42-WX84 (as seen on page 19) but will use the same internal mode power up procedure as seen here.
60

Photo of PD42V475. The PD-42X776 will be similar.
This assy must be loosened or removed in order to access the dip switches on the Logic Main Board, please consult the service manual for disassembly instructions. Take care not to damage any FFCs while disassembling this section or accessing the Logic Main Board. 61
Page 61 notes.
The models that have this A/V Input (JVC Boards) set up have a few FFCs and wire assemblies that run across and underneath this assy. Care should be taken when accessing the Logic Main Board or when removing this assy.
62
PDP Trouble Shooting Basic Flow Chart

Verify Proper Power Supply Operation
Verify Proper Operation of Y-Main and X-Main PWBAs Identify if problem is horizontal or vertical in nature Exchange Address or Y Buffer PWBAs depending upon existing problem
Exchange PDP
63
Page 63 notes.
This is a simplified flowchart of the pdp trouble shooting process. With respect to the chart not every step will be required for all repairs once the technician is familiar with the different types of problems Plasma sets experience and will be able to skip over most of the chart and individual steps.
64
Troubleshooting Summary
Condition Name
No Voltage Output No Display
Description
Operating Voltages dont exist
Related Board
SMPS
Operating Voltages Y-Main, X-Main, are good but there is Logic Main, Cables no picture Abnormal Image Horizontal Lines may be missing or may be the same Y-Main, X-Main, Logic Main Scan Buffers, FPC of X/Y-Main PWBA
Abnormal Display Sustain Open or Short Address Open or Short
Some vertical lines Logic Main, Address appear linked or are Buffer, FFC, COF missing
65
Page 65 notes.
Here is a table of the different conditions related to the boards that may be defective. Each row in the table will have a different trouble shooting technique and as can be seen from the table many of PWBAs can be attributed to nearly all of the symptoms.
66
No Voltage Output Troubleshooting
Test at 2pin ac input connector
AC Input Condition
NG Check Line Filter Fuse, Replace As Required
OK
Check SMPS Fuses
NG Replace SMPS and Check X/Y-Main in advance
OK
Continue 67
Page 67 notes. Here we can see that in the event that the technician suspects that the power supply is non operational the first step is to check for 120VAC at the 120VAC input connector on the Main SMPS. If it is absent the fuse on the ac filter board should be checked and replaced if necessary. Once 120VAC has been established at the connector on the Main SMPS board the fuses on the Main SMPS board should be checked. Depending on the required procedure the individually fuses may need to be replaced and the operation of the Main SMPS checked. In most cases the Main SMPS will need to be replaced. The Main SMPS should also be inspected for parts with physically damaged parts and burn marks on the board and heat sinks.
68

Verify 120VAC Input At SMPS AC Input Connector Typically Found In This Location.
69
Page 69 notes.
Here is the general location for the 120VAC input connector. This connector is a two pin Molex type connector often times found in JVC televisions. If a power cord can be found from an old TV it can be used to power the plasma panel with the A/V Input PWBAs completely removed and out of the way. A polarized power cord with an inline fuse should be used.
70
Check the Line Filter PWBA Fuse
71
Page 71 notes.
This is the location of the fuse on the Main Filter PWBA. It is similar on all JVC models and is always mounted along with any A/V Input (JVC) PWBAs.
72
Continue
Check SMPS Output Voltages
OK Continue to No Display Troubleshooting
NG Disconnect AC power. Now remove X-Main, Y-Main, and Address Buffer power connectors. Re-apply AC power and recheck SMPS Output Voltages. OK Continue to No Display Troubleshooting 73
NG Replace SMPS
Page 73 notes.
Once it has been established that the Main SMPS does not have any open fuses and is not causing any fuses to open the technician will be able to check the individual output voltages of the Main SMPS PWBA. If they are all OK the technician can go to the No Display Trouble Shooting section. If the output voltages are not good the cable assy that leads to X-main, Y-main, and Address PWBAs can be disconnected to check if any of these PWBAs are loading the Main SMPS PWBA. Note: These connectors must be all be disconnected in the power off mode otherwise damage may occur to the pdp, X-Main, or Y-Main PWBAs. If the voltages check good the tech can proceed to the No Display Trouble Shooting section. If the voltages do not check good the Main SMPS must be replaced. Adjustment is mandatory in order to avoid PWBA damage and premature pdp failure.
74
Power Supply Trouble Shooting
Verify SMPS Output Voltages
Voltage Specification Label On PDP
Typically Found In These Locations
If these check good please proceed to XMain and Y-Main Trouble Shooting
Typical Adjustment Section From Service Manuals
75
Page 75 notes.
Here are the locations of nearly all of the voltages that should be checked. Again this is very typical of all pdp assemblies. There are also voltage outputs like 5VDC and 15VDC which do have adjustments and test points. These can be easily be found on the pwba itself and are usually not found in the adjustment sections of the service manuals. It should be noted that each individual panel will have specific adjustment needs which will be found on a Voltage Specification Label on the pdp itself.
76

If the SMPS output voltage is not correct please check the fuses on the SMPS.
If fuses are NG please replace the SMPS board.
PD-42V475 Power Supply Fuse Location

Please locate and check the fuses on the particular PS you are working on.
77
Page 77 notes.
Here are the locations of the fuses on the Main SMPS of the PD-42V475. This board will normally have a flat aluminum plate on top of the heat sinks that will need to be removed to check fuses and possibly make any adjustments. The fuse locations may be in different locations for different models. It should be noted that the Main SMPS PWBAs that are found in the PD-42V475, PD-42X776, and PD-42X795 are component level repair items. Fuses, at the minimum should be replaced when trouble shooting these items.
78

If the fuses are good and the output voltages are no good disconnect the X-Main, Y-Main, and Address Buffer Output Connectors
Once the output cables are disconnected reapply power and recheck output voltages.
If voltages are good proceed to X and YMain Display Troubleshooting. If voltages are no good please replace SMPS and do all required Power Supply adjustments.
Y-Main, X-Main, and Address Buffer Output Locations For PD-42WX84

Please verify the proper connectors for the model you are repairing as they may be different. DO NOT APPLY POWER UNLESS THESE OUTPUTS ARE ALL DISCONNECTED. OTHERWISE ADDITIONAL DAMAGE MAY OCCUR.
79
Page 79 notes.
Here are the general locations for the connectors that supply power to the Y-Main, X-Main, and Address Buffer PWBAs. These must all be disconnected with the power disconnected to test the output of the Main SMPS in an unloaded state. In this picture both CN8005 and CN8006 provide Address Buffer power. One is for the upper row and one is for the lower row because this particular pdp panel is capable of XVGA/WXGA resolution. A WVGA panel will have only one Address Buffer power output since only the bottom of the panel will have Address Buffer PWBAs. Again the exception to this is the PD-42X776 which is XVGA with only one row of address buffers.
80
No Display/Abnormal Display Trouble Shooting, Y-Main

Y-Main
Check Y-Main Fuses for proper DC voltage
Open Replace Y-Main
OK Check FETS for shorts OK Y-Main normal Check X-Main Short Replace Y-Main
81
Page 81 notes.
Now that the it has been confirmed that the Main SMPS PWBA is operating properly the technician can begin to trouble shoot the Y-Main (Scan) PWBA. The first step is to check the fuses located on the Y-Main PWBA. If there are any open fuse please replace the Y-Main PWBA. If the fuses are good, the FETS should be checked. There are numerous FETs on each Y-Main PWBA all of which can be located by the labels printed on the boards themselves. None should show a short when checked with a DVM. If any show a short the entire board should be replaced. It should be mentioned that there are also many diodes on each Y-Main board which look very much like the FETs. These are also labeled on the circuit board and will show a short when checked. A defection Y-Main may have random irregular spots through out the picture. A defective Y-Buffer PWBA may damage the Y-Main PWBA.
82
Please check that all fuses on the Y-Main board are good. Y-Main Fuses
If any fuses have failed please replace the board.
PD-42V475 Y-Main fuse locations. Please

verify the Y-Main fuse locations for the PDP you are working, they may be different.
83
Page 83 notes.
This is the general location of the fuses on the Y-Main PWBA. Different plasma models have different Y-Main PWBAs so it should be determined where the fuses are on the board the tech is currently inspecting. If any fuses are found to be open please replace the board.
84

Inspect transistors/FETs for physical damage. If any are damaged replace the board.
Check for any shorted FETs on the Y-Main PWBAs. Y-Main FETs
If any FETs/Transistors are shorted replace the board.
Y-Main FET location for PD-42V475. Please

verify the Y-Main FET locations for the PDP you are working, they may be different.
85
Page 85 notes.
Here are the general locations of the FETs on a Y-Main PWBA. Again different plasma models will have a different configuration so the location of the FETs will have to be determined on a case by case basis. These should all be checked for shorts and physical damaged. If any are shorted or damaged the board will require replacement. Keep in mind that many of the diodes look like FETs. Please determine which are which by reading the labels on the PWBA.
86
Y-Main Measurement
OUT4
GND
(Base Chassis)
Probe
(Port 2)
DC Voltage Range : 50~100V Setting
87
Page 87 notes.
In order to measure the Y-main output, connect the scope as shown in the picture. The signal is approximately 400V p-p. In order to avoid damage to your test equipment, choose correct settings on the scope before connecting to the unit. To insure a valid ground, scope ground should be attached to the metal portion of the chassis. The wave form might not trigger. Use the trigger location and setup shown in the next slide.
88
Y-Main Measurement Trigger
V_TOGG
GND1
Probe
(Port 1)
GND
Logic Main
DC Voltage Range : 5V under Setting
Trigger point is adjusted to Riging time
89
Page 89 notes.
The trigger test point is on the logic main PWB. V_TOGG is the designation for the trigger pin. Use scope ground as indicated. Obviously, to get to this test point on the Logic Main board, the JVC portion of the display unit must be removed or carefully relocated.
90
Y-Main Waveform and block

Vset Vsc_h 1 1 Vs Ysc_h Yset Panel Ys RAMP 2
To Panel
Yr 2
YDCL 1 2
GND
Ysc_l Ypp Ypn R5124 1k Vs Ysc Yfr 2 RAMP RAMP Yer Yg
bead 1 YDr 2 bead 1
YDCH 1
YDf 2
GND
Yf
GND
R5118 R5117
Vsc
Vset
This is the general shape of the waveform from the Y-Main output.
Note: The waveform will vary depending on model number or board/pdp versions.
- 70V
Vs Vsch
91
Page 91 notes. This is a block diagram representative of the operation of the Y-Main board. Y-Main output is a complex wave form used to drive the PDP cells. The signal flow in the block diagram is from right to left. DC voltages are switched on and off at different timings to generate this wave form. Each FET is switched to add certain voltages. For example YS FET switches and raises the waveform to YS. (Refer to the waveform). The final output with different voltage levels at periodic times are then output to the plasma cells for turning them on and off according to the inputted video. An example trouble shooting tip: When measuring the wave form, if you find the highest spike (Vset) is absent. This means that either Vset voltage is missing or Vset switching is not occurring. If the power supply outputs Vset to the Y-main, replace the Y-main. The waveforms in the handout are taken by a digital scope. Obviously, the waveform will vary widely when using an analog scope. With careful interpretation of a good units waveform, you should be able to determine if another is good or bad. Note: The level equipment used to obtain this waveform may not be available in every shop. Note: This procedure can be used as a quick check to verify that the Y-Main is operating properly if it has been determined that the Main SMPS supply voltages are all good. 92
No Display/Abnormal Display Trouble Shooting, X-Main

X-Main
Check X-Main Fuses for proper DC voltage
Open Replace X-Main
OK Check FETS for shorts OK X-Main normal Check Logic Main Short Replace X-Main
93
Page 93 notes.
The procedure for the X-Main (Sustain) PWBA is nearly identical to the Y-Main PWBA. The first step is to check the fuses located on the X-Main (Sustain) PWBA. Depending on the procedures any open fuses may need to be replaced, otherwise board should be replaced. If the fuses are good, the FETS should be checked. There are numerous FETs on each X-Main PWBA all of which can be located by the labels printed on the boards themselves. None should show a short when checked with a DVM. If any show a short the entire board should be replaced. It should be mentioned that there are also many diodes on each X-Main board which look very much like the FETs. These are also labeled on the circuit board and show a short when checked. The symptoms of a defective X-Main may appear that the previous picture does not get erased. (lag?)
94

Please check that all fuses are good on the X-Main PWBA.
X-Main Fuses
If any fuses are open please replace the X-Main board.
PD-42V475 X-Main fuse locations. Please

verify the X-Main fuse locations for the PDP you are working, they may be different.
95
Page 95 notes.
This is the general location of the fuses on the X-Main PWBA. Different plasma models have different X-Main PWBAs so it should be determined where the fuses are on the board the tech is currently inspecting. If any fuses are found to be open please replace the board.
96

Inspect transistors/FETs for physical damage. If any are damaged replace the board.
Check for any shorted FETs on the X-Main PWBAs.
X-Main FETs
If any FETs/Transistors are shorted replace the board.
X-Main FET location for PD-42V475. Please

verify the X-Main FET locations for the PDP you are working, they may be different.
97
Page 97 notes.
Here are the general locations of the FETs on a X-Main PWBA. Again, different plasma models will have a different configuration so the location of the FETs will have to be determined a case by case basis. These should all be checked for shorts and physical damaged. If any are shorted or damaged the board will require replacement. Keep in mind that many of the diodes look like FETs. Please determine which are which by reading the labels on the PWBA.
98
X-Main Measurement
This is the X-Main output waveform.
99
Page 99 notes.
This slide is a picture of the X-Main output wavesshape. It was taken with a 400Mhz Digital Scope. Do not expect this result with an analog scope. This check can be used to ensure that the X-Main is operating properly after it has been determined that the Main SMPS out voltages are all good.
100
X-Main Measurement
The X-Main waveform can be checked at any pin on any of these three connectors.
101
Page 101 notes.
The X-Main (Sustain) wave form may be checked at any of the pins on any one of the three connectors. All of these pins are in parallel due to the current requirement of the scan electrode of the pdp panel.
102
Address, Buffer, and Logic PWBA Troubleshooting Procedure

1. Identify nature of the problem. a. Vertical b. Horizontal c. PDP 2. If vertical or horizontal, please replace appropriate address, Y buffer, or possibly the Logic Main pwba and check if problem is corrected. 3. If problem is not corrected please replace the PDP.
103
Page 103 notes. Once it has been determined that the Main SMPS, XMain, and Y-Main are operating properly the technician can usually diagnose the problem by just looking at the picture on the plasma set. With the exception of a no picture problem the panel will usually have a horizontal or vertical line or block in the picture at this point. This leaves the diagnoses in many cases to swapping out a few pwbas to determine if it is a problem with an individual board or with the panel itself. Since the Logic Main PWBA communicates to the Address Buffers via a 8bit bus a failure of the Logic Main or an associated FFC would cause multiple vertical lines through that section of the pdp or a loss of picture all together in that section of the pdp. This should hold true for any Y-Main communication also.
104

Y Buffer PWBAs
Logic Main PWBA
Address PWBAs
Buffer and Address PWBAs from PD-42V475. Please

note that your pdp may differ as it may include upper address pwbas as well.
105
Page 105 notes.
This a picture of the locations of the Y Buffers, Address Buffers, and the Logic Main in a WVGA panel. Note the single row of Address Buffers on the lower edge of the panel. The PD-42X776 will also look like this although it is a XVGA panel.
106
Upper Address PWBAs
Y Buffer PWBAs
Logic Main
Lower Address PWBAs
Buffer and Address PWBAs from PD42WX84. Please note that your pdp may differ as it may include upper address pwbas as well.
107
Page 107 notes.
This a picture of the locations of the Y Buffers, Address Buffers, and the Logic Main in a XVGA/WXGA panel. Note the upper and lower row of Address Buffers on the lower and upper edges of the panel.
108
No Display/Abnormal Display Trouble Shooting, Logic Main
Logic Main Does the LED Blink?
Blinks at a regular interval and there is no display
Blinks at a regular interval and the display is abnormal.
Does not blink with no display or blinks abnormally with abnormal display.
OK Logic Main is normal.
OK Logic Main is normal. NG Replace Logic Main Replace PDP Note: This procedure is in reference to internal sync
mode only.
109
Page 109 notes.
This is a step that could be accomplished at nearly anytime in the trouble shooting process. From the flowchart we can see that if the led on the Logic Main PWBA is blinking at regular interval the board main is good. If the led does not blink or blinks abnormally then the board is defective. Of course since this circuit board produces all the data that is used to create the picture on the screen the all of the FFCs should be checked to verify that they are connected and not broken. This board should also be considered a board to swap in order to verify that a problem does not exist in the original since this board can produce problems that may appear like defects in other pwbas or the panel itself. Since the Logic Main PWBA communicates to the Address Buffers via a 8bit bus a failure of the Logic Main or an associated FFC would cause multiple vertical lines through that section of the pdp or a loss of picture all together in that section of the pdp.
110
Location of Logic PWBA
111
Page 111 notes.
The Logic Main PWBA can be found in this location in nearly all of the plasma models.
112

This LED should blink at a regular interval when the power is on, whether the panel is in internal or external sync mode.
Note: This Logic PWBA is from the PD-42V475, the logic board on the pdp you have may be different.
113
Page 113 notes.
Here is the location of the LED. Since this is only one example of a Logic Main pwba it may be located in a different location on different models.
114
Y-Main Buffer 0pen (Some horizontal lines dont exist) Y-Main Buffer Short (Some horizontal lines appear to be linked)
Y-Main Buffer Open/Short
Replace the PDP NG Change the appropriate buffer and recheck status
OK
Defect was caused by the buffer
115
Page 115 notes.
In this picture we can see that there is a thin horizontal line missing in the picture. The things we do know immediately with out even opening the cabinet is that the Main SMPS, XMain, Y-Main, and anything that could possible generate a part of the picture that is vertical in nature (Address Buffers) is good. The first step would be to replace the Y Buffer that would drive this part of the screen to determine if that is the defective part. If that was not the problem then the pdp would be replaced. The Y-Buffers Y Electrode connection may be temporarily disconnected to check if that particular buffer is causing a problem. 1. With the AC disconnected remove the suspect connection. 2. Power the unit on and check the picture for any change. 3. The unit should not be left on for no more than 5 seconds in this state. Damage may occur to good Y Buffer PWBA otherwise.
116
Upper Y Buffer
Lower Y Buffer
Y Electrode FFC
117
Page 117 notes.
Here is another picture of the location of the upper and lower Y Buffers.
118
If this buffer were to fail it would create a thick horizontal bar across the screen.
A thin horizontal line may also be present with a failure like this.
Note: This symptom may also be caused by a defective PDP.
119
Page 119 notes.
Here we can get an idea of what type of symptom that a failed Y Buffer will produce. It will always be horizontal in nature and may either be a thick bar or just a thin line.
120
If the picture has a black bar like this, this Y Buffer would be defective, and this pwba would be replaced.
A thin horizontal line could also be present with a failure like this.
Note: This symptom may also be caused by a defective PDP.
121
Page 121 notes.
This picture demonstrates how to determine which Y-Buffer to replace in the event that a horizontal line is present in the picture. One only needs to determine if the problem is in the upper or lower portion of the screen in order to know which Y Buffer to replace. There is always the possibility that the pdp is defective in a case like this.
122
Example of YMain buffer or PDP failure.
123
Page 123 notes.
Here is an example of what a real horizontal type failure looks like. If it was a Y Buffer it would have been the upper Y Buffer. In this case though it was determined to be the pdp after a replacement upper Y Buffer did not solve the problem.
124
125
Page 125 notes.
This is a larger sized picture from page 56. This is either a problem with the lower Y Buffer or the pdp.
126
Failed upper and lower YMain Buffers or most likely a failed Xmain.
127
Page 127 notes.
It was explained in the report that was submitted for this pdp that both upper and lower Y Buffers had failed in this Plasma TV creating this type picture. (Poor antenna signal?) Most likely a failed X-Main. Note: picture most likely looks like this due to a poor antenna signal.
128
Address Buffer 0pen (Some vertical lines dont exist) Address Buffer Short (Some vertical lines appear to be linked)
Identify the failure
1 line or 1 block Yes Replace Address Buffer NG Replace the PDP
No
Half of screen
OK Done Yes Replace the Logic Main/Applicable Address Buffer/FFC OK Done
NG
129
Page 129 notes.
With a problem that is vertical in nature the tech must determine if the line is considered 1 line, 1 block, or half the screen. In most cases an Address Buffer will be changed first to verify that the Address Buffer is not the problem, otherwise the pdp will need to be changed. Since the Logic Main PWBA communicates to the Address Buffers via a 8bit bus a failure of the Logic Main or an associated FFC would cause multiple vertical lines through that section of the pdp or a loss of picture all together in that section of the pdp.
130
This type of failure may look like a thick vertical bar or a thin vertical line. Please replace the appropriate vertical address pwba and check if the problem has been solved.
Address buffer pwbas. Note: WVGA Panel 852x480 or PD-42X776 (XVGA, 1024 x 768) Note: A failure of this nature usually requires the pdp to be replaced due to a chip on film/tape carrier package vertical driver failure. 131
Page 131 notes.
In this slide we can see how each Address Buffer and Address electrode will affect the picture. With this type of problem first replace the appropriate Address Buffer to see if the problem is corrected. If the problem is not corrected the pdp will need replacement in most cases.
132
This type of failure may look like a thick vertical bar or thin line that extends half way through the picture. Please replace the appropriate vertical address pwba and check if the problem has been solved. In this case this address pwba would be changed.
Note: XVGA/WXGA 1024x768 or 1365x768 Note: A failure of this nature may require the pdp to be replaced due to a chip on film/tape carrier package vertical driver failure. 133
Page 133 notes.
This slide is the same as the previous with the exception of the higher resolution panel. The Address Buffers are not only on the bottom but also on the top. When a problem occurs on a panel like this the vertical line will be on only the upper or lower half of the screen.
134
These would be located in this location under the aluminum bar. If one of these fail the pdp must be replaced.
135
Page 135 notes.
Here are parts that are located under the aluminum bar in the red circle above. These drive the Address Electrodes and if they fail the pdp will need replacement. When units with the COF package have failure with the one of these a burn mark can usually be found on the COF IC in direct relationship of where the vertical line or bar is in the picture. The pictures here are for reference only. If one of these packages fail they cannot be replaced individually so the entire pdp must be replaced.
136
137
Page 137 notes.
Here is an example of either a lower Address Buffer or pdp failure on a XVA/WXGA screen (except the PD-42X776).
138
139
Page 139 notes.
Here is an example of either an upper Address Buffer or pdp failure on a XVGA/WXGA screen (except the PD-42X776).
140
141
Page 141 notes.
Here is an example of either an Address Buffer or pdp failure on a WVGA screen or the PD-42X776 (XVGA).
142
143
Page 143 notes.
This is an example of a failure on a WVGA screen with multiple thin vertical lines. In this case it could be multiple Address Buffers but most likely the pdp itself. PD-42X776 (XVGA) also.
144
Miscellaneous PDP Failures
145
Page 145 notes.
146
PDP Failure Causing Picture Distortion
147
Page 147 notes.
This is an example of a pdp failure causing picture distortion. Note: No antenna signal causing fuzzy white picture.
148
149
Page 149 notes.
This is an example of a pdp failure causing picture distortion.
Note: No antenna signal causing fuzzy white picture.
150
151
Page 151 notes.
Here is an example of a pdp failure that will look like solarization or a possible defective bit in a 8 bit digital video bus. With this type of particular problem it would be a good idea to change the Logic Main PWBA in order to rule out a failure there. Possibly the A/V/Tuner section also (this course did not cover).
152
Possible Logic Board Or PDP Failure
153
Page 153 notes.
This is a failure of either the Logic Main or the pdp. The included report did not specify either way.
154
PDP Vertical Failure
155
Page 155 notes.
This particular failure was with the pdp. It could have been one of the lower Address Buffers as well. XVGA/WXGA screen (except PD-42X776).
156
157
Page 157 notes.
Another pdp failure on a WVGA or PD-42X776 (XVGA) screen. This could also be an Address Buffer failure. Note: Poor antenna signal causing fuzzy black and white picture.
158
159
Page 159 notes.
Another type of pdp vertical failure.
160
161
Page 161 notes.
Another single vertical line failure.
162
PDP Complete Failure
163
Page 163 notes.
This is a pdp that has completely failed. It has no picture despite all the circuit boards being good. Note: The image you see on the pdp screen is the reflection of the person taking the picture.
164
Board and PDP Replacement Information
165
Page 165 notes.
Important board and pdp replacement information. This is in addition to any previous service precautions.
166
Power Supply Adjustment Information
Power Supply Adjustment Procedure for GM-V42UG, PD-42WV74, and PD-42WX84 167
Page 167 notes.
If the Main SMPS or the pdp are replaced on the GM-V42UG, PD-42WV74, or the PD-42WX84 these adjustments must be done. Damage can occur to the pdp if these adjustments are not completed. Once the technician is familiar with the approximate positions of the test points and potentiometers these adjustments will take no more than 5 minutes.
168
Power Supply Adjustment Procedure for PD-42V475S, PD42X776, PD-42X795 169
Page 169 notes.
These particular models have the newer style power supply which require a slightly different adjustment routine. The adjustment instructions contain several cautions against touching the heat sinks and disconnecting the Y-Main, X-Main, Address Buffers, and the Logic Main PWBAs power connections prior to adjustment.
170
Power Supply Adjustment Procedure for PD-42V475S, PD42X776, PD-42X795 171
Page 171 notes.
There is also a method that is needed to turn the power supply on since the Logic Main PWBA is not connected. According to Fig 2 a 3.3 to 5VDC source needs to be connected in series with a 1k ohm resistor between pins 12 and 9 in order to turn the supply on. The dc source can be accomplished by using three 1.5V cells in series (it is a low current circuit).
172
PD-42V475 Main SMPS output connectors
173
Page 173 notes.
These are the pin outs for the PD-42V475 Main SMPS connectors that are the primary concern for most trouble shooting. These will also apply to the PD-42X776 and PD-42X795 models.
174
PD-42V475 Main SMPS output connectors
175
Page 175 notes.
These are the pin outs for the PD-42V475 Main SMPS connectors that are the primary concern for most trouble shooting. These will also apply to the PD-42X776 and PD-42X795 models. The PD-42X795 will also have a connector for the F-Buffer since it is a XVGA resolution screen and will have an upper row of Address Buffer PWBAs.
176
Power Supply Adjustment Procedure for GM-X50U 177
Page 177 notes.
Here are the adjustments that need to be performed done after the Main SMPS is replaced in the GM-X50U. Upon closer inspection of the manual it was discovered that there is also a Sub Main SMPS that needs to be adjusted as well when it is replaced. This applies as well to the PD-50X795 and will be covered a little later.
178
Power Supply Adjustment Procedure for PD-50X795 179
Page 179 notes.
These are the adjustments for the PD-50X795. The adjustments themselves are identical to the GM-X50U and include a few more details and warnings.
180
Power Supply Adjustment Procedure for PD-50X795 181
Page 181 notes.
This is the continuation of the previous slide.
182
DC/DC board adjustment procedure for GM-X50U and PD-X50795 183
Page 183 notes.
These are the adjustments for the Sub Main SMPS which are not included in the service manual for the GM-X50U and PD-X50795. This picture shows the locations of the potentiometers and the connectors where the checks and adjustments will be made.
184
Page 185 notes.
Here is the Voltage Identification Label from the pdp itself, notice that the label does not identify most of the required voltages.
186
Page 187 notes.
These are the instructions which explain where the voltages should be checked. For these adjustments it is recommended that to use the suggested grounds for the adjustments.
188
Page 189 notes.
This is the continuation.
190
Y-Main and Logic Main Board Replacement Information
Note: This information applies to all plasma models. 191
Page 191 notes.
This TT was issued for the models seen above but pertains to all plasma models. Also see page 15. If ROMs are defective from old Logic Main PWBA all applicable adjustments will need to be performed.
192
193
Page 193 notes.
This picture displays the location of the ROMs that need to be swapped from the old board to the new board when replacing the Logic Main PWBA. This particular board is from a PD-42WX84 model. Also see page 15.
194
195
Page 195 notes.
This picture displays the location of the ROMs that need to be swapped from the old board to the new board when replacing the Logic Main PWBA. This particular board is from a PD-42V475 model. Also see page 15.
196
197
Page 197 notes.
As noted previously when replacing a Y-Main circuit board the potentiometers on the new board should adjusted to the same physical position of the potentiometers on the old board. Also see page 15.
198
Resetting DVI/HMDI Modules

1. Separate modules, HDMI or DVI. See TT-04100701-T(R) on ISEE. 2. Early version of combined HDMI/DVI module. Place unit into Self Diagnostic Mode and transmit 03-6C with service jig/remote. 3. Improved version of HDMI/DVI module. Place unit into Self Diagnostic
Mode and then turn the power off.
199
Page 199 notes.
If the unit happens to be powered up and the proper precautions have not been taken for the DVI/HMDI module these are the methods in which to bring the module back to proper operating condition. Most modules encountered will be the type that numbers 1 and 3 will remedy. The number 2 type was very limited in production but may be encountered.
200
PD-42WV74 Board Compatibility
201
Page 201 notes.
The numbers over the circuit boards in the picture correspond to the item numbers in the chart below. The JVC input filter, signal, and audio boards have been removed to show the panel board locations. The three types of displays are listed across the top of the replacement chart. QLE0023-001 and 002 are the COF type. The 003 is TCP type. The part numbers and interchangeability are listed here. As an example, item number 1, the SMPS board, replacement from older to newer versions only is allowed. Item number 2 has full interchangeability from old to new and visa versa. For the items marked NG, there is no interchangeability. These boards available on individual order are CORE units. If a board is replaced, the new board will come with return instructions and paperwork, and a return label. Return the defective unit promptly. This will avoid problems with your parts account and credit status. The same applies is you have the need to replace the plasma display panel. This will also apply to the GM-V42UG.
202

JVC Plasma Troubleshooting Manual

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PDP Troubleshooting

PD-42WV74 GM-X50U PD-42X776 PD-42X795

PD-42WX84 GM-V42UG PD-42V475/485 PD-50X795

Plasma Basics: Pixel

Display electrodes are Horizontal and address electrodes are vertical

Plasma Basic: Panel

Plasma Basics: Electrodes

Plasma Basics: Overall

Plasma Basics: The Image

1TV field (time)

Plasma Basics: The Image

Plasma Basics: The Image

Plasma Basics: The Image

M em ory C ont l roler

To Address (Logic) Buffers 19

Plasma Basics: Panel Overview

Power Outputs from SMPS

Plasma Basics: Board Functions

This caution applies to the PD42X475.

Panel troubleshooting without CPU.

1. Remove the shield cover

2. Remove the bracket

3. Remove the Speaker connector

4. Carefully raise the Video process Assembly

Logic Main Dip Switches

Panel troubleshooting without CPU.

Panel troubleshooting without CPU.

Panel troubleshooting without CPU.

Panel troubleshooting without CPU.

Panel troubleshooting without CPU.

Panel troubleshooting without CPU.

Apply power to the AC input

Panel troubleshooting without CPU.

Panel troubleshooting without CPU.

New style PS with large aluminum heat sink plate.

Panel troubleshooting without CPU.

PDP Trouble Shooting Basic Flow Chart

Abnormal Display Sustain Open or Short Address Open or Short

No Voltage Output Troubleshooting

Test at 2pin ac input connector

NG Check Line Filter Fuse, Replace As Required

Check SMPS Fuses

NG Replace SMPS and Check X/Y-Main in advance

No Voltage Output Troubleshooting

No Voltage Output Troubleshooting

Check the Line Filter PWBA Fuse

No Voltage Output Troubleshooting

Check SMPS Output Voltages

OK Continue to No Display Troubleshooting

Power Supply Trouble Shooting

Verify SMPS Output Voltages

Voltage Specification Label On PDP

Typically Found In These Locations

Power Supply Trouble Shooting

If fuses are NG please replace the SMPS board.

PD-42V475 Power Supply Fuse Location

Power Supply Trouble Shooting

Y-Main, X-Main, and Address Buffer Output Locations For PD-42WX84

No Display/Abnormal Display Trouble Shooting, Y-Main

Check Y-Main Fuses for proper DC voltage

Open Replace Y-Main

No Display/Abnormal Display Trouble Shooting, Y-Main

If any fuses have failed please replace the board.