FPGA

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturinghence "field-programmable". FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together"somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. In addition to digital functions, some FPGAs have analog features

SPARTAN 3E (XC3S500E) FPGA

Overview of Features and Layout

The Spartan-3E FPGA is embedded with the 90nm technology at theheart of its architecture. This reduces the die size and cost, increasesmanufacturing efficiency, and addresses a wider range of applications. Youcan integrate embedded processing, digital signal processing (DSP), andconnectivity capabilities into Spartan-3E devices at no extra cost. These are supported with customized tools (ISE and EDK), JTAG probes, IP cores,design services, and training. The Spartan-3E diagram shown in Figure 2.3allows users to easily migrate to different densities across multiple packagesand supports 18 different single-ended and differential I/O standards.

Figure 1: Programmable Logic Block Of An FPGA

Figure 2: Spartan 3E Layout

The main advantages are High Speed Connectivity, High Performance Solutions and Lowest Cost Embedded Processing Solutions. 1. High Speed Connectivity System connectivity consists of physical parallel I/O interfaces and the protocols required for higher bandwidth. The Spartan-3E device I/O pins support full functionality for fast, flexible electrical interfaces. The PCI- Express slots are 100 MHz compatible. Also there are 18 I/O standards, DDR I/O registers, DCMs. 2. High Performance DSP Solutions Spartan-3E FPGAs help you efficiently build DSP solutions that handle. Up to 9.1 billion multiply and accumulates (MACs) per second. There are up to 36, 18x18 embedded multipliers for implementing compact DSP structures such as MAC engines, and adaptive and fully parallel FIR filters. The Block RAM can be used for storing partial products and coefficients. 3. Lowest Cost Embedded Processing Solutions The effective fractional cost of incorporating the MicroBlaze (32-bit soft processor) into a Spartan3E FPGA is very less. The Xilinx MicroBlaze with Spartan-3E FPGA (Figure 2.4) can be used to integrate the entire processing engine, all control functions, and additional supporting logic into a single cost-effective platform. The Embedded Development Kit (EDK) offers a common development environment for Spartan Series FPGAs with MicroBlaze.

Figure 3:Spartan 3E Starter Kit

The FPGA implementation is divided into blocks, each block implementing a separate portion of the algorithm. This approach allowed for concurrent development and for testing of individual blocks. The inbuilt finite state machine (FSM) controls each block. In addition, a high-level FSM controls the interaction of the blocks. Each computational block is implemented in C and checked for proper functionality with simulators (ISE Simulator).

Xilinx-ISE
Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of HDL designs, which enables the developer to synthesize ("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. The Web Edition is a free version of Xilinx ISE that can be downloaded at no charge. This edition provides synthesis and programming for a limited number of Xilinx devices. In particular devices with a large number of I/O pins and large gate matrices are disabled. The low-cost Spartan family of FPGAs is fully supported by this edition, as well as the family of CPLDs, meaning small developers and educational institutions have no overheads from the cost of development software. License registration is required to use the Web Edition of Xilinx ISE, which is free and can be renewed an unlimited number of times. The 13.4 version released in 2012-01-18 and the GNU/Linux version has a size of 5.8 GB.

Supported chips

Figure 4 : ISE Design suite device support

Design Flow Overview

The following steps are involved in the realization of a digital system using Xilinx FPGAs, as illustrated by the following figure.

Figure 5:Overview of the various steps involved in the design flow of a digital system

Design Entry

The first step is to enter y our design. This can be done by creating Source files. Source files can be created in different formats such as a schematic, or a Hardware Description Language (HDL) such as VHDL, Verilog or ABEL. A project design will consist of a top-level source file and various lower-level source files. Any of these files can be either a schematic or a HDL file.

Design Synthesis

The synthesis step creates netlist files from the various source files. The netlist files can serve as input to the implementation module.

Design Verification (simulation)

This is an important step that should be done at various stages of the design. The simulator is used to verify the functionality of a design (functional simulation), the behavior and the timing (timing simulation) of your circuit. Timing simulation is run after implementing your circuit in the FPGA since

it needs to know the actual placement and routing to find out the exact speed and timing of the circuit. Design Implementation

After generating the netlist file (synthesis step), the implementation will convert the logic design into a physical file that can be downloaded on the target device (e.g. Virtex FPGA). This steps involves three sub-steps: Translating the netlist, Mapping and Place&Route.

Device Configuration

This refers to the actual programming of the target FPGA by downloading the programming file to the Xilinx FPGA.

Project Navigator Window

The above steps are managed through a central ISE Project Navigator window, shown below.

Figure 6 :ISE Project Navigator Window (Screen clip from Xilinx (TM) ISE software)

Sources Window
This window contains the design source files for a project. These are the source files that you created or added to the project (see later on). A drop down list at the top of sources window allows you to select source files that are associated with a particular design aspect such as Synthesis/Implementation or Simulation.

Processes Window
The processes windows list the available processes (corresponding to the process selected in the processes window). Typically you will select a particular process that you want to perform on the selected source file. This can include a simulation, implementation, etc. To run a process you can double click on the process. When a process has been successfully executed a red tick-off icon appears. When you run a high-level process, the Project Navigator will automatically run all the associated lower-level processes.