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INTRODUCTIONTO VERILOGHDL

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OVERVIEW

VerilogwasadoptedasanofficialstandardasIEEEStandard1364 1995in1995. Anenhancedversion,calledVerilog2001,wasadoptedin2001as IEEEStandard13642001. Originallyintendedforsimulation,todayVerilogisdesignedto facilitatedescribedigitalhardwareforbothsimulationand synthesis. Verilogisagreatlowlevellanguage. StructuralmodelsareeasytodesignandBehavioralRTLcodeis prettygood.

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Thesyntaxisregularandeasytoremember.ItisthefastestHDL languagetolearnanduse. HoweverVeriloglacksuserdefineddatatypesandlacksthe interfaceobjectseparationoftheVHDL'sentityarchitecturemodel.

Verilogconstructs Entity declaration modulecircuit(a,b,C,D); inputa; outputb; input[3:0]C; output[0:7]D; endmodule

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Internalsignals, wireinta; variables, wire[3:0]intb; constants integer[7:0]counter; reg[0:7]temp; parameterC3b000; Component instantiation modulesystem1(); circuitU_comp(A,B); endmodule

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Concurrent signal assignment

assignDataout=Datain;

Sequentialblock always@(a) begin End

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Controlflow a) If b) ifelse

if(en==1)f=x1; if(sel==0) beginf=x1;g=x2;end else beginf=x2;g=x1;end case(y) 0:f<=stateA; 1:f<=stateB; default:f<=stateC; endcase

c) case

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BASICSOFVERILOG
Verilogdesignunit
modulemodule_name(ports); {parameterdeclarations} input<portlist>; //input/outputdeclarations: output<portlist>; wire<list>; //nets&variables: reg(orinteger)<list>; {assigncontinuousstatement;} //behaviourstatements: {initialblock;} {alwaysblocks;} {gateinstantiations;} {moduleinstantiations;} endmodule
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Verilogdescribesadigitalcircuitorsystemasasetofmodules. TheentityusedinVerilogdescriptionofhardwarecomponentsisa module Followingthemoduleheaderisadeclarativepart,wheremodule ports,netsandvariablesaredeclared. AportinVerilogmaybeinput,output,orinout.Portsprovidethe modulewithameanstoconnecttoothermodules. Netsaretypicallydeclaredbythekeywordwire,connection betweenhardwareelements. Aportisautomaticallydeclaredaswireifitisdefinedasinput, output,orinout. Variables,declaredasreg,areusedforbehaviouraldescriptions, andareverymuchlikevariablesinsoftwarelanguages.
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UsuallyeachlineofVerilogtextmustterminatewithasemicolon, oneexceptionofwhichistheterminatingendmodulekeyword. Verilogiscasesensitive.Itallowsletters,numbersandspecial character_tobeusedfornames. Names(oridentifiers)areusedformodules,parameters,ports, variables,andinstancesofmodules,andmustbeginwithletters. Keywordscannotbeusedfornames.

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modulecircuitA(Cin,x,y,X,Y,Cout,s,Bus,S); inputCin,x,y; input[3:0] X,Y; outputCout,s; output[3:0] S; inout [7:0] Bus; wire d; reg e; endmodule
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RepresentationofNumbersinVerilog

Verilogusesa4valuelogic,thatis,0,1,z,andx. Numberscanbegivenasbinary(b),octal(o),hex(h),ordecimal (d). <sizeinbits><radixidentifier><significantdigits>

E.g.,2217canberepresentedas12b100010101001,12h8A9,or 8d2217. Unsignednumbersaregivenwithoutspecifyingthesize,e.g. b1000100110orh116ord2217(willnotbezeropadded) Negativenumbers,e.g.if5isspecifiedas4b101,itwillbe interpretedasafourbit2scomplementof5,whichis1011.

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Thenumber12b100010101001maybewrittenas 12b1000_1010_1001toimprovereadabilityinthecode. AconstantusedinVerilogmaybegivenas8hz3,whichisthe sameas8bzzzz0011. 8hxdenotesanunknown8bitnumber.

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Fancytotry?

14'h1234 14'h1234 32'hDEAD_BEEF 32'hDEAD_BEEF

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OperatorsinVerilog Operator type Bitwise Logical Arithmetic Relational Equality Operator symbol ~,&,|,^,~^ !,&&,|| +,,*,/ >,<,>=,<= ==,!= ===,!== Shift >>,<< Concatenation {,} Conditional ?: Operation not,and,or,xor,xnor not,and,or add,sub,mult,divide Gt,Lt,Gtoreq,Ltoreq Logicalequality,logicalinequality, caseequality,caseinequality Rightshift,Leftshift

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ConsiderthatA,B,andCtobeoperands,eithervectorsorscalar(1 bit).

The bitwise operator produce the same number of bits as the operands.E.g,A=a1a0,B=b1b0,C=c1c0,thenA|Bresultsin c1=a1|b1andc0=a0|b0. Thelogicaloperatorgeneratesaonebitresult.Usedinconditional statements. o A||Bresultsin1unlessbothAandBarezeros o A&&Bwillproducearesultof1ifbothAandBarenonzeros. o !Agivesa1ifallitsbitsare0,otherwiseitresultsina1. Therelationaloperatoroutputsa1or0basedonthe(specified) comparisonofAandB. Theshiftoperatorsperformlogical1bitshiftstotherightorleft, withzerosshiftedin.
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In the case of the conditional operator, the operation A?B:C producearesultthatisequaltoBifAevaluatesto1,otherwisethe resultisC. The precedence of Verilog operators is similar to that found in arithmeticandBooleanalgebra.

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HDLMODELLINGOFDIGITALCIRCUITS

Different circuit complexities (e.g., simple modules to complete systems) require different kinds of specification or levels of abstraction. ThreemodellingstylesinHDLbaseddesignofdigitalsystems Structuralmodelling Dataflowmodelling Behaviouralmodelling

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Structural modelling using primitives and lowerlevel module instantiation. This modelling allows for the hierarchical modular design approach in design. It is used to describe a schematic or logicdiagram.Thefunctionalityofthedesignishiddeninsidethe components. Dataflowmodelling outputsignalsarespecifiedintermsofinput signal transformation. This style is similar to Boolean equations. This modelling style allows a digital system to be designed in termsofitsfunction. Behavioural modelling describes the function or expected behaviourofthedesigninanalgorithmicmanner.Thisstyleisthe closesttoanaturallanguagedescriptionofthecircuitfunctionality.

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DataflowModelling
modulefunc2(x1,x2,x3,f); input x1,x2,x3; outputf; assignf=(~x1&~x2&x3) |(x1&~x2&~x3) |(x1&~x2&x3) |(x1&x2&~x3); endmodule

func2 x1 x2 x3 Logic Function f

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Modellingoffulladderusingconcurrentstatements 1 modulefulladder(Cin,x,y,S,Cout); 2 input Cin,x,y; 3 outputS,Cout; 4 5 assignS=(x^y^Cin); 6 assignCout=(x&y)|(Cin&x)|(Cin&y); 7 endmodule

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NotesonConcurrent/Continuoussignalassignmentstatements InVerilog,concurrentassignmentstatementsarecalledcontinuous assignmentstatements. Lines5and6intheaboveVerilogcodearecontinuousassignment statements,bythefactthattheybeginwiththeassignkeyword. Theyareexecutedconcurrently,andthelineorderisnotimportant. Besidesconcurrentstatements,therearealsosequential(inVHDL jargon)orprocedural(inVerilogjargon)statements. Differing from concurrent statements, sequential statements are evaluatedintheorderinwhichtheyappearinthecode.

Verilogsyntaxrequirethemtobeinanalwaysblock.

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HDLdataflowdescriptionofahalfadder moduleHA(a,b,s,c); input a,b; outputs,c; assigns=a^b; assignc=a&b; endmodule

a HA s = a + b c = a . b b

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StructuralModelling
Modulardesignoffulladderusinghalfadders moduleFA(cin,a,b,sum,cout); input cin,a,b; outputsum,cout; wires1,s2,s3; HAu1(a,b,s1,s2); HAu2(s1,cin,sum,s3); assigncout=s2|s3; endmodule
cin FA HA a b a b u1 sum cout HA

s1 s2 s3

a b

u2

sum cout

sum

cout

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InVerilogstructuralmodelling,moduleinstantiationisused. Theinstantiationstatementassociatesthesignalsintheinstantiated module(HA,inthiscase)withtheportsofthedesignunit(FAin thiscase). Here, positional association is applied, where each signal in the instantiationstatementismappedbypositiontothecorresponding signalinthemodule.

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BehaviouralModelling

At higher levels of design abstraction, a digital module is often modelledbehaviourally, The function or operation of the module is described in an algorithmicmanner. The HDL code will contain statements that are executed sequentiallyinapredefinedorder(orprocedure). Theorderofthesequential(orprocedural)statementsintheHDL codeisimportantandmayaffectthesemanticsofthecode.

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BehaviouralModellinginVerilog

Behavioural modelling in Verilog uses constructs similar to C languageconstructs. Sequential statements, like ifelse and case statements, are called proceduralstatements. Procedural statements be contained inside a construct called an alwaysblock Analwaysblockexecutesequentiallyintheordertheyarelistedin thesourcecode. The@symboliscalledtheeventcontroloperator.Thepartafterthe @symbol,istheeventcontrolexpression,alsoreferredtoasthe sensitivitylist. Thisvariableholdsitsvalueuntilthenexttimeaneventoccurson inputsinthesensitivitylist.
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moduleVcircuit(A,B,z); input [3:0]A,B; outputz; regz; always@(AorB) begin z=0; if(A==B)z=1; end endmodule

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Verilog syntax requires any signal assigned a value inside an alwaysblockhastobeavariableoftypereg;hencezisdeclaredas reg. Since z depends on A and B, these signals are included in the sensitivitylist. Blocking assignments, denoted by = symbol is used. The assignment completes and updates its LHS before the next statementisevaluated. We will cover nonblocking assignment, denoted by <= symbol lateron.

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