AN221E04 Datasheet

AN221E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced I/O
www.anadigm.com
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Disclaimer
Anadigm reserves the right to make any changes without further notice to any products herein. Anadigm makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Anadigm assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including with out limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Anadigm does not in this document convey any license under its patent rights nor the rights of others. Anadigm software and associated products cannot be used except strictly in accordance with an Anadigm software license. The terms of the appropriate Anadigm software license shall prevail over the above terms to the extent of any inconsistency.
Anadigm, Inc. 2003 2012 All Rights Reserved.
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PRODUCT AND ARCHITECTURE OVERVIEW
The AN221E04 device consists of a 2x2 matrix of fully Configurable Analog Blocks (CABs), surrounded by a fabric of programmable interconnect resources. Configuration data is stored in a n on-chip SRAM configuration memory. Compared with the first-generation FPAAs, the Ana digmvortex architecture provides a significantly improved signal-to-noise ratio as w ell as higher bandwidth. These devices also ac commodate nonlinear functions such as sensor response line arization and arb itrary waveform synthesis. The AN221E04 device features an adva nced input/output structure that allows the FPAA to be programmed w ith up to six outputs or triple the number provided by the ANx20E04 devices. The AN221E04 devices have four confi gurable I/O cells and two dedicated output cells. For I/O-intensive applications, this means a single F PAA can now be used to process multiple channels of analog signals where two or more such devices were previously needed. In addition, the AN221E04 devices allow designers to implement an integrated 8-bit analog-to-digital converter on the FP AA, eliminating the potential need for an external converter. Using this new device, de signers can route the digital output of the A/D converter off-chip using one of the dedicated output cells.
Figure 1: Architectural overview of the AN221E04 device

With dynamic reconfigurability, the functionality of the AN221E04 can be reconfigured in-system by the designer or on-the-fly by a microprocessor. A single AN221E04 can thus be programmed to implement multiple analog functions and/or to adapt on-the-fly to maintain precision operation despite system degradation and aging.
PRODUCT FEATURES
Dynamic reconfiguration Four configurable I/O cells, two dedicated output cells 8-bit SAR analogtodigital converter Fully differential architecture Fully differential I/O buffering with options for single ended to differential conversion Low input offset through chopper stabilized amplifiers 256 Byte Look-Up Table (LUT) for linearization and arbitrary signal generation 4:1 Input multiplexer Typical Signal Bandwidth: DC-2MHz (Bandwidth is CAM dependent) Signal to Noise Ratio: o Broadband 80dB o Narrowband (audio) 100dB Total Harmonic Distortion (THD): 80dB DC offset <100V Package: 44-pin QFP (10x10x1.4mm) o Lead pitch 0.8mm Supply voltage: 5V Dynamically reconfigurable FPAA Sample Pack Dynamically reconfigurable FPAA Tray (96 pcs) Dynamically reconfigurable FPAA Tape & Reel (1000 pcs) AN221E04 Evaluation Kit AN221E04 Development Kit
APPLICATIONS
Real-time software control of analog system peripherals Intelligent sensors Adaptive filtering and control Adaptive DSP front-end Adaptive industrial control and automation Self-calibrating systems Compensation for aging of system components Dynamic recalibration of remote systems Ultra-low frequency signal conditioning Custom analog signal processing
ORDERING CODES
AN221E04-QFPSP AN221E04-QFPTY AN221E04-QFPTR AN221D04-EVAL AN221D04-DEVLP
[For more detailed information on the features of the AN221E04 device, please refer to the AN121E04/AN221E04 User Manual]
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AN221E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced I/O ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
DC Power Supplies xVDD to xVDD Offset Package Power Dissipation Analog and Digital Input Voltage Ambient Operating Temperature Storage Temperature
a
AVDD(2) BVDD DVDD Pmax 25C Pmax 85C Vinmax Top Tstg
Symbol
Min
-0.5 -0.5 Vss-0.5 -40 -65
Typ
-
Max
5.5 V 0.5
Unit
V V W V C C
Comment
AVSS, BVSS, DVSS and SVSS all held to 0.0 V a Ideally all supplies should be at the same voltage Still air, No heatsink, 4 layer board, 44 pins. ja = 55C/W
1.8 0.73 Vdd+0.5 85 150
Absolute Maximum DC Power Supply Rating - The failure mode is non- catastrophic for Vdd of up to 7 volts, but w ill cause reduced operating life time. The additional stress caused b y higher local electric fields within the CMOS circuitry may induce metal migration, oxide leakage and other time/quality related issues.
Recommended Operating Conditions

Parameter
DC Power Supplies
Symbol
AVDD(2) BVDD DVDD Vina Vind Tj
Min
4.75 VMR-1.9 0 -40
Typ
5.00 5.25 -
Max
Unit
V V V C
Comment
AVSS, BVSS, DVSS and SVSS all held to 0 V VMR is 2.0 volts above AVSS Assume a package ja = 55C/W b
Analog Input Voltage. Digital Input Voltage Junction Temp

b
VMR+1.9 DVDD 125
In order to calculate the junction temperature you must first emp irically determine the cur rent draw (total I dd) for the design. Once the current consumption established then the following formula can be used; Tj = Ta + Idd x Vdd x 55 C/W, where Ta is the ambient temperature. The worst case ja of 55 C/W assumes no air flow and no additional heatsink of any type.
General Digital I/O Characteristics (Vdd = 5v +/- 10%, -40 to 85 deg.C)

Parameter
Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Input Leakage Current Input Leakage Current Max. Capacitive Load Min. Resistive Load DCLK Frequency ACLK Frequency Clock Duty Cycle
Symbol
Vih Vil Vol Voh Iil Iil Cmax Rmin Fmax Fmax -
Min
0 70 0 80 10 45
Typ
12.0 -
Max
30 100 20 100 1.0 10 40 40 55
Unit
A A pF Kohm MHz MHz %
Comment
% of DVDD % of DVDD % of DVDD % of DVDD All pins except DCLK DCLK if a crystal is connected and the on-chip oscillator is used The maximum load for a digital output is 10 pF // 10 Kohm The maximum load for a digital output is 10 pF // 10 Kohm For MODE = 1, Max DCLK is 16 MHz Divide down to <8 MHz prior to use as a CAB clock All clocks
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Detailed Digital I/O Interface Characteristics: Vdd = 5.0volts LCCb
Parameter
Output Voltage Low Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source
Symbol
Vol Voh Cmax Rmin Isnkmax Isrcmax
Min
Vss 4.5 50 -
Typ
-
Max
150 Vdd 20 15 4
mV V pF Kohm mA mA
Unit
Load 20pF//50Kohm to Vss Load 20pF//50Kohm to Vss Maximum load 20 pF // 50 Kohm Maximum load 20 pF // 50 Kohm LCCb pin shorted to Vdd LCCb pin shorted to Vss
Comment
CFGFLG, ACTIVATE
Parameter
Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Output Voltage Low Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source External Resistive Pullup
Symbol
Vil Vih Vol Voh Vol Voh Cmax Rmin Isnkmax Isrcmax Rpullupext
Min
0 70 Vss 4.5 Vss 4.5 50 5
Typ
Max
30 100
Unit
% % mV V mV
Comment
% of DVDD % of DVDD Pin load = Internal pullup + 20pF//50K to Vss Pin load = Internal pullup + 20pF//50K to Vss Pin Load = External 5K ohm pullup + 20pF//50K to Vss Pin Load = External 5Kohm pullup + 20pF//50K to Vss Maximum load 50 pF // 50 Kohm Maximum load 50 pF // 50 Kohm Pin shorted to Vdd Pin shorted to Vss Use only if internal pullup is deselected
- 200 7.5
85 Vdd
Vdd 50 2.5 200 10
V pF Kohm mA A Kohm
ERRb
Parameter
Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source External Resistive Pullup
Symbol
Vil Vih Vol Voh Cmax Rmin Isnkmax Isrcmax Rpullupext
Min
0 70 Vss 4.9 50 10
Typ
10
Max
30 100 50 Vdd 50 10 0 10
Unit
% % mV V pF Kohm mA A Kohm
Comment
% of DVDD % of DVDD Maximum load 50 pF // 50 Kohm Maximum load 50 pF // 50 Kohm
DCLK,Mode,DIN,EXECUTE,PORb,CS1b,CS2b
Parameter
Input Voltage Low Input Voltage High
Symbol
Vil Vih
Min
0 70
Typ
-
Max
30 100
Unit
% %
Comment
% of DVDD % of DVDD
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OUTCLK/SPIMEM,DOUTCLK
Parameter
Output Voltage Low Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source
Symbol
Vol Voh Cmax Rmin Isnkmax Isrcmax
Min
0 80 10 -
Typ
-
Max
20 100 50 17 4
Unit
% % pF Kohm mA mA
Comment
% of DVDD % of DVDD Maximum load 50 pF // 50 Kohm Maximum load 50 pF // 50 Kohm
ACLK/SPIP
Parameter
Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Current Source
Symbol
Vil Vih Vol Voh Cmax Rmin Isnkmax Isrcmax
Min
0 70 0 80 10 -
Typ
-
Max
30 100 20 100 50 15 4
Unit
% % % % pF Kohm mA mA
Comment
% of DVDD % of DVDD % of DVDD % of DVDD Maximum load 50 pF // 50 Kohm Maximum load 50 pF // 50 Kohm
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Analog Inputs General
Parameter
High Precision Input Range c Standard precision Input Range d High Precision Differential Input c Standard Precision Differential Input d Common Mode Input Range Input Offset Input Frequency
Symbol
Vina Vina
Min
0.5 0.1 0 0 1.8 -
Typ
- 3.5 - 3.9
Max
Unit
V V
Comment
Vdiffina Vdiffina Vcm Vos
2.0 2.2 5
+/-3.0 +/-3.8
V V V
VMR +/- 1.5v VMR +/- 1.9v Common mode voltage = 2 V Common mode voltage = 2 V
15
mV
Fain
<2
MHz
Non-chopper stabilized input Max value is clock, CAM and input stage dependant. Input frequency is limited to approx <2MHz due to CAM signal processing which is based on sampled data architectures.
c. d.
High precision operating range provides optimal linearity and dynamic range. Standard precision operating range provides maximum dynamic range and reduced linearity.
Input Differential Amplifier ON and filter OFF

Parameter
Input Range Gain Setting Gain Accuracy Gain Drift (Temperature, Supply Voltage zand Time) Equivalent Input Offset Voltage
Symbol
Vina Vdiffina Ginamp Dist
Min
16 -
Typ
1.0 -
Max
128 2.5 1.0
Unit
Comment
Usable input range will be reduced by the effective gain setting
See analog input above % %
Vos Offset Voltage Temperature Coefficient Input Frequency c Input Frequency d Power Supply Rejection Ratio Common Mode Rejection Ratio Large Signal Harmonic Distortion Input Resistance Input Capacitance Input Referred Noise Figure
12
mV
Non-chopper stabilized input When the input amplifier and filter are used in combination Vos contribution comes only from the input amplifier from -40C to 125C
Voffsettc Fain Fain PSRR CMRR Dist Rin Cin NF
0 0 65 10 -
1 -2 <2 67 -65
10 8 5.0
V/C MHz MHz dB dB dB Mohm pF V/sqrtHz
d.c. Amp Gain =16 a.c. See graphs page 18 0.4v p-p Differential input at 660Hz Gain setting = 16 Input cell Gain = 16 Applies to audio frequency range (400Hz to 30KHz). See graphical data on page 18 Input signal = 285 mV p-p diff, audio frequency range See graphical data on page 18 Input signal = 100 mV p-p diff See graphical data on page 18
0.1 -
Signal-to Noise Ratio and Distortion Spurious Free Dynamic Range

c. d.
SINAD SFDR
75 73
dB dB
High precision operating range provides optimal linearity and dynamic range. Standard precision operating range provides maximum dynamic range and reduced linearity.
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Input Differential Chopper Amplifier on and filter OFF
Parameter
Input Range Gain Setting Gain Accuracy Gain Drift, (Temperature, Supply Voltage and Time) Chopper Frequency Clock Range
Symbol
Vina Vdiffina Ginamp
Min
16 -
Typ
1.0 -
Max
128 2.5 1.0 >250
Unit
Comment
Usable input range will be reduced by the effective gain setting
See analog input above
% % KHz Fc = master clock frequency Set Fch as slow as possible Fch > 250KHz will result in some signal attenuation Chopper stabilized amplifier The maximum value of 200V is guaranteed by production test This is a tester limitation from -40C to 125C d.c. a.c. See graphs on page 18 0.4v p-p Differential input at 660Hz Gain setting = 16 Fch=Chopper clock frequency The chopper frequency and input frequency should be chosen such that subsequent low pass filtering can remove the chopper stage frequency elements Input to filter or chopper Input cell Gain = 16 Applies to Audio frequency range Chopper clock Fch = 250KHz See graphical data on page 18 Input signal = 285 mV p-p differential, Audio frequency range See graphical data on page 18 Input signal =100 mV p-p differential See graphical data on page 18
Fch Equivalent Input Offset Voltage Vos Offset Voltage Temperature Coefficient Power Supply Rejection Ratio Common Mode Rejection Ratio Large Signal Harmonic Distortion Input Frequency Fain Voffsettc PSRR CMRR Dist
Fc/260100
65 -
<100 0.5 102 -40
200 2.0 -
V V/C dB dB dB
Fch/20
Fch/2
KHz
Input Resistance Input Capacitance Input Referred Noise Figure
Rin Cin NF
10 0.09
5.0 -
Mohm pF V/sqrtHz
Signal-to Noise Ratio and Distortion Spurious Free Dynamic Range
SINAD
75
dB
SFDR
74
dB
Input Differential Amplifier OFF and filter ON

Parameter
Input Range Equivalent Input Offset Offset Voltage Temperature Coefficient Input Frequency Fain -MHz
Symbol
Vina Vdiffina Vos Voffsettc
Min
Typ
Max
Unit
Comment
Non-chopper stabilized input, Filter corner frequency =470KHz from -40C to 125C I. measured at filter corner=470Khz II. maximum at Filter corner=76KHz Input filter frequency will define the maximum frequency Input filter is recommended to be >30x higher than the max input frequency, for 80dB distortion performance
8 0.05 I
32 1.0 II
mV mV/C
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Common Mode Rejection Ration Power Supply Rejection Ratio Large Signal Harmonic Distortion Input Low Pass Filter (Anti-Alias) Corner Frequency Settings Input Resistance Input Capacitance Input Referred Noise Figure Signal-To Noise Ratio and Distortion Spurious Free Dynamic Range CMRR PSRR Dist Ffiltcorner Rin Cin NF SINAD SFDR 68 76 10 60 -82 0.17 84 90 470 5.0 dB dB dB KHz Mohm pF V/sqrtHz dB dB Input to filter or chopper Input cell filter corner Fc = 470KHz Applies to Audio frequency range See graphical data on page 18 Input signal = 1400 mV p-p diff, Audio frequency range See graphical data on page 18 Input signal =1400 mV p-p differential See graphical data on page 18 d.c. a.c. See graphical data on page 19 4v p-p Differential input at 660Hz Filter corner frequency 470KHz
Input Differential Voltage mode, Amplifier OFF, Filter OFF and Unity Gain stage ON
Parameter
Input Range Equivalent Input Offset Offset Voltage Temperature Coefficient Input Frequency Power Supply Rejection Ratio Common Mode Rejection Ratio Large Signal Harmonic Distortion Large Signal Harmonic Distortion Input Resistance Input Capacitance Input Referred Noise Figure Signal-To Noise Ratio and Distortion Spurious Free Dynamic Range
Symbol
Vina Vdiffina Vos
Min
60 -
Typ
5 20 60 -80 -80 126 2.0 0.16 84 90
Max
15 50 1.0 5.0 -
Unit
V mV V/C MHz dB dB dB dB Kohm pF V/sqrtHz dB dB
Comment
Non-chopper stabilized input from -40C to 125C Gain Bandwidth limited by input impedance d.c. a.c. See graphs on page 18 4v p-p Differential input at 660Hz 3v p-p single ended signal at 660Hz Input to unity gain stage Applies to Audio frequency range See graphical data on page 18 Input signal = 1400 mV p-p diff, Audio frequency range See graphical data on page 18 Input signal =1400 mV p-p differential See graphical data on page 18
Voffsettc Fain PSRR CMRR Dist Dist Rin Cin NF SINAD SFDR
Input Differential Voltage mode, Amplifier OFF, Filter OFF and Unity Gain stage OFF
Parameter
Input Range Equivalent Input Offset Offset Voltage Temperature Coefficient Input Frequency Power Supply Rejection Ratio Large Signal Harmonic Distortion Input Resistance
Symbol
Vina Vdiffina Vos Voffsettc Fain PSRR Dist Rin
Min
N/A N/A N/A -
Typ
N/A N/A N/A -85 --
Max
N/A N/A 8 N/A -
Unit
V mV V/C MHz dB dB Mohm
Comment
See CAM Op Amp See CAM Op Amp. from -40C to 125C Dependant upon CAM See CAM Op Amp See CAM Op Amp Input to CAM directly (Input cell bypass mode). This variable is influenced by CAB capacitor size, CAB clock frequency and CAB architecture Input to CAM directly (Input cell bypass mode) This variable is influenced by CAB capacitor size, CAB clock frequency and CAB architecture
Input Capacitance Cin -pF
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Analog Outputs
(See Output Cell section in the AN12xE04/AN22xE04 user manual for more details)
Parameter
High Precision Output Range c Standard Precision Output Range d High Precision Differential Output c Standard precision Differential Output d Common Mode Voltage
c d
Symbol
Vouta Vouta Vdiffouta Vdiffouta Vcm
Min
0.5 0.1 1.9
Typ
- 3.5 - 3.9 2.0 2.1
Max
Unit
V V
Comment
VMR +/- 1.5v VMR +/- 1.9v Common mode voltage = 2 V Common mode voltage = 2 V
+/-3.0 +/-3.8
V V V
. High precision operating range provides optimal linearity and dynamic range. . Standard precision operating range provides maximum dynamic range and reduced linearity.
Output Voltage mode and filter ON, corner frequency 470KHz

Parameter
Input Range Equivalent Input Offset Offset Voltage Temperature Coefficient Output Frequency Faout MHz
Symbol
Vina Vdiffina Vos
Min
-
Typ
5 0.05 I
Max
15 1.0 II
Unit
V mV mV/C
Comment
Voffsettc
Power Supply Rejection Ratio Large Signal Harmonic Distortion Input Low Pass Filter (Anti-Alias) Corner Frequency Settings Output Load c e Output Load c e Output Load d e
PSRR Dist Ffiltcorner Rload Cload
60 76 0.1 -
-82 --
470 50
dB dB KHz Mohm pF
from -40C to 125C measured at filter corner: 470Khz II maximum at filter corner: 76KHz Output filter frequency will define the maximum frequency Input filter is recommended to be >30x higher then the max input frequency, for good distortion performance d.c. a.c. See graphical data on page 19 4v p-p Differential input at 660Hz Filter corner frequency 470KHz
I
Rload
10
Kohm
Output Load d e Common Mode Rejection Ratio Input Referred Noise Figure Signal-To Noise Ratio and Distortion Spurious Free Dynamic Range
c
Cload CMRR NF SINAD SFDR
56 0.22 82 90
100 -
pF dB V/sqrtHz dB dB
Additional loading causes internal voltage drops across output stage and series resistances The output stage has a small signal output impedance of approx 10ohm
Output filter corner fc = 470KHz Applies to Audio frequency range See graphical data on page 18 Input signal = 1400 mV p-p diff, Audio frequency range See graphical data on page 18 Input signal =1400 mV p-p diff See graphical data on page 18
. High precision operating range provides optimal linearity and dynamic range. . Standard precision operating range provides maximum dynamic range and reduced linearity. e . The maximum load for an analog output is 50 pF // 100 Kohms. This load maybe with respect to analog ground VMR or AVSS.
d
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Output Voltage mode and filter off (bypass mode)
Parameter
Input Range Equivalent Input Offset Offset Voltage Temperature Coefficient Output Frequency c e Output Frequency d f
Symbol
Vina Vdiffina Vos Voffsettc Faout Faout
Min
N/A N/A N/A N/A N/A
Typ
N/A N/A N/A -85 N/A N/A
Max
N/A N/A 4 8 N/A N/A N/A
Unit
V mV mV/C MHz MHz dB dB Mohm pF
Comment
See CAM Op Amp See CAM Op Amp The realizable output frequency is limited to approx <2MHz due to CAM signal processing which is based on sampled data architectures. See CAM Op Amp See CAM Op Amp See CAM Op Amp
Power Supply Rejection Ratio Large Signal Harmonic Distortion Output Load Output Load
c d e
. High precision operating range provides optimal linearity and dynamic range. . Standard precision operating range provides maximum dynamic range and reduced linearity. . The maximum load for an analog output is 50 pF // 100 Kohms. This load maybe with respect to analog ground VMR or AVSS. f . The maximum load for an analog output is 100 pF // 100 Kohms. This load must be differential and with respect to analog ground(VMR).
PSRR Dist Rload Cload
VMR (voltage Mid Rail) and VREF (Reference Voltage) Ratings

Parameter
VMR Output Voltage VREF+ Output Voltage VREF- Output Voltage Output Voltage Deviation VREF+, VMR, VREFVoltage Temperature Coefficient VREF+, VMR, VREFPower Supply Rejection Ratio, VMR Power Supply Rejection Ratio Vref+ and VrefStart Up Time
V+ref vs temperature
Symbol
Vvmr Vref+ VrefVrefout Vreftc PSSR PSSR Tstart
Min
1.925 3.4 0.45 60 75 -
Typ
2.01 3.51 0.505 0.5 -VMR vs temperature
Max
2.075 3.6 0.55 1
Unit
V V V % -
Comment
At 25C, Vdd=5.00 volts At 25C, Vdd=5.00 volts At 25C, Vdd=5.00 volts Over process and supply voltage corners See typical graphical data below -40C to 125C f
dB dB ms Assuming recommended capacitors

0.510 0.505
Volts Vref- vs temperature
3.510 3.505
Volts
2.010 2.005
Volts
3.500 3.495 3.490

-50 0 50 Tchip (C) 100 150
2.000 1.995 1.990
0.500 0.495 0.490
-50
50 Tchip (C)
100
150
-50
50 Tchip (C)
100
150
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CAB (Configurable Analog Block) Differential Operational Amplifier
Parameter
High Precision Input/Output Range c Standard Precision Input/Output Range d High Precision. Differential Input/Output c Standard Precision Differential Input/Output d Common Mode Input Voltage Range d Common Mode Output Voltage Range Equivalent Input Voltage Offset. Offset Voltage Temperature Coefficient Power Supply Rejection Ratio Common Mode Rejection Ratio CMRR Common Mode Rejection Ratio CMRR 60 dB 77 dB
Symbol
Vinouta Vinouta Vdiffioa Vdiffioa Vcm Vcm Voffset
Min
0.5 0.1 0 1.9 0.1
Typ
2.0 2.0 5
Max
3.5 3.9 +/-3.0 +/-3.8 4 2.1 15
Unit
V V V V V V mV
Comment
VMR +/- 1.5v
VMR +/-1.9v Common mode voltage = 2 V Common mode voltage = 2 V
Voffsettc
10
V/C
PSSR
80
dB
Differential Slew Rate, Internal Differential Slew Rate, External Unity Gain Bandwidth, Full Power Mode. Input Impedance, Internal Output Impedance, Internal
Slew Slew UGB Rin Rout
10 -
50 10 50 -
V/sec V/sec MHz Mohm Ohms
Some CAMs (Configurable Analog Modules) can inherently compensate from -40C to 125C some CAMs (Configurable Analog Modules) can inherently compensate Variation between CAMs is expected because of variations in architecture Example 1 GainInv CAM CAM clock = 1MHz CAM parameter settings Gain = 1 Example 2 Filterbiquad Setting = Low pass filter CAM clock = 1MHz CAM parameter settings Gain = 1, Corner frequency = 50KHz Quality Factor = 0.707 Applicable when the OpAmp load is internal to the FPAA Applicable when the OpAmp driving signal out of the FPAA package Applicable when sourcing and loading the OpAmp with a load internal to the FPAA The OpAmp output is designed to drive all internal nodes, these are dominantly capacitive loads Output to an FPAA output pin (ouput cell bypass mode). This variable is influenced by CAB capacitor size, CAB clock frequency and CAB architecture Additional loading causes internal voltage drops across output stage and series resistances The output stage has a small signal output impedance of approx 10ohm Example1 GainInv CAM CAM clock = 1MHz Gain = 1
Output Impedance, External Output Load, External c e Output Load, External c e Output Load, External d e f
Rout Rload Cload
0.1 -
--
Ohms Mohm pF
50
Rload
10
Kohm
Output Load, External d e f Noise Figure g
Cload Noise
0.13
50 -
pF V/sqrtHz
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Signal-To Noise Ratio and Distortion g

SINAD 80 dB Input signal=1400 mV p-p differential Audio frequency range Example. GainInv CAM CAM clock = 1MHz Gain = 1 Input signal=1400 mV p-p differential, Audio frequency range Example. GainInv CAM CAM clock = 1MHz Gain = 1
Spurious Free Dynamic Range g SFDR 92 dB
. . . f .
d e
High precision operating range provides optimal linearity and dynamic range. Standard precision operating range provides maximum dynamic range and reduced linearity. The maximum load for an analog output is 50 pF || 100 Kohms. This load may be with respect to analog ground VMR or AVSS. Using the FPAA with CAB Op Amps driving directly off-chip, requires care, full characterization of the performance of each application circuit by the circuit designer is necessary. g . This specification parameter can only be characterized when a circuit topology is configured onto the CAB differential amplifier architecture. The figure provided here is an representative on the performance of one specific CAM, as specified in the comments.
Idealized CAB Op Am p, Open Loop Gain [dB] 90 80 70 60 50 40 30 20 10 0 -10 -20 0.1 10 1000 100000 Frequency (KHz)
Open Loop Gain (dB)
The idealized open loop gain plot is provided for information only. This information is associated with the FPAA in full power mode of operation. The FPAA operation amplifier open loop gain cannot be observed nor used when associated with external connections to the device. Internal reprogrammable routing impedances and switched capacitor circuit architecture using this operational amplifier limit the effective usable bandwidth of a circuit realized in the FPAA to less than 2MHz.
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CAB (Configurable Analog Block) Differential Comparator
Parameter
Input Range, Internal Input Range, External Differential Input, Internal Differential Input, External Common Mode Output Voltage Range, Internal c Common Mode Input Voltage Range, External c Common Mode Input Voltage, External d Differential Output Single Pin Output (Ox1P) Input Voltage Offset Offset Voltage Temperature Coefficient Setup Time, Internal Setup Time, External Delay Time Output Load Output Load Differential Variable Reference Voltage Settings Differential Hysteresis Differential Hysteresis Differential Hysteresis Differential Hysteresis Hysteresis Setting Accuracy Hysteresis Temperature Coefficient Hysteresis Temperature Coefficient Hysteresis Temperature Coefficient Hysteresis Temperature Coefficient
c d
Symbol
Vina Vina Vdiffina Vdiffina Vcm Vcm Vcm
0.1 0.0 +/- 0.0 1.9 0 0 0 Td+25 10 0 -
Min
Typ
-
3.9 Vdd +/-3.8 +/- Vdd 2.1 4 5 +/-5 5 10 10 125 500 1Td+25 50 +/-4.0 -
Max
Unit
V V V V V V V V V mV V/C nsec nsec nsec Kohm pF V mV mV mV mV % V/C V/C V/C V/C
Comment
Common mode voltage = 2 V
2.0 2.0 2 1 Voffcomp 20 40 80 25 5 50 100 200
Voutdiff Vout Voffcomp Voffsettc Tsetint Tsetext Tdelay Rload Cload CompVref Hysta1 Hysta2 Hysta3 Hysta4 Hystb Hysttc1 Hysttc2 Hysttc3 Hysttc4
The comparator will function correctly Zero hysterisis from -40C to 125C, Zero Hysterisis Td = 1/Fc Fc = master clock frequency Applies if comparator drive off chip with output cell in bypass mode Applies if comparator drive off chip with output cell in bypass mode Hysteresis setting = zero Hysteresis setting = 10mV Hysteresis setting = 20mV Hysteresis setting = 40mV Hysteresis setting = zero Hysteresis setting = 10mV Hysteresis setting = 20mV Hysteresis setting = 40mV
. High precision operating range provides optimal linearity and dynamic range. . Standard precision operating range provides maximum dynamic range and reduced linearity.
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ESD Characteristics
Pin Type
Digital Inputs Digital Outputs Digital Bidirectional Digital Open Drain Analog Inputs Analog Outputs Reference Voltages
Human Body Model

4000V 4000V 4000V 4000V 2000V 1500V 1500V
Machine Model
250V 250V 250V 250V 200V 100V 100V
4kV 4kV 4kV 4kV 4kV 4kV 4kV
Charged Device Model
The AN221E04 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the AN221E04 device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Power Consumption Low Power Mode

Parameter
Minimum Power 1a Nominal 25% Power1b Nominal 50% Power 1c Nominal 75% Power1d Maximum Power1e Temperature Coefficient
Symbol
Idd Idd Idd Idd Idd -
Min
-
Typ
0.2 25 42 50 60 63 66 -2
Max
30 47 55 68 -10
Unit
Comment
mA = 5.00 = 25C Vdd volts, Tj mA Vdd=5.00 volts, Tj=25C mA Vdd=5.00 volts, Tj=25C mA Vdd=5.00 volts, Tj=25C Vdd=4.75 volts, Tj=85C mA Vdd=5.00 volts, Tj=25C Vdd=5.25 volts, Tj= -40C A/C
Power consumption low power mode (temp 25 degree C) 70 60 Idd (mA) 50 40 30 20 10 0 25% 50% 75% Vdd=4.75V Vdd=5.0V Vdd=5.25V 100% Resource Utilization
1a. External clock, all analog function disabled, memory active. 1b FPAA active elements Two core op-amps (low power mode), one comparator, one input (bypass mode), one output filter and differential to single-ended converter (low power mode). 1c. FPAA active elements Four core op-amps (low power mode), two comparators (one using SAR), two inputs (bypass mode), two output filters and two differential to singleended converters (low power mode). 1d FPAA active elements Six core op-amps (low power mode), three comparators (two using SAR), three inputs (bypass mode, two output filters and two differential to single-ended converters (low power mode). 1e FPAA active elements Eight core op-amps (low power mode), four comparators (two using SAR), four inputs (bypass mode), two output filters and two differential to singleended converters (low power mode).
Power Consumption Full Power Mode

Parameter
Full Power Mode Minimum Power 2a Full Power Mode Nominal 25% Power2b Full Power Mode Nominal 50% Power2c Full Power Mode Nominal 75% Power2d Full Power Mode Maximum Power2e
Symbol
Idd Idd Idd Idd Idd
Min
-
Typ
1.5 80 150 170 200 210 220
Max
90 160 190 230 -
Unit
mA mA mA mA mA
Comment
= 5.00 volts, Tj 25C Vdd = = 5.00 volts, Tj 25C Vdd = Vdd=5.00 volts, Tj=25C Vdd=5.00 volts, Tj=25C Vdd=4.75 volts, Tj=85C Vdd=5.00 volts, Tj=25C Vdd=5.25 volts, Tj= -40C
2a. AN221E04 Crystal Oscillator, all analog functions disabled, memory active. 2b. FPAA active elements Two core op-amps, one comparator, one input filter and chopper amplifier, one output filter and differential to single-ended converter. 2c. FPAA active elements Four core op-amps, two comparators (one using SAR), two Input filters and two chopper amplifiers, two output filters and two differential to single-ended converters. 2d FPAA active elements Six core op-amps, three comparators (two using SAR), three input filters and three chopper amplifiers, two output filters and two differential to single-ended converters. 2e FPAA active elements Eight core op-amps, four comparators (two using SAR), four input filters and two chopper amplifiers, two output filters and two differential to single-ended converters.
Power consumption full power mode (temp 25 degree C) 250 200 Idd (mA) 150 100 50 0 25% 50% 75% Vdd=4.75V Vdd=5.0V Vdd=5.25V 100%
Resource Utilization
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PINOUT
Pin Numb er
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Name
I4PA I4NA O1P O1N AVSS AVDD O2P O2N I1P I1N I2P I2N SHIELD AVDD2 VREFMC VREFPC VMRC BVDD BVSS CFGFLGb
Pin Type
Analog IN+ Analog INAnalog OUT+ Analog OUTAnalog Vss Analog Vdd Analog OUT Analog OUT Analog IN+ Analog INAnalog IN+ Analog INAnalog Vdd Analog Vdd Vref Vref Vref Analog Vdd Analog Vss Digital IN Digital OUT
Comments
21 22
CS2b CS1b
Digital IN Digital IN (during config) Digital IN (after config)_ Digital IN Digital Vss Digital IN Digital IN Digital OUT Digital OUT Digital OUT Digital Vdd Digital Vss Digital IN Digital OUT Digital IN (monitored OUT) Digital OUT Digital IN
Low noise Vdd bias for capacitor array n-wells Analog power Attach filter capacitor for VREFAttach filter capacitor for VREF+ Attach filter capacitor for VMR (Voltage Main Reference) Analog power for bandgap Vref Generators Analog ground for bandgap Vref Generators In multi-device systems... 0, Ignore incoming data (unless currently addressed) 1, Pay attention to incoming data (watching for address) 0, Device is being configured Z, Device is not being configured (if internal pullup is selected) 0, Chip is selected 1, Chip is not selected 0, Allow configuration to proceed 1, Hold off configuration Passes read-back data through to LCC_B pin Digital ground - substrate tie 0, Synchronous serial interface 1, SPI EPROM Interface MODE = 0, analog clock < 40 MHz MODE = 1, SPI EPROM or serial EPROM clock During power-up, sources SPI EPROM initialization command string After power-up, sources any of the four internal analog clocks Serial configuration data input 1, Local configuration is needed. Once configuration is completed, it is a registered version of CS1b or if the device is addressed for read, it serves as serial data out port 0, Initiate reset 1, No action 0, Error condition Z, No error condition (external pullup required) 0, Hold off completion of configuration Rising Edge, Allow completion of configuration O.D. Output 0, device has not yet completed primary configuration Z, Device has completed primary configuration (if internal pullup is selected) A buffered version of DCLK. (Factory reserved test input. Float if unused) 0, Chip held in reset state Rising edge, re-initiates power on reset sequence To initiate a POR reset cycle, the minimum pulse width required on the PORb pin is 25ns. 0, No action 1, Transfer shadow RAM into configuration RAM Analog multiplexer input signals. The multiplexer can accept 4 differential inputs or 8 single ended inputs
23 24 25 26 27 28 29 30 31 32
DCLK SVSS MODE ACLK / SPIP OUTCLK / SPIMEM DVDD DVSS DIN LCCb ERRb
33
ACTIVATE
34 35 36 37 38 39 40 41 42 43 44
DOUTCLK / TEST PORb EXECUTE I3P I3N I4PD I4ND I4PC I4NC I4PB I4NB
Digital OUT Digital IN Digital IN Digital IN Analog IN+ Analog INAnalog IN+ Analog INAnalog IN+ Analog INAnalog IN+ Analog IN-
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MECHANICAL AND HANDLING
The AN221E04 comes in the industry standard 44 lead MQFP package. Dry pack handling is rec ommended. The package is qualified to MSL3 (JEDEC Standard, J-STD-020A, Level 3). Once the d evice is removed from dry pack, 30C at 60% humidity for not longer than 168 hours is the maximum recommended exposure prior to solder reflow. If out of dry pack for longer than this re commended period of time, then the recomme nded bake out procedure prior to solder reflow is 24 hours at 125C. MQFP Package. Devices Manufactured 2002 to 2009. (See page 18 for new LQFP package devices manufacture from 2010).
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MECHANICAL AND HANDLING

The AN221E04 comes in the industry standard 44 lead MQFP package. Dry pack handling is rec ommended. The package is qualified to MSL3 (JEDEC Standard, J-STD-020A, Level 3). Once the d evice is removed from dry pack, 30C at 60% humidity for not longer than 168 hours is the maximum recommended exposure prior to solder reflow. If out of dry pack for longer than this re commended period of time, then the recomme nded bake out procedure prior to solder reflow is 24 hours at 125C. LQFP Package. devices manufacture from 2010 (See page 17 for older MQFP package Devices Manufactured 2002 to 2009.).
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Distortion, SINAD and SNR Measurements
The following plots give an indication of the Distortion, SINAD and SNR for some representative CAMs.
INPUT CELL UGB SNR, DSTN, SINAD
120 100 80 60 40 20 0 -20 -40 -60 -80 -100 0.7 1.4 2.8 5.6 7.0
120 100 80
SNR[ dB] DISTN[ dB]
INPUT CELL LOW PASS FILTER SNR, DSTN, SINAD
60
[dB]
[dB]
SINAD[ dB]
40 20 0 -20 -40 -60 -80 -100 0.7
SNR[ dB] SINAD[ dB] DISTN[ dB]
INPUT [Vp-p]
1.4
INPUT [Vp-p]
2.8
5.6
7.0
100.00 80.00 60.00 40.00 20.00 0.00 -20.00 -40.00 -60.00 -80.00 -100.00 0.08 0.14 0.21 0.28 0.35 0.42 0.49
SNR[ dB] SINAD[ dB] DISTN[ dB]
INPUT CELL AMPLIFIER SNR,DSTN,SINAD Measured with Inputcell Gain G = 16 Same results for Input Amplifier and Chopper Amplifier stage, If the signal from the chopper Amplifier is correctly filtered before measurement.
[dB]
INPUT [Vp-p]
Output Cell SNR, DSTN, SINAD

120 100 80 60 40 20 0 -20 -40 -60 -80 -100 0.7
[dB]
SNR[dB] SINAD[dB] DISTN[dB]
1.4
2.8
3.5
5.6
7.0
INPUT [Vp-p]
100 80 60 40 20 SNR[ dB] SINAD[ dB] DISTN[ dB]
0 - 20 - 40 - 60 - 80 - 100 - 120 0.7 1.4 2.8
GAININV CAM SNR, DSTN, SINAD This graph shows the typical performance of an FPAA CAB when configured with a CAM in this example GainInv CAM Input signal=1400 mV p-p differential, CAM clock = 1MHz CAM parameter settings Gain = 1
5.6 7.0
[dB]
3.5
INPUT [Vp-p]
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Power Supply Rejection Ratio (PSRR) Measurements
The following plots give an indication of the PSRR for some representative CAMs. AVDD to Power Supply (PS): 5v +/- 0.25v sinusoidal waveform (100 kHz to 1 MHz)
INPUT AMP PSRR [dB]
80.00 70.00 60.00 50.00 40.00 30.00 20.00 DC 100 1KHz 10KHz 100KHz 1M Hz
80.00 70.00 60.00 50.00 40.00 30.00 20.00 DC 15 50 100 1KHz 10KHz 100KHz 1M Hz
INPUT LPF PSRR [dB]
100.00 90.00 80.00 70.00 60.00 50.00 40.00 30.00 20.00 DC
VMR, Vref+, Vref-
PSRR [dB]
PSRR_VMR [ dB] PSRR_VREFP [ dB] PSRR_VREFP [ dB]
100
1KHz
10KHz
100KHz
1M Hz
OUTPUT Voltage Mode + LPF PSRR [dB]

80.00 70.00 60.00 50.00 40.00 30.00 20.00 DC 100 1KHz 10KHz 100KHz 1M Hz
GAININV_1MHz PSRR [dB]

100 90 80 70 60 50 40 30 20 DC 50 100 1KHz 10KHz 100KHz 1M Hz 100 90 80 70 60 50 40 30 20 100
GAININV_4MHz PSRR [dB]
1KHz
10KHz
100KHz
1M Hz
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The following is provided for information only, as and when additional characterization data is collected noise measurements will be added formally to the datasheet.
Noise And Distortion Observations

The following plots give an indication of the noise characteristics of Anadigms AN221E04 FPAA device. These were done using a simple set-up and in many cases reflect the noise limit of the setup. Actual device noise margins are expected to be better.
Signal and Noise for the Input Cell (input signal - 50mVp-p differential to the FPAA at 10 kHz)
Signal to Noise: -92 dB, at 376KHz, 3Hz BW
Input gain stage set at X16 Input anti-aliasing filter set off Input chopper amplifier set off
Signal and Noise for the Output Cell (with a differential input 4V p-p, 660Hz)
Signal to Noise: -106 dB, at 345KHz, 3Hz BW
Voltage output mode (including filter) ON Output smoothing filter set at fC = 470 kHz
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Measured THD for input and output cells (with a differential input 4V p-p, 660Hz)
Settings
Input cell with anti-aliasing filter set at fC = 470 kHz Output cell with differential to single ended converter and output smoothing filter set at fC = 470 kHz
Distortion in dB
81.6 82
Signal and Noise for a representative CAM Gaininv CAM (input signal of 700mV p-p differential at 10 kHz)
Signal to Noise: 108 dB, at 528 kHz, 3Hz BW
THD for a representative CAM Gaininv CAM (with a differential input 4V p-p, 660Hz)
CAM Clock Frequency

250 KHz 1 MHz 2 MHz 4 MHz
Distortion (dB)
80.00 72.83 69.22 73.48
As above, zoom to lower frequency
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AN221E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced I/O Notes
DS030100-U006c
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For More information Contact
http://www.anadigm.com support@anadigm.com
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AN221E04 Datasheet

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AN221E04 Datasheet

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AN221E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced I/O

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