This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication.

A Novel DC Voltage Control Method for STATCOM Based on Hybrid Multilevel H-bridge Converter
Sixing Du, Jinjun Liu, Senior Member, IEEE, Jiliang Lin, Yingjie He, Member, IEEE
frequency or increasing the cascaded number of modules, which bring high power loss or high cost to the STATCOM system. Fortunately, hybrid multilevel technology provides a good tradeoff between waveform quality and switching loss [9]. The important advantages of hybrid multilevel converters are as follows: increasing voltage levels of output waveform, improving AC current quality, reducing switching frequency resulting in low switching loss, as well as enhancing converter efficiency. As the concept of hybrid multilevel was proposed in literature [10], great attentions have been paid to this field. In order to achieve hybrid multilevel, many approaches have been published in literatures [11-22] [26] [27]. A hybrid topology with the series connection of three-phase full-bridge converter (two-or three-level) and single-phase H-bridge converter is adopted by literature [11-16][26][27]. This topology effectively produces higher voltage levels compared with traditional ones with the same number of switches, but it is companied by a problem of DC voltage control. One popular method for capacitor voltage control is selecting switching states redundancy [11] [12] [13], which introducing another problem of uncertain switching frequency for relevant devices. To avoid the issue of DC voltage control, DC link of the hybrid topology is connected directly to expensive DC supplies such as battery, fuel cell and rectifier[14][15][26]. In [16], three-phase three-level converter is fed by rectifiers while the H-bridge converter uses a capacitor as a replacement of DC source for cost saving. Capacitor voltage and NPC voltage is regulated by adjusting common mode voltage. This control algorithm requires a large amount of real-time online calculation, which brings difficulty for STATCOM application. In [27], all the DC-link voltages are controlled purely by control algorithm. Reactive-power regulation is realized by adjusting DC voltages. However, this control method is based on steady state model and the dynamic performance is not discussed. Additionally, the capability of compensating unbalanced load is not mentioned either. Moreover, hybrid multilevel topology based on cascaded single-phase H-bridge converter with unequal DC voltage is considered by [17-22]. Literatures [17] [18] describe a motor drive system based on hybrid multilevel H-bridge converters with unequal DC voltage supplies. The mentioned control method is not suitable for STATCOM system because the DC sources are replaced by capacitors in STATCOM system. Literatures [19] [20] [21] provide new solution with

AbstractThis paper presents a transformerless static synchronous compensator (STATCOM) system based on hybrid multilevel H-bridge converter with delta configuration. This hybrid multilevel STATCOM is characterized by per-phase series connection of a high-voltage H-bridge converter operating at fundamental frequency and a low-voltage H-bridge converter operating at 5 kHz without any other circuit for DC voltage control. A new control strategy is proposed in this paper with focus on DC voltage regulation. Clustered balancing control is realized by injecting a zero-sequence current to the delta-loop while individual voltage control is achieved by adjusting the fundamental content of AC quasi-square-waveform voltage of high-voltage converter. A downscaled experimental prototype rated at 100V and 3kVA is constructed in authors laboratory. Experimental results show that the hybrid multilevel STATCOM performs satisfactory not only improving efficiency and waveform quality , but also compensating reactive power and negative-sequence current while maintaining DC voltage at the given value. Index TermsCascade H-bridge, STATCOM, DC voltage control, hybrid multilevel.

I. INTRODUCTION ascaded H-bridge converter with equal DC voltage has been widely used for STATCOM application because of natural modular and high-quality output spectrum [1-7] [25]. Compared with diode-clamped converter and flying capacitor converter, cascaded single-phase H-bridge converter saves a large amount of clamped diodes and flying capacitors [8]. However, further improvement of power efficiency and waveform quality is expected of cascade H-bridge topology in high power application [9]. Traditionally, low-distorted AC voltage waveform is achieved by either increasing switching
Sixing Du is with the Department of Industry Automation, Xi'an Jiaotong University, No.28 Xianning West Road, Xian, Shaanxi, 15289367159, China (e-mail: dusixing@163.com). Jinjun Liu is with the Department of Industry Automation, Xi'an Jiaotong University, No.28 Xianning West Road, Xian, Shaanxi, 029-82665223, China (e-mail: jjliu@mail.xjtu.edu.cn). Jiliang Lin is with the Department of Industry Automation, Xi'an Jiaotong University, No.28 Xianning West Road, Xian, Shaanxi, 029-82665223, China (e-mail: linjiliang2008@stu.xjtu.edu.cn). Yingjie He is with the Department of Industry Automation, Xi'an Jiaotong University, No.28 Xianning West Road, Xian, Shaanxi, 029-82665223, China (e-mail:hyj202411@163.com).

Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

2 high-voltage converter fed by DC supplies and low-voltage converter fed by DC capacitor. In [19], diode-clamped H-bridge with multi-output boost rectifier functions as the high-voltage inverter. The utilization of clamped diode and rectifier increases the cost of whole system. In [20], DC voltage ratio of 4:2:1 is arranged to the series-connected H-bridge converters. The expensive isolated DC supplies are required for ratio-4 and ratio-2 converters. Fundamental frequency modulation is adopted by literature [21] for cascade hybrid H-bridge converters. In [21], selective harmonic elimination method is adopted for hybrid modulation and selecting switching redundant states is applied for capacitor voltage control. The quality of output voltage waveform is not good, which prevents this method for STATCOM application. Literature [22] proposes an active power filter system composed of three series-connected H-bridge converters with voltage ratio of 6:2:1.5, which is realized by control algorithm. However, DC voltage control strategy is not discussed in detail and three-phase performance is not verified by experiments. Recently, some other interesting topologies have been published in [28]-[30]. In [28], a hybrid-source impedance networks with the DC-link of serious-connected z-sources is presented for enhancing the three-phase AC voltage levels, but it is not suitable for STATCOM application because of the utilization of large amount of DC sources. Literature [29] describes a multilevel circuit topology based on switched-capacitors and diode-clamped converters. The model related to switched-capacitor converters is given by literature [30]. This kind of converters can successfully produce high voltage levels and the issue with DC voltage balancing can be easily solved by choosing proper switching sequences. This structure requires a plenty of switching devices, so it havent widely accepted in medium-voltage application. In this paper, the authors focused on the STATCOM application using hybrid multilevel converters. Delta-type cascaded Hybrid single-phase H-bridge topology is preferred because of modularity and simplicity. This paper proposed a new DC voltage control strategy for those hybrid multilevel converters. Clustered balancing control is achieved by injecting zero-sequence current to the delta-loop and the individual voltage control is realized by trimming the fundamental content of quasi-square-wave voltage of high-voltage converters. Compared with other hybrid multilevel approaches, this control strategy along with the STATCOM system has the advantages of fast-speed response to load change, accurate unbalanced load compensation, none auxiliary circuit for DC-links, less on-line calculation, specific unequal DC voltage regulation, as well as certain but unequal switching frequencies. The experiment results obtained from the downscaled prototype confirm the merits. single-phase H-bridge cells. TABLEsummarizes the circuit parameters. The cascade number of N = 2 is assigned to the prototype because of the restriction of the authors laboratory condition, resulting in 6 converter cells in total. In each phase cluster, one single-phase H-bridge cell is controlled as a high-voltage converter with DC-link voltage of 110V, and the other single-phase H-bridge cell acts as a low-voltage converter with DC-link voltage of 65V. The explanation of this arrangement is described in next section. Each cell is equipped with an isolating electrolytic capacitor with a capacitance value of 9400 F. No auxiliary circuit is connected to the six split DC capacitors except for six voltage sensors. An ac inductor is also required for each cluster to support the difference between the sinusoidal source voltage and the AC PWM voltage of cluster, and it also makes contribution in filtering out switch ripples caused by high-frequency modulation.

(a) Hardware of experimental STATCOM

Ls

MC1

MC1

icu
MC2

icv
Rs
LAC

MC1

icw
MC2

Rs
LAC

MC2

Rs
LAC

viu

C v cu1

viv

viw
C vcv1 C v cw1

vcu 2

C vcv 2

C v cw2

Fig 1. 100-V 3-kVA downscaled STATCOM. (a) Experimental hardware view. (b) Configuration of experimental system.

II. CONFIGURATION OF THE 100-V 3-kVA STATCOM SYSTEM Fig 1 shows the configuration of a three-phase STATCOM rated at 100-V and 3-kVA, which is based on hybrid cascade

In experiment, switching frequencies of 50 Hz and 5 kHz are assigned to high-voltage converter and low-voltage converter respectively. The constant DC voltages are achieved purely by control algorithm. This design is reasonable to verify the improvement of output voltage waveform and the performance

Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

3 of the 100-V 3-kVA STATCOM system, because these special characteristics mainly relay on control strategy.
TABLE . Circuit parameters in fig 1 Nominal line-to-line rms voltage v sab , v sbc , v sca Power rating P AC inductor L AC Starting resistor Rs Back ground inductance Ls DC voltage for cell u1,v1,w1 Vcu1 ,Vcv1 ,Vcw1 DC voltage for cell u2,v2,w2 Vcu 2 ,Vcv 2 ,Vcw2 DC capacitor C Switching frequency for cell u1,v1,w1 PWM carrier frequency for cell u2,v2,w2 100 V 3kVA 6mH 51 0.3mH 110V 65V 9400 F 50Hz 5000Hz

viu

Vcmp
0 Vcmp
u Vcu1

viu1

Vcu1
u

Ls
3
100V,50Hz PT

LAC

0
3
PLL

3
A/D

Hybrid H-bridge converters

12 24
DSP

u Vcu 2
6

viu 2

FPGA (PWM)

0 Vcu 2

Fig 3. Diagram for hybrid modulation

Fig 2. Fully digital control system for 100-V 3-kVA STATCOM

As is shown in fig.2, this experimental system is totally controlled by a fully digital controller using a 32-bit digital signal processor (DSP) and field-programmable gate arrays (FPGA). Most of the calculation is dealt with by the DSP chip and the hybrid modulation strategy is implemented on FPGA chip. The gating signals for all the switching devices are generated by the hybrid modulation, which matches the 10-kHz sample frequency well. Hybrid modulation shown in fig. 3 includes two parts: fundamental modulation and PWM modulation. The fundamental modulation could be simply described as: when the sinusoidal command is higher than a threshold value of Vcmp , the high-voltage converter output positive voltage; as the sinusoidal command is lower than the negative threshold value of Vcmp , the high-voltage converter output negative voltage; if the sinusoidal command is in the range between Vcmp to Vcmp , the high-voltage converter outputs zero. The remaining part of sinusoidal command and the quasi-square-waveform voltage is the comand voltage for low-voltage converter. It is modulated by single-polar PWM modulation technology with the carrier frequency of 5 kHz. Based on this modulation strategy, an AC waveform with higher voltage levels is produced. It brings the advantages of improving output quality, keeping high equivalent switching frequecy, and reducing power loss.

III. MATHEMETIC ANALYSIS OF CAPACITOR VOLTAGE CONTROL

A. Fundamentals of circuit operation In each cluster, the high-voltage converter output quasi-square-waveform while the low-voltage converter output the remaining part between sinusoidal command and the quasi-square-waveform shown in fig.4. Therefore, low-frequency contents in total AC voltage are completely eliminated. The total AC voltage only includes fundamental component and harmonic components around switching frequency. Three-phase smooth sinusoidal currents are guaranteed because the high-frequency components can be easily filtered by interface inductors. The sharp change of load can be well followed by dynamically trimming the sinusoidal command voltage, which ensures the fast-speed response. As the issue with DC voltage control is also very crucial for safe operation. DC voltage control strategy is also investaged in this paper. As is shown in fig.4, a fundamental-frequency zero-sequence current is suggested to the delta-loop for balancing of DC voltages among three phases. This clustered balancing method enables the STATCOM system to compensating unbalanced load. Moreover, unequal DC voltages of high-voltage converter and low-voltage converter are achieved by the effert of individual voltage control, which suggests a small trim to the fundamental contents of quasi-square-waveform voltage of high-voltage converter for

Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

4 active-power redistribution between high-voltage and low-voltage converters. In the whole process, the low-voltage converter always compensates the remaining part to match the sinusoidal command. Additionally, the sum of all capacitor voltages is regulated by the algorithm of overall voltage control. vsa
viu 2
p oab = p nab + p ab p obc = p nbc + p bc p oca = p nca + p ca

(3)

Where, terms of p nab , p nbc , p nca are used for power cancellation and terms of p ab , pbc , p ca are used for balancing of DC voltages among clusters. For simplification, the clustered balancing control considers a cluster of series-connected converters as one equivalent single-phase H-bridge converter. The mathematic relationship between the clustered capacitor voltage and active power is calculated by: dv 2 Vcu v cu p ab = C Vcu cu + (4) dt Rc Where Rc is the equivalent parallel resistance of u-phase cluster, which represents the power loss of u-phase converters. Equation (5) gives the transfer function, which is obtained by applying Laplace transformation to (4). According to (5), the regulator for clustered balancing control could be designed. v R (5) Gvp = cu = p ab RCVcu s + 2Vcu In practice, the amount of active power redistributed by zero-sequence current is calculated by close-loop based regulator. Once the required power is determined, the command zero-sequence current can be obtained by solving equation (2). The magnitude I o and original phase angle o are derived by:
Io = 2 Vs ( p oab ) 2 +
1

vsb

viu1

viw1
viw2

vsc

viv 2

viv1

vsa

viu
vsb
io
viw

vsc

viv

Fig 4. Three-phase equivalent circuit

B. Injection of zero-sequence current for clustered balancing control

1 ( p oab + 2 p obc ) 2 3 2 p obc p oab )]

The command zero-sequence current with the symbols of I o and o could be written as:
io = I o sin(t + o )

o = tan [

1 3

(6)

(1 +

(1)

Where I o and o are the magnitude and original phase angle respectively. The average power redistributed by zero-sequence current is expressed as: V I 1 t +Ts poab = v sab io dt = s o cos( o ) Ts t 2 V I 1 t +Ts 2 (2) pobc = v sbc io dt = s o cos( o + ) Ts t 2 3 V I 1 t +Ts 2 poca = v sca io dt = s o cos( o ) Ts t 2 3

Where Vs is magnitude of line-to-line grid voltage; Ts is a line period. v sab , vsbc , vsca are the three-phase line-to-line voltage. The sum of the three equations in (2) equals to zero, which indicates that zero-sequence current just causes the redistribution of active power among three clusters without any influence on total active power. The redistributed power could be used for canceling that caused by unbalanced compensating current, as well as for providing proper amount of power for balancing of DC voltages among three clusters. Therefore, the average power could be expressed as:

C. Trimming fundamental content of quasi-square-waveform for individual voltage control As the clustered DC voltage are controlled and maintained, the individual control become necessary because of the different power loss between high-voltage converter and low-voltage converter. Due to the symmetry of structure and parameters among the three phases, u-phase cluster was taken as an example for individual control analysis. As is shown in fig.5, the fundamental voltage and input current of u-phase cluster could be assumed as: viu = Viu sin(t iu ) (7) icu = I c cos(t cu ) (8) During one line period, the average power absorbed by the high-voltage converter could be calculated as:
piu1 = = 2
iu + 3 / 2 +Wa / 2 1 iu + / 2 +Wa / 2 Vcu1 icu dt + Vcu1 icu dt ) ( iu + 3 / 2 Wa / 2 Ts iu + / 2 Wa / 2

W Vcu1 I c sin( cu iu ) sin( a ) 2

(9)

Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

i/u
cu
icu Vcmp

modulated waveform is got by:

viu

Cvalue =

piu1
* piu1

iu + / 2 + Wa / 2

Vcu1

2 2 Viu Vcmp 2 Viu

(14)

t 0
iu + / 2 Wa / 2
iu
iu + / 2

cu
icu
Vcmp

viu

viu

iu + / 2 + Wa / 2

+ cu

iu + / 2 Wa / 2
iu

Fig.5 Mathematic analysis for individual control

Where, Vcu1 is the high-voltage DC-link; I c is the magnitude of input current; cu is the original phase angle referring to the pure reactive current, which is introduced to represent the active power absorbed by high-voltage converter; iu is also a original phase angle respecting to the source voltage; Wa is the pulse width of the quasi-square-waveform voltage of high-voltage converter. Equation (9) implies that the active power of high-voltage converter is affected by Vcu1 , I c , cu ,

iu + / 2
+ cu

Fig. 6 The modulation of the high-voltage converter for DC voltage control

iu and Wa . Actually, I c and cu are decided by the reference current. Therefore, iu and Wa are the only factors that could be
used for adjusting DC voltage of high-voltage converter. In this paper, the adjustment of both iu and Wa is preferred, which is realized by trimming the modulated waveform along the direction of input current icu . As is shown in fig.5, the mathematic relationship between threshold value Vcmp and pulse width Wa could be expressed as: Viu sin(t 0 iu ) = Vcmp Wa 2 + iu t 0 = 2 By solving equation (10), the result is obtained by:
2 2

(10)

According to (14), the average power absorbed by high-voltage converter could be easily obtained by calculating the modulated waveform. In order to control the capacitor voltage of high-voltage converter, the modulated waveform can be changed as: viu = viu + e icu = Viu sin(t iu ) + e I c cos(t cu ) (15) Where, e is the trimming amplitude along the direction of input current. The modulated waveforms before and after change are shown in fig. 6. And then, the power calculated by the modulated waveform is obtained by: 1 t +Ts 1 * * 2 (16) p iu1 = (viu icu )dt = p iu1 + e I c t 2 Ts Based on (14), the average power absorbed by high-voltage converter is rewritten as: 1 * 2 (17) p iu1 = C value p iu1 = p iu1 + e I c C value 2 Therefore, the change of power for high-voltage converter could be obtained:

Viu Vcmp W sin( a ) = (11) 2 Viu Substituting (11) into (9), average power obtained by the high-voltage converter can be rewritten by: (12) Viu The average power calculated by the modulated waveform is expressed as: 1 t +Ts 1 * (13) piu1 = (viu icu )dt = Viu I c sin( cu iu ) Ts t 2 The relationship between the average power absorbed by the high-voltage converter and the power calculated by the piu1 = 2

p iu1 =

2 e I c Vcu1

2 2 Viu Vcmp 2 Viu

(18)

Vcu1 I c sin( cu iu )

2 2 Viu Vcmp

The mathematic relationship between the power and the capacitor voltage is calculated by: dv 2 Vcu1 vcu1 piu1 = C Vcu1 cu1 + (19) R dt Where R is the equivalent parallel resistance of DC capacitor. The transfer function is obtained by applying Laplace transformation to (18) and (19).
Gvh =
2 2 2 v cu1 2 Viu Vcmp R Ic = 2 e RCs + 2 Viu

(20)

When the clustered DC voltage and the high-voltage DC-link

Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

6 are regulated, the low-voltage DC-link would be automatically maintained at the expected value because it equals to the difference between the clustered DC voltage and the high-voltage DC-link. According to (20), the individual voltage control algorithm is designed. D. Design of DC capacitor voltages In each phase cluster, the high-voltage converter and low-voltage converter complement each other to produce the sinusoidal command voltage. Therefore, the low-voltage DC-link illustrated in fig.7 must be higher than the difference of sinusoidal command and quasi-square-waveform to guarantee the safe operation. Taking u-phase cluster for an example, the constraint can be described as: Vcu1 < V * < Vcu1 + Vcu 2 iu (21) V x1 = Vcu1 Vcmp < Vcu 2 V =V < Vcu 2 x2 cmp Where, Vcu1 is the high-voltage DC-link; Vcu 2 is the
* low-voltage DC-link; V iu is the magnitude of the sinusoidal

IV. CONTROL STRATEGY Fig 8 shows a block diagram of the control algorithm proposed in this paper. The whole control algorithm consists of four parts, namely, decoupled current control, overall voltage control, clustered balancing control and individual voltage control.
vcu1 vcu 2 vcv1 vcv vcw2 vcw1 2 Vdc _ ref ila ilb ilc

idref iqref

idcref
* iq

vsab vsbc vsca

icu icv icw

d q

vsd vsq

* id

io

v* iu v* iv
v* iw
* vo

id d q iq

viu1 viu 2 viv1 viv 2 viw1 viw2

Fig 8. Block diagram of the total control scheme for 100-V 3-kVA STATCOM

command; Vcmp is a constant threshold value. Inequality (21) could be rewritten as: Vcu1 < V * < Vcu1 + Vcu 2 iu Vcu1 < 2 Vcu 2 V V cu1 cu 2 < Vcmp < Vcu 2
Vcu1 + Vcu 2
Vcu1

(22)

* viu

Vcu 2
Vx1 < Vcu 2

Vcmp
0
Vcmp
Vcu1

A. Decoupled current control Referring to fig 1, the set of voltage-current equation can be obtained as follows: di L AC cu + RL icu = v sab viu dt dicv (23) L AC + RL icv = v sbc viv dt di L AC cw + RL icw = v sca viw dt Where RL is the equivalent series resistance (ESR) of the

Vx 2 < Vcu 2

/2

3 / 2

inductor. Applying the d q transformations (23), the equations in d q axis are derived:
did L AC iq + RL id = v sd vid dt (24) diq L AC + L AC id + RL iq = v sq viq dt The proportional and integral (PI) regulators with parameters of kip and kii are introduced for close-loop current control. L AC

Vcu1 Vcu 2
Fig. 7 Principle for DC voltage decision

Based on (22), the reference value can be assigned as Vcu1 = 110V , Vcu 2 = 65V and Vcmp = 55V . This voltage ratio

Parameters of kip and kii are given in Table-II. The command voltages in d -axis and q -axis are given by:
k * vid = L AC iq + vsd (kip + ii )(id id ) s (25) k * viq = L AC id + vsq (kip + ii )(iq iq ) s Here, id and iq are the feed back currents in d -axis and
* * q -axis respectively. id and iq are the d -axis and q -axis

of Vcu1 : Vcu 2 is close to 2:1, but there is a small margin of Vcu1 Vcu 2 / 2 = 10V . This small margin is essential for individual voltage control. As a result, nine voltage levels of 0V, 45V, 65V, 110V, 175V are produced by each cluster. Although unequal steps exist, the output spectrum is still improved compared with the traditional 5-level waveform.

* * reference currents. The three-phase command voltages viu , viv

Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

7
* and viw can be obtained by applying the inverse d q transformations to vid and viq as shown in fig 9.

B. overall voltage control

Vdc _ ref +

* d

vsd

vid

v* iu
vdc _ sum

k vp + kvi / s

idcref

id
i
* q

LAC

Fig 12. Block diagram of overall voltage control.

iq

d q
viq vsq

v* iv v* iw

Fig 12 shows the overall voltage control diagram. Vdc _ ref is the reference value for the sum of all the dc capacitors voltage. vdc _ sum acts as the feedback, which is obtained by summing up all the dc capacitors voltage. PI regulator is preferred for overall control. The regulator design process for k vp and kvi is similar to literature [24]. The output of PI regulator is the active component of command current. C. Clustered balancing control.

LAC

Fig 9. Block diagram of decoupled control

Command current generating algorithm intended for detecting reactive and negative-sequence load current includes two parts, reactive current algorithm and the negative-sequence current algorithm. These two parts are all based on d q transformations and moving average low-pass filter (LPF). The main difference between them is that the negative-sequence current algorithm needs to change the position of b -phase current and c -phase current when applying d q transformations. As is shown in fig 10, the upper algorithm is for reactive current detection and the lower algorithm is for negative-sequence current detection. The three-phase line * * * current ila , ilb , ilc ought to be transformed into phase current because of the delta configuration of the three clusters. Fig 11 shows the diagram for this transformation. One of the solutions as described in (26), is preferred because of its independence from the zero-sequence current [23].
* * iuref = (ila ilb ) / 3 * * iwref = (ilb ilc ) / 3

sin t
vdc _ ave
poab

cos t

vcu

ioref
pobc
vcv

kio

* uo

iio

Fig 13. Clustered balancing control among the three clusters by introducing a zero-sequence current, where each of the three clusters is considered as single-phase H-bridge converters.

(26)

ivref =
ila ilb ilc

* (ilc

* ila ) / 3
Caculation (Eq.20)
* ila * ilb * ilc
+

d q

d q

+ + + +

iuref ivref d q iwref

idref iqref

Fig 13 shows the block diagram of clustered balancing control. Two PI regulators with constant parameters are adopted for calculating the amount of power for redistribution. The reference zero-sequence current is synthesized based on equation (1) (6). Referring to (3) (5), the close-loop control is formed in fig.14. Where Vcu is the total DC voltage of u-phase cluster at steady state operating point; vcu is the small voltage change around Vcu .
pnab
vdc _ ave

d q

d q

Fig 10. Block diagram of command current generating algorithm

vcu

k k op + oi s

poab

pab

vcu R RCVcu s + 2Vcu

Vcu
vcu

* la

iuref iwref ivref

* ilb

Fig 14. Block diagram of clustered balancing control

* ilc

The closed-loop transfer function is obtained by: Rk op s + Rk oi vcu = 2 vdc _ ave RCVcu s + (2Vcu + Rk op ) s + Rk oi

(27)

Fig 11. Diagram for the transformation from line current to phase current

Based on (27), the parameters of k op and k oi for PI regulators are designed and the design processing can be found in the literature [24]. The parameters are given in Table-II.

Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

8 D. Individual voltage control.

viu
+

V. EXPERIMENT RESULTS
viu 2

Su 2

Vcu1

vcu1 _ ref + vcu1

+ +

viu1
Vcmp
S u1

icu

Fig 15. Individual voltage control, taking

u -phase cluster for example.

Fig 15. shows the block diagram of the individual voltage control. Let ucu1 be the difference between the reference voltage and the capacitor voltage of high-voltage converter: vcu1 = vcu1 _ ref vcu1 (28) After introducing the proportional regulator k p , the close-loop control based on (20) is formed in fig.16. Where
vcu1 is the small voltage change around Vcu1 .
vcu1 _ ref
vcu1

(CH1: source voltage, v sab ; CH2: output voltage of u-phase cluster viu ; CH3: output voltage of cell u2 viu 2 ; CH4: output voltage of cell u1 viu1 ) Fig 17. Experiment waveforms testing for the hybrid modulation

2 k p e

2 Viu

2 Vcmp 2 Viu

2 R Vcu1 I c vcu1 RCVcu1s + 2

Vcu1

vcu1

Fig 16. Block diagram of individual voltage control

The closed-loop transfer function is obtained by:

vcu1 vcu1 _ ref

2 Rk p Cvalue I c 2 2 RCVcu1s + RCvalue k p I c + 4

(29)

(a)
(CH1: source voltage v sa ; CH2: STATCOM line-current ica (1A/10mV); CH3: capacitor voltage vcu 2 ; CH4: capacitor voltage vcu1 )

Based on (29), the regulator k p is designed and the design processing can be found in the literature [24].
TABLE II. CONTROL GAINS AND PARAMETERS Symbols Experiment Symbols Experiment

k vp kip k op k io

0.1A/V 25V/A 0.3A/V 2V/A

k vi k ii k oi kp

0.3A/V 166V/A 1.5A/V 0.5A/V

(b) (CH1: capacitor voltage vcv1 ; CH2: capacitor voltage vcv 2 ; CH3: capacitor voltage vcu 2 ; CH4: capacitor voltage vcu1 ) Fig 18. Experiment waveforms testing for individual balancing control with high-DC link-voltage 110V and low-DC link-voltage 65V

Fig.17 shows the experiment results verifying the effect of hybrid modulation. As the DC voltage of the high-voltage converter maintains at 110V and those of the low-voltage converter stays at 65V, 9-level voltage waveform is produced. The voltage steps of 45V and 65 are close to each other, so it

Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

9 looks like a 7-level voltage waveform. The quasi-square-waveform voltage of the high-voltage converter and the 3-level PWM-waveform voltage of low-voltage converter are also generated as expected. This hybrid modulation scheme is effectiveness in both of producing high-quality low-harmonic output voltage and reducing the power loss of high-voltage converters Fig 18. shows the experiment waveforms in capacitive operation at q* =-2.2kVA. At the beginning of the experiment, individual voltage control is not applied while other controls remain active. The DC voltages of both the high-voltage converter and the low-voltage converter could not maintain at the given values. After a short time period of 20 seconds, the individual voltage control is enabled and the two DC voltage waveforms return to the given values quickly. Because the scope is limited to 4 channels, only the DC-link voltages of u-phase cluster and v-phase cluster are shown in fig.18 (b). This experiment verifies that the individual voltage control is effective for regulating individual DC voltages. voltages of three clusters is not maintained at the given values. After a short time period of 20 seconds, the clustered balancing control is triggered and the 4 curves converge as two quickly. The experiment verifies that the clustered balancing control is effective for balancing DC voltages among three clusters.

(CH1: source voltage v sab ; CH2: output voltage viu ; CH3: STATCOM
* phase-current icu (1A/10mV); CH4: reactive power q (kVA/div)) Fig 20. Experiment waveforms in a transient state from inductive to capacitive operation at 2.2kVA.

The dynamic performance of the hybrid multilevel STATCOM is also tested. Fig 20 shows the experiment waveforms in a transient state from inductive to capacitive operation from q * =-2.2kVA to 2.2kVA with a sharp change. Dynamic response is very fast. During the transient state, whole system works well with 9-level output voltage. Note that a small degree of distortion exist in the STATCOM phase-current icu . The explanation is that icu is clustered current which includes the distorted circulation current. It does not affect the line current because the circulating current is not injected to the network. Fig 21. Confirms the compensation effectiveness when the three-phase load is balanced. As is shown in fig.21 (a), the STATCOM system is enabled for 100ms. During this interval, the RL load is sufficiently compensated. After compensation, source side current keeps in phase with source voltage. Fig.21 (b) shows that when the STATCOM system is in run mode, DC voltage is maintained at the given value and the fast response is ensured. Phase B and C have the same compensation effect, but only A-phase curves are demonstrated due to the limitation of 4 channels of the scope. Fig 22. Confirms the effect of unbalanced load compensation. As is shown in fig 22(a), a great difference exists in the magnitudes of the STATCOM current. Because of the limitation of scope, only the current of ica and icb are shown. During the compensating process, the dc mean voltage of capacitors stays at the reference value of 110V and 65V respectively in fig22 (b). In order to compensate unbalanced load, the STATCOM output unbalanced line current to network while a zero-sequence current is produced by the clustered balancing control to keep the equal DC voltages of the three clusters. After compensation, the source side currents have the same magnitude and keep in phase with the grid voltages

(a)

(CH1: source voltage vsa ; CH2: capacitor voltage vcu 2 ; CH3: STATCOM
line-current ica (1A/10mV); CH4: capacitor voltage v cu1 )

(CH1: capacitor voltage vcu 2 ; CH2: capacitor voltage v cv 2 ; CH3: capacitor

voltage v cv1 ; CH4: capacitor voltage v cu1 ) Fig 19. Experiment waveforms testing for clustered balancing control

Fig.19 shows the experiment waveforms for testing clustered balancing control. At the beginning of the experiments, clustered balancing control is intentionally disabled while other controls are still enabled. The waveforms of DC voltages show clearly as four different curves in fig.19(b), and the DC

Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

10 respectively in fig 22(c). The power quality is greatly improved with the power factor being unit.

(b)
(CH1: capacitor v cu 2 ; CH2: capacitor voltage v cu1 ; CH3: STATCOM line-current icb (1A/10mV); CH4: STATCOM line-current ica (1A/10mV))

(a)
(CH1: source voltage v sa ; CH2: source side current i sa (1A/10mV); CH3: load current ila (1A/10mV); CH4: STATCOM line-current ica (1A/10mV))

(c)
(CH1: source voltage v sa ; CH2: source current i sb (1A/10mV); CH3: source current i sa (1A/10mV); CH4: STATCOM line-current ica (1A/10mV)) Fig 22. Experiment waveforms verifying the effect of compensating serious unbalance load.

(b) (CH1: source voltage v sa ; CH2: capacitor voltage vcu 2 ; CH3: capacitor
voltage v cu1 ; CH4: STATCOM line-current ica (1A/10mV)) Fig 21. Experiment waveforms verifying the effect of compensating balance load.

(CH1: source voltage v sa ; CH2: output voltage viu ; CH3: capacitor v cu1 ; CH4: STATCOM line-current ica (1A/10mV)) Fig 23. Experiment waveforms confirm the control effect when source voltage sag.

(a)
(CH1: source voltage v sa ; CH2: STATCOM line-current icb (1A/10mV); CH3: source side current i sa (1A/10mV); CH4: STATCOM line-current

ica (1A/10mV))

Fig.23 confirms the effectiveness of DC voltage control when source voltage sag happens. As is shown in fig.23, DC voltage keeps constant during the interval of source voltage sag, and the compensating current is not affected because of the source voltage feed forward. The DC voltage control method is effective when source voltage is either normal or sag.

Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

11 VI. CONCLUSION This paper has analyzed the fundamentals of DC voltage control based on cascaded hybrid multilevel H-bridge converters. And then, a hybrid modulation for hybrid multilevel converter has been proposed and the control algorithm has also been designed in details. The control scheme proposed in this paper is characterized by the capability of maintaining the unequal DC voltage at the given value without any additional circuit, as well as by the ability of compensating serious unbalanced load. This control strategy has taken full advantages of the available switching devices by operating the high-voltage device at low switching frequency and low-voltage device at high frequency. This control method along with the STATCOM system has the merits of producing high-quality output waveforms, reducing switching loss and improving whole systems efficiency. Experimental results obtained from a 100-V 3-kVA laboratory downscaled model have verified the effect of DC voltage control, dynamic performance of compensating seriously unbalancing load.
[14] Two-Level Inverters in series With a Capacitor-Fed H-Bridge Cell, IEEE Trans. Ind. Electron., vol. 57, no. 11, pp.3703-3714, Nov. 2010. Saad Mekhilef, Member, IEEE, and Mohamad N. Abdul Kadir, Voltage Control of Three-Stage Hybrid Multilevel Inverter Using Vector Transformation, IEEE Trans. Power Electron., vol. 25, no. 10, pp.2599--2606, Oct. 2010. Saad Mekhilef, Mohamad N. Abdul Kadir, Novel Vector Control Method for Three-Stage Hybrid Cascaded Multilevel Inverter, IEEE Trans. Ind. Electron., vol. 58, no. 40, pp.1339-1349, Apr. 2011. Martin Veenstra, Alfred Rufer, Control of a Hybrid Asymmetric Multilevel Inverter for Competitive Medium-Voltage Industrial Drives, IEEE Trans. Ind. Appl., vol. 41, no. 2, pp. 655-664, Mar/Apr. 2005. Farid Khoucha, Soumia Mouna Lagoun et al, Hybrid Cascaded H-Bridge Multilevel-Inverter Induction-Motor-Drive Direct Torque Control for Automotive Applications, IEEE Trans. Ind. Electron., vol. 57, no. 3, pp.892-899, Mar. 2010. Madhav D.Manjrekar, Peter K. Steimer, Thomas A. Lipo, Hybrid Multilevel Power Conversion System: A Competitive Solution for High-Power Applications, IEEE Trans. Ind. Appl., vol. 36, no. 3, pp.834-841, May/Jun. 2000. Alireza Nami , Firuz Zare, Arindam Ghosh, Frede Blaabjerg, A Hybrid Cascade Converter Topology With Series-Connected Symmetrical and Asymmetrical Diode-Clamped H-Bridge Cells, IEEE Trans. Power Electron., vol. 26, no. 1, pp.51--65, Jan. 2011. Mohamed Rashed, Christian Klumpner, Greg Asher, Hybrid Cascaded Multilevel Converter with Integrated Series Active Power Filter for Interfacing Energy Storage System to Medium Voltage Grids, in International Power Electronics Conference (IPEC) , Sapporo 2010, Japan, pp. 1236-1243, Jun. 2010. Zhong Du, Leon M. Tolbert, Burak Ozpineci, John N.Chiasson, Fundamental Frequency Switching Strategies of a Seven-Level Hybrid Cascaded H-Bridge Multilevel Inverter, IEEE Trans. Power Electron., vol. 24, no. 1, pp.25--33, Jan. 2009. L. A. Silva S. P. Pimentel J. A. Pomilio, Nineteen-level Active Filter System using Asymmetrical Cascaded Converter with DC Voltages Control, in Conf. Rec. 36nd IEEE Power Electron. Spec. Conf. (PESC), 2005, pp. 303--308. Shukai Xu, Qiang Song et al, Development of a D-STATCOM Prototype Based on Cascade Inverter with Isolation Transformer for Unbalanced Load Compensation, in Conf. Proc. Industrial Technology (ICIT), pp. 1050-1056, Dec. 2005. Laxman Maharjan, Shigenori Inoue, Hirofumi Akagi, A Transformerless Energy Storage System Based on a Cascade Multilevel PWM Converter With Star Configuration, IEEE Trans. Ind. Appl., vol. 44, no. 5, pp.1621-1630, Sep/Oct. 2008. Yingjie He, Du Si-xing, Liu Jin-jun, A study on the DC link voltage balancing for power conditioners based on cascaded H-bridges, in Conf. 8nd IEEE Power Electronics and ECCE Asia (ICPE & ECCE), pp. 1821 1827, May/Jun. 2011. P. P. Rajeevan, K. Sivakumar, Chintan Patel,Rijil Ramchand, K. Gopakumar. A Seven-Level Inverter Topology for Induction Motor Drive Using Two-Level Inverters and Floating Capacitor Fed H-Bridges, IEEE Trans. Power Electron., vol. 26, no. 6, pp.1733--1740, Jun. 2011. Malaya Kumar Sahu and Gautam Poddar. Transformerless Hybrid Topology for Medium-Voltage Reactive-Power Compensation, IEEE Trans. Power Electron., vol. 26, no. 5, pp.1469--1479, May 2011. Ding Li, Feng Gao, Poh Chiang Loh et al. Hybrid-Source Impedance Networks: Layouts and Generalized Cascading Concepts, IEEE Trans. Power Electron., vol. 26, no. 7, pp.2028--2040, July 2011. Jing Zhao, Yunlong Han, Xiangning He, Cheng Tan et al. Multilevel Circuit Topologies Based on the Switched-Capacitor Converter and Diode-Clamped Converter, IEEE Trans. Power Electron., vol. 26, no. 8, pp.2127--2040, July 2011. Jordan M. Henry and Jonathan W. Kimball. Switched-Capacitor Converter State Model Generator, IEEE Trans. Power Electron., vol. 27, no. 5, pp.2415--2425, May 2012. -

[15] [16] [17]

[18]

[19]

[20]

REFERENCES
[1] Wenchao Song, Alex Q.Huang, Fault-Tolerant Design and Control Strategy for Cascaded H-Bridge Multilevel Converter-Based STATCOM, IEEE Trans. Ind. Appl., vol. 57, no. 8, pp. 2700-2708, Aug. 2010. Chong Han, Alex Q. Huang, Mesut E. Baran et al, STATCOM Impact Study on the Integration of a Large Wind Farm into a Weak Loop Power System, IEEE Trans. Energ. Conv., vol. 23, no. 1, pp. 226-233, Mar. 2008. Akagi H Inoue S, Yoshii T., Control and performance of a transformerless cascade PWM STATCOM with star configuration, IEEE Trans. Ind. Appl., vol. 43, no. 4, pp. 1041-1049, Jul/Aug. 2007. Nobuhiko Hatano, Toshifumi Ise., Control Scheme of Cascaded H-Bridge STATCOM Using Zero-Sequence Voltage and Negative-Sequence Current, IEEE Trans. Pow. Del., vol. 25, no. 2, pp.543-550, Apr. 2010. Qiang Song and Wenhua Liu, Control of a Cascade STATCOM With Star Configuration Under Unbalanced Conditions, IEEE Trans. Power Electron., vol. 24, no. 1, pp.45--58, Jan. 2009. Ronny Sternberger, Dragan Jovcic, Analytical Modeling of a Square-Wave-Controlled Cascaded Multilevel STATCOM, IEEE Trans. Pow. Del., vol. 24, no. 4, pp.2261-2269, Oct. 2009. Alan J. Watson, Patrick W. Wheeler, Jon C. Clare, A Complete Harmonic Elimination Approach to DC Link Voltage Balancing for a Cascaded Multilevel Rectifier, IEEE Trans. Ind. Electron., vol. 54, no. 6, pp.2946-2953, Dec. 2007. Fang Zheng Peng, Jih-Sheng Lai, John W. McKeever, James VanCoevering, A Multilevel Voltage-Source Inverter with Separate DC Sources for Static Var Generation, IEEE Trans. Ind. Appl., vol. 32, no. 5, pp. 1130-1138, Sep/Oct. 1996. Y. S. Lai and F. S. Shyu, Topology for hybrid multilevel inverter,Proc. Inst. Elect. Eng.---- Elect. Power Appl., vol. 149, no. 6, pp. 449--458, Nov. 2002. M. Manjrekar and T. Lipo, A hybrid multilevel inverter topology for drive applications, in Proc. IEEE Appl. Power Electron. Conf., 1998, vol. 2, pp. 523--529. Cesar Silva, A Novel Modulation Technique for a Multilevel Hybrid Converter with Floating Capacitors, in Conf. 36nd IEEE Ind. Electron. Soc. Annu. Meet., 2010, pp. 296--302. Zhong DU, Burak Ozpineci, Leon M. Tolbert, John N.Chiasson, DC-AC Cascaded H-Bridge Multilevel Boost Inverter With No Inductors for Electric/Hybrid Electric Vehicle Applications, IEEE Trans. Ind. Appl., vol. 45, no. 3, pp. 963-970, May/Jun. 2009. K. Sivakumar, Anandarup Das, et al, A Hybrid Multilevel Inverter Topology for an Open-End Winding Induction-Motor Drive Using

[21]

[2]

[22]

[3] [4]

[23]

[24]

[5] [6] [7]

[25]

[26]

[8]

[27] [28] [29]

[9] [10] [11] [12]

[30]

[13]

Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.

12

Sixing Du was born in Nanyang, Henan, China. He received the B.S. degree in electrical engineering from Taiyuan University of Science and Technology, Taiyuan, China, in 2009. And then, He received the M.S. degree in electrical engineering from Xian Jiaotong University in 2011, where he is currently working toward the Ph.D. degree in electrical engineering. His main field of interest includes the hybrid multilevel, multilevel converter, power quality and the applications of power electronics in power systems.

Yingjie He was born in Henan Province,China in 1978.He received his B.S,M.S.and Ph.D.from the Huazhong University of Science and Technology, China in 1999,2003,and 2007,respectively. From May 2007 until May 2009, he was with the Power Electronics and Renewable Energy Center at Xian Jiaotong University, China, as a Postdoctoral Research Scholar. He is currently a Lecturer at Xian Jiaotong University. His research interest include power quality control, multilevel inverters and the applications of power electronics in power systems.

LIU Jinjun (M97-SM10 ) received his B.S. and Ph.D. degrees in Electrical Engineering from Xian Jiaotong University (XJTU), China in 1992 and 1997 respectively. He then joined the XJTU Electrical Engineering School as a teaching faculty. In 1998, he led the founding of XJTU/Rockwell Automation Laboratory and served as the lab director. From 1999 until early 2002, he was with the Center for Power Electronics Systems at Virginia Polytechnic Institute and State University, USA, as a visiting scholar. He then came back to XJTU and in late 2002 was promoted to a Full Professor and the head of the Power Electronics and Renewable Energy Center at XJTU. During 2005 to early 2010, He served as the Associate Dean for the School of Electrical Engineering at XJTU. Now he also serves as the Dean for Undergraduate Education at XJTU. He coauthored 3 books, published over 100 technical papers, holds 8 patents, and received several national, provincial or ministerial awards for scientific or career achievements and the 2006 Delta Scholar Award. His research interests are power quality control, renewable energy generation and utility applications of power electronics, and modeling and control of power electronic systems. Dr. Liu is an AdCom member of the IEEE Power Electronics Society and serves as Region 10 Liaison. He also serves as an Associate Editor for the IEEE TRANSACTIONS ON POWER ELECTRONICS. He is an AdCom member and the Chair of Student Activities Committee for IEEE Xian Section. He is on the Executive Board and serving as a Deputy Secretary-General for the China Power Electronics Society, and also on the Executive Board and serving as a Deputy Secretary-General for the China Power Supply Society.

Jiliang Lin was born in Anhui Province,China in 1984. He received his B.S.from the Northeast Dianli University of Automation Engineering ,China in 2007. And is currently pursuing the M.S degree in the school of Electrical and Electronic Engineering, Xian Jiaotong University, Xian. His research interest include power quality control, multilevel inverters and the applications of power electronics in power systems.

Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.