1016

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21, NO. 6, DECEMBER1986

A 12-bit Successive-Approximation-Type ADC with Digital Error Correction

KANTI BACRANIA,
MEMBER, IEEE

Abst~actA 12-bit successive-amnoximation-tvrseanalo~-to-di~ital . ... converter which uses a dlgitaferror correctiontechnique is presented. The correction afgoritbm gives almost a twofold improvement in conversion speed without loss of accuracy or changes to the analog circuitry of a slower design. This paper deseribes the design of a smart successiveapproximation register (Smart SAR) chip which has been fabricated in double-poly CMOS process and takes up 18K mi12 in die area. This is 13 percent larger than the A/D converterutiliiing tbe same analog chip but a conventional dlgitaf chip without error correction. A speed improvement from 12 to 7 ps with digital errorcorrectionhas been achieved.

.--

SUCCESSIVEAPPROXIMATION REGISTER

--

ANALOG INPUT + ~

r--kz=i
i I I I + . :OMPARATOR STATUS (t bz b3 . . a bl t OIGITAL OUTPUT bN J MSBTVT

? v

I.

INTRODUCTION

NALOG-to-digital conversion can be accomplished in numerous ways, but apart from flash converters, successive-approximation methods of analog-to-digital conversion are well known for producing accurate and high-speed conversion of an analog signal. The accuracy of conversion is mainly limited by the precision component matching in the digital-to-analog converter and the ability of the comparator to accurately resolve small voltages to yield a result of the difference between the analog input and the D/A output. The speed is directly related to the D/A settling time combined with the comparator settling time to some desired accuracy. The overall speed of a successive-approximation converter is determined by the amount of time required for the execution of each comparison step. Usually, sufficient time must be allowed prior to the next comparison step in order to permit the transient errors of the circuit to settle out to a necessary minimum level (typically to 1/2 LSB of final resolution) so that an accurate comparison can be made. This minimum time and the number of bits of a converter determine the minimum time for conversion of an analog input to a digital word. In the conventional successive-approximation converter, each bit decision made is also irrevocable, In the past, some converters [1], [2] included circuits which require complicated signal amplifiers and track and hold circuits which correct these errors at the expense of additional accurate analog components, die area, and slower speed due to added circuitry. Another approach [3] has been to use a low-resolution DAC with a R-2R type resistor ladder
Manuscript received May 1, 1986; revised July 17, 1986. The author is with the Anatog Division, Harris Semiconductor Corporation, Melbourne, FL 32901. IEEE Log Number 8610620.

Vo

N-BIT O/A CONVERTER

Fig. 1.

Conventional SAR-type A/D converter.

network which uses a radix of 1.85 instead of 2, i.e., R-1.85R. This approach, however, needs 17-bit DAC, EPROM, ROM, adder/accumulator, and an error correction cycle at package level which programs the EPROM. This paper describes a digital approach to error correction without extensive addition of logic circuitry or memory.

II.

THE SMART SAR CONCEPT

In a conventional A/D system (Fig. 1) if the settling-time characteristics of the D/A converter and the comparator combination are known to different levels of accuracy, then low-resolution decisions can be made on the higher order bits with an intent of digitally correcting the result at some point during the conversion. Since low-resolution decisions take shorter time than higher resolution decisions, the net result is a savings in conversion time.

III.

THE ALGORITHM

The new algorithm of successive approximation is based on the smart successive-approximation register (Smart SAR) concept. Using this concept, the first X bits of a 12-bit converter are successively approximated at a faster 01986 IEEE

0018-9200/86/1200-1016$01.00

BACRANIA: SUCCESSIVE-APPROXIMATION-TYPEAbC

1017

0.4
STARt 0.3

o
TRY
MSB #

0.2

KEEP/llEJECT

0.1

TRY , BIT8 o KEEP) EJECT R

DAC> V,a

DECREMEN1

A
CB1 DEC CB2 DAC> V,m DEC TRY BIT 9

0.1 0.0 CORRECTION CYCLE 1

1.0 TIME (MICROSECONDS)

2.0

3,0

DAC< V,n

Fig. 3.
INC INCREMENT

Plot of D/A converter and comparator settling.

O/A ANO COMPARATOR SETTLING VS TIME CORRECTION CYCLE 2 DAC< V,n -2,0 WAIT x - Measured P -4,() A 0 > ~ g -6.0

o
# TRY BIT 12

KEEP/REJECT

-8,0

CORRECTION ALGORITHM

-10.0 -00

1.0

2.0

3.0

TIME (MICROSECONDS)

Fig. 4. Fig. 2. Flowchart forcorrection algorithm.

Ln plot of D/A converter aad comparator settling.

IV. rate asallowable by the Xth-bit settling time of the D/A andl comparator combination. It is probable that during the first X bits of conversion, an error will be made on the bit decisions. However, after the Xth bit, the successive-approximation register (SAR) is allowed to enter a correction routine whose flow is shown in Fig. 2. During the first correction cyc Ie, the output ,of the D/A converter and comparator are allowed sufficient time to settle to 13-bit accuracy (to achieve 12 bits t 1/2 LSB) at which point the output of the comparator is examined. If the D/A output > Vi~~Ut >a single decrement of the X-bit word obtained before the correction cycle is carried out whereas if the D/A output < V,nput, a single increment of the X-bit word is carried out. After this, a second correction cycle is entered and again the D/A converter and comparator are allowed to settle to 13-bit accuracy. Again if the D/A output > Vi.~ul, a decrement of the X-bit word is carried out. However, if the D/A output is < Vi~PUt then no operation on the , X-bit word is carried out. At the end of the second correction cycle, the remaining bits are successively approximated to complete the conversion. Thus the whole conversion cycle requites a total of 14 clock cycles: 12 for successive approximation and two for correction cycles. The algorithm allows for up to 2 bits and +(1+ [(2(12-) 1)/(2(12-x) )]) bits of correction at X-bit level. The 2 bits are a direct result of the two decrements allowed in the algorithm and the +(1 + [(2(12-) 1)/(2(12))]) bits are the result of one increment and the remaining bits of the successive approximation.

THE

D/A CONVERTER AND COMPARATOR

CHARACTERIZATION

In order to determine the optimum place to introduce the correction cycles, the settling time of the D/A converter and compartor has to be known to various resolutions. Such an existing system with the D/A converter and comparator was characterized for settling time at 125C to obtain worst-case times for various resolutions. The results of this are shown in Fig. 3. The D/A converter reference voltage was 10.0 V with nominal & 15.O-V supply voltages. It can readily be seen that the curve has two distinct slopes to the first approximation in Fig. 3. The sharp vertical part of the curve shows that the main contributor is the D/A converter settling time whereas the horizontal part is dominated by the comparator settling time whose limitation is the overdrive at the input. In order to see the experimental results better, the settling times were plotted on a log scale as shown in Fig. 4. Further, a curve fit was carried out on these results and the following approximation resulted: y(f) =1.435 [exp(14.31*t)] where y(t)
t
is

+0.3257*10-3/t

(1)

in millivolts, and time given in seconds.

For a finite solution, t must be greater than zero. It can also be observed that this expression results in a fairly good agreement with the experimental results. Some deviation of the experimental data may be due to the

1018

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21, NO. 6, DECEMRER1986

second-order type settling of the system with a slight underdamping of the control amplifier. This was not conclusively proven to be due to the low-signal levels involved. V.
OPTIMIZATION

TABLE I D/A
AND COMPARATOR SETTLING TIME l=oR VARIOUS I@OLUTIONs

RESOLUTION (BITS)

SETTLING TIME T(X)/fs

The A/D converter is operated from a 1O-V on-chip voltage reference. This allows easy calculations of the voltages for each of the bit weights. For example, the required resolution of bitx=+

10v
2(X+1) 8.0

4 5 6 7 6 9 10 11 12 13

0058 0107 0158 0206 0252 0304 0358 0,409 0469 0539

Using numerical analysis and (l), the values of the settling time 1(x ) for the D/A and comparator to settle to x-bit solution can easily be derived and are tabulated for x from 4 to 13 in Table I. Note that the values are for settling time of the comparator and the D/A converter combination to + 1/2 LSB and do not include any logic delays in the SAR logic that controls the D/A converter switching, but do include the strobe delay of the comparator. The analog comparator has an active clamp circuit at the input which effectively clamps voltage excursions to plus and minus a diode. This helps the comparator in achieving a faster settling as long as the input is within the ~ diode limits. However, for larger voltages, a clamp turns on and adds to the overall settling time of the comparator. This condition of the clamp occurs only for bits 1 to 4 with decreasing amplitude at each successive bit. Furthermore, after the correction cycles, each increment or decrement of the correction cycle may cause a change of major carries which may cause a clamp to turn on. This problem is conventionally overcome by giving the MSBS a slightly longer time to settle. This was done by extending the relative bit times as follows: T(l) =1.3* T(x) T(2) =1.2* T(x) and correction cycles 1 and 2 settling time= T(13). Using this data and various settling times for other bits as derived in Table I, the conversion times for a 12-bit conversion with two correction cycles can be calculated by the equation: TC=(14*A)+ where
Tc A T(X)

1% .
H
o g z

6.0
A= LOGIC DELAY 5,0 2 4 6 8 10 12

Fig. 5.

12-bit conversion time versus correction bit placement.

The conversion times resulting by placing the correction cycles at various positions from bit 2 to 12 can be computed and are plotted as shown in Fig. 5. It can readily be observed that the minimum conversion time is achieved using correction cycles at bit 7 giving a conversion time of under 6.3 ps. In the actual circuit, the correction cycles were placed after bit 8 in order to simplify the input/output to 8- or 16-bit data bus structures. In a conventional A/D converter each bit decision is irrevocable, and thus to allow for worst-case settling of the DAC and the compartor, the minimum settling time allowed for any bit is 130 percent of the 13-bit settling time as indicated in Table I. Moreover the first two MSBS are extended as follows: bit l(t)s=2.O*(t),s bit2(t)s=l.5*(t)s (t)s=l.3*539ns. The overall conversion time Tc can be calculated by the equation: Tc=(13* where
Tc A

X* T(X)+

0.5* T(X)+

(14 X)* T(13) (2)

A)+ bitl(t)s

+bit2(t)s+ll*(i)s

().5 * T(X) (14- X)* T(13)

conversion time for 12-bit conversion, logic delay of the SAR per bit, settling time of bit X, extra time for bits 1 and 2, settling time allowed for bits after correction, and bit position before first correction cycle (X is an integer).

(t)s

conversion time for 12-bit conversion, logic delay per bit =120 ns, and 1.3 X539 ns.

Therefore Tc = 11.6 ps. Note that the logic delay in the conventional-type SAR is almost twice that of Smart SAR. This is because of the different clocking schemes used. The conventional SAR uses only the comparator signal to keep or reject a bit whereas the Smart SAR uses the clock and the comparator signal synchronously to keep or reject the bit.

BACRANIA: SUCCESSIVE-APPROXIMATION-TYPEADC

1019

yhv,u,

I L I--4
REFERENCE 1 I (MSB) El B2 B3 B4 B5 B6 B7 B8 B9 B1O Bll B12

12 BIT CUR RENT OUTPUTDAC I

COMPARATOR

(LSB)

l+
I
! CORRECTION! 10

COMPARATOR OUTPUT

I
B12 B1l B1O

-GATING
B9 cB2 CB1 B8 B7 B6 B5 B4 B3 B2 B1

1 1 CLOCK

I
,.

CLOCK cc.,co..rn,.c,.

,r,

1
,

1 CONVERT CONTROL START CONVERT

[
Fig. 6. Block diagram of the converter.

I ~ ENO OF

CONVERT

VI.

IMPLEMENTATION

The D/A converter, the 1O-V precision reference, and the strobed comparator are a subset of the chip used in a slower converter with 12-Ps conversion time. They are implemented in a high-frequency high-beta process using dielectric isolation. The chip is designed for operation over 55 C to + 125C with ~ l/2-LSB accuracy. The digital chip is fabricated using self-aligned junction-isolated CMOS (SAJI CMOS) process with 5-pm feature size. A simplified block diagram of the converter identifying the major blocks is shown in Fig. 6. The convert control logic is made up of random logic and contains an asynchronous controller to carry out the successive approximation. It interfaces to the bus and interrogates the various input commands such as 12-bit or 8-bit conversion and start conversion, and detects end of conversion. It also controls the output functions through READ control, allowing two 8-bit bytes, one 12-bit byte REm, or bus-enable/tri-state control. Both inputs and outputs are TTL/CMOS compatible. The 14-bit shift register, logic gating, correction logic, latches, and up/down counter form the Smart SAR which interfaces to the output buffers and the D/A converter inputs. The clock generator is a current-controlled oscillator whose precision reference current is derived from the analog chip. IJpon receiving a start convert command, the controller issues a master reset to the shift register, gating, counter, latches, and the oscillator. This reset sets the MSB of the 14-bit shift register to logic ONE and the rest of the bits to

i
S-R,% UP/LIOWN COUNTER

~JKcLK

GATING/ I I I CKL t I 14SITSH$FT~ REGISTERI 1 I

co

q
D

I
II -

l-l

I
I

on

I
,

DO

L 1 RESET + TO

I 4
TOD/A B2

4
TOEIIA 83

3 BITS OF SAR

Fig. 7. ZERO.

Gating functions for the SAR.

This logic ONE propagates through the gating and counter to set bit 1 (MSB) of the D/A converter high. At the same instant, the clock generator is enabled and the

1020
CB1> CLK

IEEE JOURNAL OF SOLID-STATE CIRCU2TS,VOL. SC-21, NO. 6, DECEMBER1986

*JKCLK CB2 > CQ >

JK CLK

q UP/DOWN

AA
Is 0s

Fig. 8. Correction logic.

SIMPLIFIED CLOCK GENERATOR

B1

L72 +V

CB2

1[ [1

PI

PI o i ?---l

P3

+-J

@J

p@-=-

. w mK

REF!i 1~ iEsETt
Fig. 9. Current-controlled oscillator.

reference current charges up a ramp-type oscillator. At a predetermined time of the first bit settling, a strobe pulse is issued to the comparator whose output is fed back into the logic gating which determines whether to keep or reject the bit. Synchronous to the clock, logic ONE is walked or shifted to bit 2 on the shift register and D/A converter bit 2 is turned on. The gating function is shown in Fig. 7. The Boolean functions are: set bit 1 reset bit 1 SI = reset
R~=clk. Q.+CQ clk . Q.

out for the first correction cycle. However, no increment is allowed during the second correction cycle. Also, during these correction cycles, the conditions when all bits are ZERO or ONE are detected. This is because no decrement should be allowed when all eight bits are ZERO and no increment should be allowed when all bits are ONE. The implementation of the correction logic is shown in Fig. 8. The conditions for decrement are
JKclk=DOWN [( CBlclk)+(CB2. elk CQ)]DS

and for increment JKclk=UP. where

DS

sn+l
where
n

[(CB1.elk)]

.1S

R .+l=clk

Qn+l+cQ

1S bit position of the shift registered, and comparator output.

decrement suppress, increment suppress,

CQ

The first eight bits are converted faster as shown in the algorithm. During this time the up/down counter which is made up of modified J K flip-flops is only used as a set/reset flip-flop. After bit 8, the two correction cycles are entered. At this point the J K flip-flops are switched to a synchronous counter mode. Based on the clock and the comparator output states, either a single decrement or an increment of the 8-bit word converted so far is carried

and UP and DOWN are derived from comparator output. At the end of the second correction cycle, the last four bits are converted successively with the same gating functions as the first eight bits except that the outputs are stored in the set/reset latches. At the end of the 14th clock cycle, end of conversion is detected and the clock is stopped by the controller. The requirements of the oscillator are fairly stringent to maintain the correct relationships between the periods. A simplified circuit of the oscillator is shown in Fig. 9.

BACRANZA: SUCCESSIVE-APPROXIMATION-TYPEADC

1021

RESET n MAIN RAMP STROBE CLOCK B1 n n B2 n n B3 n n n n n n B6 n-m n n B7 n n B8 CB1 n n cB2 n n 89 n n Blo n n Bll n n B12 n U

B4 B5

Fig. 10. Waveforms of the oscillator.

-z .: =

32

o m

z
N 16 -.

m. .

CORRECTION 8
8 b,t CONVERSION

WINDOW

. . ---~%LSB 1

0 \r .8 # P----= -42,s ~.;,,, DECISION (12 b,t) /

Q i.oo, CONVERSION (12 b,t)

-16 --

---------

-.

----.*

12 b,t CONVERSION MSB b!t DECISION -31 / w 600nS

1 CONVERSION

23456; INITIATED

TIME

(~S)

Fig. 11. Correction capability of the SAR.

ALreference current of 4(I pA is mirrored by PI to devices P2, P4, P6, and P8. Devices P3, P5, PI, and P9 steer the appropriate current to charge the capacitor. The master reset signal at the beginning of the conversion resets the capacitor and sets bit 1 high. A high ON bit 1 turns on P 9 thus enabling current flow through P8 and P9 to charge up the capacitor. At the same time the output of other bits is low, thus turning off the rest of the gates (P3, P5, and P7). Similarly, when bit 2 is high, P7 is enabled and when CB1 or CB2 or B9 B12 are high, P5 is enabled. Only one path at a time provides the current when none of the above bits are ON: the output of gate 4 goes low and enables P3 to conduct the current which gives the fastest ramp. To achieve the different periods, W/L ratios of devices P2, P4, P6, and P8 are designed to achieve the different charge current values for changing the ramp times on the capacitor. P1O is included for positive feedback to improve the transition point. The output of this stage feeds the circuit that generates the strobe signal for the comparator and the clock signal for the SAR. The waveforms at the main ramp, clock, and strobe are shown in Fig. 10. To achieve a tight tolerance of the conversion time the reference current feeding the oscillator is trimmed using a metal fuse scheme where the fuses on binary-weighted current sources are blown to achieve a desired conversion

time. The scheme allows a trim range, of +30 percent of conversion time to 6.75-ps + 300-ns accuracy. The output buffers are tristate with a minimum of one TTL load capability. Switching is guaranteed to be break-beforemake to avoid contention on the bus in the 2-byte READ mode. In order to minimize chip-to-chip noise injection, two primary design goals were established. First, the interface between the chips was current mode; that is, to turn a signal on, 300 PA was injected into the analog chip and to turn it off no current was supplied. This avoids the large voltage excursions encountered in voltage driven circuits and thus minimizes noise coupling between the chips. Second, the strobe pulse to the comparator is the first signal to switch at each bit period. At this point, the comparator is latched before any of the other pulses like delays and clocks are generated. This helps in avoiding noise feedthrough to the input of the comparator which may corrupt the decision-making process. VII.
THEORETICAL LIMITS OF CORRECTION

With this algorithm, the converter is capable of correcting up to 2 bits at 8-bit level ( = 32 LSBS at 12-bit resolution) and -I-(1+ ((24 - 1)/24)) bits ( = 31 LSBS at 12-bit resolution). The design also demanded that the

1022

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21, NO. 6, DECEMBER1986

ERROR CORRECTION
n

WINDOW

w+k..........
...!

/
; I [ 1 TIME CONVERSION

Fig. 12. Typical input to the converter.

converter maintain differential linearity to + 1/2 LSB of 12-bit resolution at under 7-ps conversion time. To achieve the benefits of the error correction, if the signal is perturbed during the first 8-bit cycle to within + 31/ 32 LSBS then the final answer should not change. The range of correction is shown in Fig. 11 and a typical input of a second-order type system is shown in Fig. 12.

VIII.

EXPERIMENTAL RESULTS

Using a computer system, the differential linearity of the converter was measured for all codes. A 16-bit D/A converter feeds the input to the converter. At each step of the 16-bit D/A, five measurements of the A/D outputs are made. The linearity plot of the results is shown in Fig. 13. The linearity is within + 1/2 LSB. A more conventional way of examining the dynamic performance of an A/D converter is shown in Fig. 14. This type of testing is described in [4] and [5]. The analog input voltage to the A/D converter is a triangle waveform which is superimposed on a dc voltage from a variable precision voltage reference. The rate of change of the triangle waveform is made small enough during each conversion period of the A/D converter so that a sample/hold circuit ahead of A/D is not required. Each conversion is initiated by a start convert command and the end-ofconversion signal is used to latch the output of the A/D into latches. This scheme updates the latches at the end of each conversion removing any synchronization problems. This test setup works on the principle that the two LSBS have a repeating binary code pattern output and if these two bits are connected to a 2-bit D/A converter then the output of the D/A converter will be a four-level staircase waveform. This output is fed to the Y input of the oscilloscope and the X input is the triangular waveform. A second Y input to the oscilloscope is derived from a switch which can be positioned to any of the output bits of the latches. This indicates the transition point of the bit with respect to the staircase. Fig. 15 (often called a dither plot)

shows the staircase with respect to the MSB transition. Any of the other major carries can be examined very simply by selecting the appropriate bit by the switch and varying the precision reference until a transition is observed. At this point the accuracy of the staircase waveform directly indicates the linearity of the A/D. Missing codes are always seen as missing staircase steps, or missing staircases. Uneven step widths are direct indications of linearity errors. More thorough treatment of the subject can be found in [6]. If a number of these staircase sweeps are averaged using an oscilloscope, with averaging capability, then a good indication of the transition noise with respect to each state width can be obtained directly by observing the steepness of the transition between the adjacent steps of the staircase waveform. A sharp transition indicates that the noise in the A/D converter is low and a softer transition means the noise level is higher. With a 1O-V reference to the converter, the theoretical correction range of 32 LSBS is approximately 78 mV. So if the analog input is perturbed by up to 78 mV from its final value during the first eight bits of conversion (i.e., up to the onset of the first correction cycle), then the output of the converter should be the digitized word representing the final value. For example, if the final value of the analog input to be converted is 2.50 V, then the digital word should read 0100 ..0 0. Now the input is perturbed around 2.50 V by approximately +39 mV up to the onset of the first correction cycle. The digitized output word should still be the same. If, however, the correction range is reached or exceeded the digitized output word will change. The perturbing signal at the input could be a dc source, noise, or even settling characteristics of the source driving the input. In order to test this correction capability and limit of the Smart SAR, a synthesized signal source with dc offset and amplitude modulation capability was used. The offset was set at 2.50 V for the second MSB transition. The perturbing signal was a 2.5-MHz sine wave with an amplitude of +10 mV riding on 2.50-V dc offset. The modulating signal was synchronized to the start-of-conversion pulse and its amplitude and duration were variable. The output word of the converter was sampled by a logic analyzer at the end of each conversion. At the start, the signal amplitude of +10 mV was 100-percent amplitude modulated for 500 ns and the output word of the logic analyzer observed. Gradually the duration of the modulating signal was increased from 500 ns to a point where the logic analyzer word changed from its 0100 . . . 00 value. This occurred at = 4 ps, which is the onset of first correction cycle. In order to be certain that the correction cycle is not corrupted, this pulse was reduced by 200 ns to E 3.8 ps. From this point on, the amplitude of the 2.5-MHz sine wave was increased gradually from +10 mV to a point where the logic analyzer word changed in value. This occurred at s +38 mV. This test established the maximum perturbation amplitude and duration allowable at the input of the converter which can be corrected. This is shown in Fig. 16, which shows the input as the top trace and conversion time as the bottom

BACRANIA : SUCCESSIVE-APPROXIMATION-TYPEADC

1023

STATE WIDTH TEST 2.25Input Ramp by H1-DACltI 5 repetitions at each DAC code Total Samples= 327099 Zero Frequency Codes= O Unit Number Z1

2- -

1.75.z . ~ x + a s 1.5-

1,25 --

.75

.5

to.,

,
.25 +

, ,
I
5i2

#
I I
1536 1024

,
2048

I
2560

I
3072

I
3684

ADC COOE

Fig. 13. A/D differential linearity test.

2.54V

44
START CONVERT PULSE .-. 11

1
AID CONVERTER I LSS 1!

ANALOG INPUT

2.50V

VINpUT

ENDOF CONVERT

2.46v -TCONVERSION

Fig. 16.
0 G 0 TO Y2 AXIS (BIT POSITIO%)

2.5-MHz amplitude modulated sine-wave input.

Fig. 14. Dynamic linearity test setup.

2.54V

STAIRCASE

2.50V

vlfJpIJT

2.46V BIT POSITION (MSB)

TCONVERSION

+5V-4LSB

111

Fig. 17.
+5V+4LSB

2.5-MHz amplitude modulated square-wave input.

+5 v

Fig. 15. Dither plot of the converter at MSB.

1024

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21, NO. 6, DECEMBER1986

2.54V

2.50V

INPUT

2.46V

1
Fig. 18. One cycle perturbation of the input.

CONVERSION

trace. Fig. 17 shows a similar test with a 2.5-MHz square wave. Fig. 18 shows just over one cycle perturbation of l-MHz sine wave at the input. Several other types of perturbing signals were used at the input and as long as the correction window constraints of amplitude and duration are satisfied, the converter was able to recover the error independent of the nature of the input. (The signals used in other tests were high-frequency noise, a step input, sine waves from 100-kHz to 4-MHz range, and delayed step inputs going positive and negative from the dc reference voltage.) IX.
CONCLUSION

The correction capability and the Smart SAR algorithm allow the conversion to start before the input has settled to its final 13-bit accuracy. This contributes directly to the system application performance of the converter. For example, a slower sample-and-hold can be used at the input. However, this does not reduce the conversion time of the converter, which is solely a function of the D/A converter, and comparator settling and the SAR timing. The digital circuit uses approximately 1800 devices and is fabricated using a standard 5-pm SAJI CMOS process with double poly for capacitors. A conversion time of under 7 ps is achieved using a current controlled oscillator and a fuse-trimmed timing circuit to adjust the reference current. Typical conversion times at 550 C and 1250C are 68 ps, respectively (1/2 LSB accuracy). The chip area of the digital die is 18K milz. A die photo of. the chip is shown in Fig. 19.

ACKNOWLEDGMENT

The design of a digital chip with a Smart SAR having digital error correction capability for a complete 12-bit A/D converter system has been shown. The digital error correction not only reduces the conversion time from 12 to 7 ps but also removes the need for the analog voltage at the input to settle to full accuracy before the conversion can begin as long as the input becomes stable at approximately 4 ps after the start of the conversion. Error correction capability and results are illustrated. The ability of the circuit to carry out a faster conversion of the first eight bits contributes directly to the reduction of conversion time.

The author would like to thank F. Cooper for his ideas, encouragement, and guidance, C. Garcia for his contributions to the analog circuit, R. Lomenick, J. Bordewin, and his staff for support during fabrication and testing, and A. Wood for layout of the circuits.

[1] R. E. Fletcher, Analogue to digital converters, U.S. Patent 3938

188. Feb. 10, 1976. [2] H. Kaneko, Bipolar analog to digital converter with double detection of sign bit, U.S. Patent 3735392, May 22, 1973, [3] Z. G. Boyacigiller, B. Weir, and P, D, Bradshaw, Au error correcting 14b/20uS CMOS A/D converter, in ISSCC, vol. XXIV, Feb. 1981. DD. 62-63. [4] A. Berg, A/D and D/A converter testing, Electron. Des., pp. 64-69, Apr. 1, 1974.

Fig. 19, Die photo of the Smart SAR.

BACRANIA: SUCCESSIVE-APPROXIMATION-TYPEADC

1025 He is currently a Principal Engineer in the Analog Division of Harris Semiconductor Corporati&, Melbourne, FL. He has been with the company for five years and has worked on digital controllers for A/D converters and highspeed A/D converters. Previously he had been with Burroughs Corporation and CPI, both in the U.K. His work there was related to magnetic recording, READ WRITE amplifiers, and data separators.

[5]

P. Havener, Catch missing codes, Electron. Des., pp. 58-64, Aug. 2, 1975. [6] J. R. Naylor, Testing digital/analog and analog/digital converters, IEEE Trans. Circuits Syst,, vol. CAS-25, pp. 526-538, July 1978.

Kanti Bacrania (M82) received the B.SC. degree (Hens) in physics/electronics from the University of Manchester, Manchester, U.K., and studied digital techniques at Henott-Watt University, Edinburgh, Scotlandj for the M. SC. degree.