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An Adaptive Equalizer With the Capacitance Multiplication for DisplayPort Main Link in 0.18- m CMOS
Won-Young Lee and Lee-Sup Kim

AbstractAn adaptive equalizer with the capacitance multiplication for DisplayPort main link has been proposed. The proposed equalizing lter is based on Millers theorem and composed of metal-insulator-metal capacitors and a sub-amplier. The active source degeneration capacitor achieves low cost and area saving with the capacitance multiplication. The equalizer satises the specication of DisplayPort version 1.1a. The measured eye widths of 2.7 Gb/s data are 0.6 and 0.5 UI for 5 and 8 m cables, respectively. The core area is 286 380 m and power consumption is 22.3 mW at 2.7 Gb/s at 1.8 V.

Fig. 1. Architecture of DisplayPort main link.

Index TermsAdaptive equalizer, capacitance multiplication, DisplayPort.

II. EQUALIZER IN DISPLAYPORT DisplayPort main link system consists of a link layer and a physical layer as shown in Fig. 1 [6]. The physical layer is further sub-divided into logical and electrical sub-blocks. The link layer of DisplayPort provides link and device management services over the auxiliary channel and isochronous transport services over the main link. In the physical layer, the electrical sub-blocks consist of a transmitter and a receiver for off-chip data communication and the logical sub-blocks provide link status monitoring and digital signal processing such as data scrambling/descrambling, ANSI8B10B encoding/decoding and etc. In a conventional adaptive equalizer, a varactor is widely used as source degeneration capacitors. However, a varactor is usually an additional plug-in module in CMOS process. Most blocks in a link layer and a physical layer except for electrical sub-block are composed of digital logics, which operate at a few hundred megahertz. Therefore, there is no need to use additional plug-in modules which are usually used as RF components. In addition, since a fundamental frequency of 1.35 GHz is relatively low, a conventional equalizing lter, which uses a varactor or a MOSFET capacitor as a source degeneration capacitor, occupies large area to make pole/zero near the fundamental frequency. This also increases the cost for fabrication. Recently in display interfaces, an adaptive equalizer for high-denition-multimedia-interface (HDMI) system has been reported in [5]. The data rate of HDMI is 2.25 Gb/s which is similar to DisplayPort. Against low-cost cables of different lengths, the adaptive equalizer automatically detects and compensates for the channel loss by comparing the energy ratio in high frequency and low frequency bands of the equalized signal with a self-generated energy ratio. The power consumption and the occupied area, however, are large compared to others due to the use of SiGe BiCMOS technology. This paper presents an adaptive equalizer with an active source degeneration capacitor which consists of an amplier and MIM capacitors. The active source degeneration capacitor achieves low cost and area saving with the capacitance multiplication and the proposed equalizing lter widens the compensation range with the active source degeneration capacitor. As a result, the proposed equalizer effectively compensates for ISI with various cable lengths.

I. INTRODUCTION In large display units, the wide bandwidth of display interfaces is required as the physical size, the resolution, and color depth of a at panel display increase. Although the data rate of display interface is lower than that of optical interface, there is power attenuation of the data at high frequencies because of the non-ideal effects and long length (maximum 15 m) of a copper cable. To overcome inter-symbol interference (ISI) due to the channel loss, several solutions for a transmitter and a receiver have been reported [1][5]. Adaptive equalization is an effective solution to compensate for high frequency loss of the data. Generally, a varactor or a MOSFET capacitor has been used as a source degeneration capacitor in adaptive equalizers. In display interfaces with 1 to 3 Gb/s data rate, a conventional equalizing circuit with a varactor as a source degeneration capacitor [3] consumes large area to make pole/zero at a fundamental frequency and increases the cost by using additional plug-in modules. In case of the MOSFET capacitor [4], to widen its narrow tuning range, a capacitor bank is needed, which also increases the circuit area. This work reports an adaptive equalizer with an active source degeneration capacitor which consists of an amplier and metal-insulator-metal (MIM) capacitors. The active source degeneration capacitor achieves low cost and area saving with the capacitance multiplication and the proposed equalizing lter with the active source degeneration capacitor widens the compensation range, as a result, it effectively compensates for ISI with various cable lengths. Section II explains the unsuitability of a conventional equalizing lter in DisplayPort. Section III presents the proposed equalizing lter and the implementation details. Section IV discusses the simulated results and the measured results are presented in Section V. Finally, Section VI concludes this paper.
Manuscript received October 13, 2010; revised January 20, 2011; accepted March 12, 2011. Date of publication April 07, 2011; date of current version April 06, 2012. This work was supported by Basic Science Research Program through the NRF of Korea funded by the MEST (2010-0000798). Fabrication support was provided by IDEC, Korea. W.-Y. Lee and L.-S. Kim are with the Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-701, Korea (e-mail: wylee@mvlsi.kaist.ac.kr; lskim@ee.kaist.ac.kr). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TVLSI.2011.2130546

III. CIRCUIT DESCRIPTIONS Fig. 2 shows the overall architecture of an adaptive equalizer. The feedback architecture in [2] is adopted to effectively compensate power loss of incoming data. The received input data goes through an equalizing lter and the equalizing lter roughly compensates for power loss at high frequencies with the initial lter gain. An active variable capacitor is used instead of a varactor or a MOSFET capacitor as a source

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Fig. 4. Small signal model of the active source degeneration capacitor.

MIM capacitors and a sub-amplier which is composed of M6 to M15 are used to control the high frequency gain boosting instead of varactors provided in RF process. This amplier and two MIM capacitors are connected in feedback. The proposed scheme is based on the capacitance multiplication by Millers theorem [7], [8]. The effective source degenerative capacitance, Ce , is given by
Fig. 2. Proposed adaptive equalizer with an active source degeneration capacitor.

Ce

Cs (1 0 K )

(1)

where K is the amplier gain. Since the circuit is balanced, the characteristics of the circuit can be predicted through analysis of the half circuit in Fig. 4. Assuming that Cs is zero, Vout s =Vin s and Voutb s =Vinb s are given by

Vout s Vin s

Voutb s Vinb s

= gm6 gm14

Ro1 k

sCo1

R5 k

sCo2

(2)

where Ro1 is the output resistance varied by the control voltage (Vctrl ), each Co1 and Co2 is the load capacitance which includes the intrinsic capacitance of the circuit and gm6 , gm14 , and R5 are equal to gm7 , gm13 , and R4 , respectively since the circuit is balanced. The gain (K = Voutb s =Vin s ) in (1) can be expressed as follows:
1 gm6 gm14 Ro1 k sC Vin 1 R5 k sC

K=
Assuming Vin by

Vinb s

s s =

(3)

s =

 1 sin(!t) and Vinb

0 1 sin(!t), K is given
1 1 + !s

K = 0gm6 gm14 Ro1 R5

Fig. 3. Circuit-level schematic of the proposed equalizing lter.

1+s

(4)

where

!p1 =
degeneration capacitor in the equalizing lter. The output of the equalizing lter (A) is fed into a slicer. The input data and the output data of a slicer (B) pass through the high-pass lters and the low-pass lter, then rectiers and V/I converters compare the power spectral densities of the ltered signals. The average power of high frequencies (Vcont high ) is fed into the equalizing lter to compensate for the high frequency loss of a channel and the average power of low frequencies (Vcont low ) adjusts the gain of the slicer by changing pull-up loads. A. Proposed Equalizing Filter The schematic of the proposed equalizing lter is illustrated in Fig. 3. In the proposed equalizing lter, a main amplier consists of M1 to M4 . This amplier adopts a tunable source degeneration resistor (R3 and M5 ) and the active capacitor (sub-amplier and MIM capacitor).

Ro1 Co1

; !p2 =

R5 Co2

(5)

Therefore, Ce can be expressed as

Ce

Cs

1 + gm6 gm14 Ro1 R5

1 1 + !s

1 1 + !s

: (6)

Since Ro1 is the variable resistance, Ce is also variable. Thus, the proposed equalizing lter uses this characteristic to control the peak gain boosting. To make Ce frequency-independent, a sub-amplier should have the wide bandwidth over the data rate. In other words, !p1 and !p2 should be placed far away from the Nyquist frequency of the data rate as possible. The 3-dB frequencies of the sub-amplier are from 3.4 to 1.9 GHz with control voltages from 0 to 1.1 V. In the active source degeneration circuit, the right half plane (RHP) zero yielding a phase of 0 tan01 (!=!z ) exists due to miller capacitance. However, since there is also a left half plane (LHP) zero, it somewhat cancels out

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Fig. 5. Tuning range of the two-stage sub-amplier gain at 1.35 GHz.

Fig. 7. Schematic diagram of the slicer composed of ve stage buffers.

Fig. 6. (a) Input waveforms and (b) output waveforms of a two-stage subamplier with varying the amplier gain.

Fig. 8. Simulated frequency response of the proposed equalizer.

the effect of the phase degradation due to the RHP zero. The simulated phase margin is about 30 degrees for 45 cases of variations. This margin is not good but able to make the system stable. Since the dynamic range of Vctrl is limited due to the threshold voltage of a MOSFET, diode-connected MOSFETs (M9 and M12 ) are necessary to avoid the amplier malfunction. The tuning range of a two-stage sub amplier is shown in Fig. 5. The minimum gain is 4.36 dB and the maximum gain is 16.16 dB at 1.35 GHz. Actually, since the input power difference between a main amplier and a two-stage sub-amplier is 06.4 dB due to the gate-source voltage drop, the two-stage sub-amplier operates well without the output saturation as depicted in Fig. 6 assuming the received data of the adaptive equalizer does not exceed about 400 mVpp . Thus, a pre-buffer whose maximum output swing is limited under 400 mVpp by a replica bias circuit is placed before the equalizing lter. B. Slicer Fig. 7 illustrates the slicer composed of cascaded ampliers. The slicer sharpens rising and falling edges of data from the equalizing lter. The slicer requires high gain and wide bandwidth characteristics. The natural bandwidth of the designed buffer decreases when buffers are cascaded [9]. Therefore, an effort to nd optimum numbers of buffers is required. In [9], the relationship between the total gain of cascaded ampliers (Atotal ) and the optimum stage number (Nopt ) with the maximum bandwidth has been described as

IV. SIMULATION RESULTS Fig. 8 shows the simulated frequency response of the proposed equalizer. When the high frequency component of the received signal is attenuated by channel loss, the control voltage of an equalizing lter goes up to increase the amount of high frequency component relative to low frequency component. The high frequency gain boosting of the equalizer has been designed on the basis of channel models depicted in Fig. 9. The cable model is frequency-independent but lumped into 20 segments. The each cable model has been designed as compared with measured S-parameters. The simulated S21 results of channel models are shown in Fig. 10. As the frequency increases, it is noticed that the magnitude error between the simulated and the measured S21 also increases. Actually, since the resistance and the inductance of a coaxial cable are frequency-dependent, the frequency-independent lumped cable model necessarily has errors in spite of dividing into 20 segments. DisplayPort main link should support two data rates, such as 2.7 and 1.62 Gb/s and there are various cable lengths. This means that variable channel losses exist due to the frequency-dependency and the cable length-dependency of channel loss. For example, in the case of 1.62 Gb/s data communication with a short cable, high frequency loss of incoming data is small. If the equalizer cannot support a wide range of compensation, jitter of the equalized data increases due to overcompensation by the equalizing lter. Therefore, the equalizer should have a wide range of the loss compensation, but the wide tuning range of the capacitance can hardly be obtained using a varactor or a MOSFET as the source degeneration capacitor unless a large capacitor bank is used. The simulated frequency response of equalizing lters with various source degeneration capacitors is presented in Fig. 11. The black line (Gaindi ) represents the difference of the low frequency gain and

Nopt = 2 ln Atotal :

(7)

According to (7), the slicer is designed with ve buffer stages where the total gain is 26 dB; each buffer gain is about 4.3 dB.

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TABLE I PERFORMANCE SUMMARY

Fig. 9. DisplayPort cable model; a unit segment of a 5 m cable and an 8 m cable. Fig. 11. Comparison of frequency responses with various source degeneration capacitors.

Fig. 10. Measured and simulation results of S

for variable cable lengths. Fig. 12. Source degeneration R/C layout using: (a) the proposed circuit; (b) a varactor; and (c) a MOSFET capacitor.

the boosted high frequency gain. A MOSFET capacitor, a junction varactor and the active source generation capacitor are used as the source degeneration capacitor. For the comparison, the same circuitries except for source degeneration capacitors in the equalizing lter are used for each simulation. The parameters of a junction varactor and a MOSFET capacitor are selected such that the high frequency gain boosting is at 1.35 GHz and the locations of zeros are about 135 and 300 MHz for a varactor and a MOSFET capacitor, respectively. The di of the lter with a varactor is the largest among them but its variation by the control voltage di is smaller than the proposed scheme. di of a varactor and the proposed scheme is 14.5 and 18.9 dB, respectively. The di of the lter with a MOSFET capacitor shows the nonlinearity problem as reported in [10], [11]. Fig. 12 shows physical dimensions of the source degeneration capacitors and resistors which are used for the frequency response simulation shown in Fig. 11. The lter circuit with varactors in Fig. 12(b) occupies the largest area of 3422 m2 approximately. The MOSFET lter in Fig. 12(c) has an advantage of small area but has the critical problem of the nonlinearity as shown in Fig. 11. Therefore, it is noticed that the proposed equalizing lter occupies small area and has wide and linear compensation range compared to others. However, the net power consumption increases due to an additional amplier. Total additional power consumption is 3.06 mW where a single two-stage sub-amplier consumes

Gain

1Gain

(1Gain ) Gain

765 W (simulated). There is a tradeoff between the additional power consumption and compensation range of the equalizer. Since the amplier controls the coefcient of the degeneration lter, the active source degeneration lter has wider linear compensation range than passive elements. The 1.62 Gb/s data, the reduced bit rate (RBR) in DisplayPort, is less affected by ISI. In this case, the equalizer reduces the gain boosting to about 0 as shown in Fig. 11 and can operate as a limiting amplier. V. EXPERIMENTAL RESULTS The proposed adaptive equalizer is designed for DisplayPort main link. According to DisplayPort specication [6], 2.7 Gb/s and 1.62 Gb/s 7 0 PRBS data patterns are used. DisplayPort cables of 5 and 8 m lengths are used as the data channel. Fig. 13 shows that 2.7 and 1.62 Gb/s data have suffered large power loss with 5 and 8 m cables. After adaptive equalization, the eye of output is widely opened compared to the non-equalized data. The eye width of 2.7 Gb/s data is 0.6 and 0.5 UI for 5 and 8 m cables, respectively, and the eye width of 1.62 Gb/s data is 0.7 and 0.6 UI, respectively. As shown in Fig. 14, the eye width of 0.52 UI is obtained at the BER of 09 for 2.7 Gb/s data through the

2 1

10

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Fig. 13. PRBS 2

0 1 eye diagrams of the received data and the equalized data for (a) 2.7 Gb/s rate and (b) 1.62 Gb/s rate.
lengths. A chip is fabricated in a 0.18 m CMOS process. The proposed adaptive equalizer shows the eye width of 0.52 UI at the BER of 1009 and 2.7 Gb/s data mode.

REFERENCES
[1] A. J. Baker, An adaptive cable equalizer for serial digital video rates to 400 Mb/s, in IEEE ISSCC Dig. Techn. Pap., 1996, pp. 174175. [2] S. Gondi, J. Lee, and B. Razavi, Equalization and clock and data recovery technique for 10-Gb/s CMOS serial-link receivers, IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 19992011, Sep. 2007. [3] J. Choi, M. Hwang, and D. Jeong, A 0.18-m CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method, IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 419425, Mar. 2004. [4] T. S. Kao, F. A. Musa, and A. C. Carusone, A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 11, pp. 28442857, Nov. 2010. [5] H. Liu, I. Mohammed, Y. Fan, M. Morgan, and J. Liu, An HDMI cable equalizer with self-generated energy ratio adaptive scheme, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 7, pp. 595599, Jul. 2009. [6] DisplayPort Standard, Version 1.1, Video Electronics Standard Association, 2007. [7] G. A. Rincon-Mora, Active capacitor multiplier in miller-compensated circuits, IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 2632, Jan. 2000. [8] Y. Tang, M. Ismail, and S. Bibyk, Adaptive miller capacitor multiplier for compact on-chip PLL lter, IET Electron. Lett., vol. 29, no. 1, pp. 4345, Jan. 2003. [9] B. Razavi, Design of Integrated Circuits for Optical Communications. New York: McGraw-Hill, 2002, pp. 123129. [10] R. L. Bunch and S. Raman, Large-signal analysis of MOS varactors in CMOS LC VCOS, IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 13251332, Aug. 2003. [11] M. A. Fathimulla, Varactor, U.S. Appl. 2006/0125012, Jul. 15, 2006.

Fig. 14. Bathtub curve of the 2.7 Gb/s equalized data.

Fig. 15. Die photograph of the adaptive equalizer.

5 m cable. The proposed adaptive equalizer has satised the specication of 0.47 UI eye width with the BER of 1009 for 2.7 Gb/s data [6]. A chip is fabricated in a 0.18-m CMOS process. A die photograph is shown in Fig. 15. The core circuit without output buffers consumes 22.3 mW at 2.7 Gb/s from 1.8-V supply and occupies 286 2380 m2 . The performance summary is given in Table I. VI. CONCLUSION An adaptive equalizer with the capacitive multiplication has been presented. The active source degeneration capacitor is composed of MIM capacitors and an amplier. The proposed equalizing lter with the active source degeneration capacitor widens the compensation range, so that it effectively compensates for ISI with various cable