Automatic Layout Synthesis for FIR Filters Using a Silicon Compiler

Masaki ISHIJSAWA, Masato EDAHIRO, Takeshi YOSHIMURA, Takashi MIYAZAKI, Shin-ichi AIKOHt, Takao NISHITANI, Kaoru MJTSUHASHIi, Mitsuhiro FURUICHI':
C&C Systems Research Laboratories, tR&D Planning and Technical Service Division, $System LSI Development Division, NEC Corporation 4-1-1, Miyazaki, Miyamae-ku. Kawasaki 213, JAPAN

Abstract

A silicon compiler for FIR filters is presented. Unlike existing silicon compilers for designing Digital Signal Processor (DSP) chips, which need descriptions for signal processing al-

gorithms as inputs, the synthesis system takes as inputs only filter specifications and processing word lengths, and generates the FIR filter mask pattems in a few minutes. The system consists of two programs: an FIR filter design program to determine FIR filter coefficients at the minimal filter order to meet design objectives and a module generator to generate mask pattems, according to optimal parameters obtained by the filter design program. For describing layout structures correctly and easily, the module generator provides graphical layout description tools and includes mechanisms to permit designing the structures before leaf-cells are completed. Layouts for several filters have been successfully generated in a short time. A single chip VLSI chrominance/luminance separator for NTSC composite TV signals employing four FIR filters generated by the system is shown.

This paper presents a silicon compiler for FIR filters, which are commonly included in fast video signal processors as a special hardware. In this system, the inputs are the system-level specifications. Since the abstraction for the chip design reaches a higher level, the algorithm descriptions become unnecessary, and therefore, the chips are easier to design and can be designed in a shorter period of time. The system starts from system-level specifications, such as filter specifications, coefficient word lengths, etc., and generates the FIR filter mask pattems in a few minutes. The following sections explain the system configuration and two major programs in the system: an FIR filter design program and a module generator. Finally, layout results and a micro-photograph of the developed VLSI chip are presented.

2 System Configuration
The proposed system consists of two major programs: an FIR filter design program and a module generator. The system configuration and data flow are shown in Fig.1. The input data for designing an FIR filter are only filter specifications and word lengths for the filter, as follows:

1 Introduction
With the increase in the complexity and density in V U 1 chips, the design costs for the development of a VLSI chip have been rapidly increasing. System designers, who are generally inexperienced in IC design and processing technology, now need to design VLSI chips, because whole systems can be realized on a single chip. To solve the VLSI design crisis and allow system designers to design VLSI chips, silicon compilers have become attractive. Many silicon compilers using different approaches have been proposed in the past decade[l][2]. These systems can be classified into the following two groups: Silicon compilers for general architectures. Silicon compilers for target architectures. Silicon compilers for general architectures, which usually have high-level description languages and consist of a high-level synthesizer, a logic synthesizer and an automatic layout system, can generate various layouts from high-level descriptions. However, the performance, such as size and operation speed of synthesized chips, is often much worse than that achieved by manually designed chips. On the other hand, silicon compilers for target architectures are expected to generate efficient layouts, although the chip architecture. is restricted. So far, several silicon compilers for designing Digital m Signal Processor(DSP) chips have been proposed[3]-[7]. S' e many of the systems require descriptions for signal processing algorithms, chip designers need to write the descriptions in special high-level languages.

Filter types. Filter mecifications. Word lengths.

7
FIR filter design program

J .

Architecture. Filter coefficients. Filter order.

[Mask pattern
Fig. 1 System configuration

CH2868-8/90/0000-2588$1,@31990 IEEE 0

Filter types: low-pass, high-pass, band-pass, band-stop and multi-band Filter specifications: cut-off frequency, pass-band ripple, stopband attenuation, etc. Word lengths: input, output, intemal and coefficient The FIR filter design program starts with these data, accomplishes an optimal design and generates the following parameters for layout design by using the module generator. Filter architectures and specifications Filter order
o

( Example )

-36

+
I I

11011100

1
00~00lp0

Filter coefficients

(jGz&)
Fig. 2 Representation of coefficients

The module generator generates mask patterns for the FIR filters, according to the parameters described above. The module generator has several layout structures for FIR filters in the database. The FIR filter design program selects a layout structure for optimal filter design, and the generator makes mask pattems, by using the layout structure.

4 Layout generation by a module generator

The proposed module generator can accomplish placement of leaf-cells and routing between the cells, according to layout descriptions for the target functional moddes[lO]. In addition to these basic functions, the generator has the following two features for describing layout structure.

3 FIR filter design program

The FIR filter design program automatically designs FIR filter coefficients at a minimal filter order by using the McClellan et al. algorithm based on the Remez Exchange Algorithm[8][9]. The design is canied out according to input data, such as cut-off frequency, passband ripple, stop-band attenuation, coefficient word length, etc. This program makes it possible to design optimal FIR filters without much expertise. Several initial values for the Remez Exchange Algorithm are determined automatically according to the input data, because it is difficult for inexperienced filter designers to set suitable initial values. First, FIR filter coefficients are calculated by using the algorithm. If the coefficients do not satisfy the desired filter specifications, the filter order is increased and coefficients are calculated again. If the coefficients satisfy the specifications, the coefficients are rounded off to given word length(e.g. 8 bits) and checked again to determine whether the desired specifications are satisfied by those values. If the rounded off values satisfy the specifications, those coefficients and filter order are derived as parameters for layout generation, using a module generator. When coefficients are rounded off, the Canonical Signed-digit Representation (CSR) is used to decrease non-zero digits. CSR can represent any N-bit number with less than or equal to N/2+1 non-zero digits by allowing 0, 1 and -1 weights to each digit. For example, 127 and -73 in decimal form can be represented in 8 digit CSR by 1000000~ and O ~ O O l O O ~ respectively, although they are expressed as 01111111 and 10110111 in 8 bit binary code. Here, means -1 weighting in CSR. Decreasing non-zero digits by the CSR results in reducing the number of shift and add operations for a multiplication. In the filter design for the chrominance/luminance separator chip, limiting the maximum numbers of non-zero digits to 3 for 8-bit fixed coefficients, each multiplier used in the filter can be simply realized by three shift and add operations using three adders, inverters and/or selectors. This simplified and regular structure is effective in layout design using a module generator. Figure 2 shows coefficients representation on a filter layout. Coefficients in CSR are ultimately represented with wired logics on layout.

J. Layout description with graphical interface and C language

2. Layout description with temporary cells
Individual features for the layout description aTe discussed in detail in the following sections.

4.1 Layout description with a graphical interface and C language

Layout structures can be described by the following two methods:

1. C language 2. Graphical interface

More than 50 functions in C language, called layout functions, are prepared to describe the layout s t ~ ~ c t u r e s . Layout functions include functions not only for absolute/relative cell placement, but also for making a netlist for automatic routers. Using these functions and control statements in C, such as for, if then, case, etc., any layout structures can be described. Since cells have various sizes and terminal positions in practical layout designs, it is quite difficult to describe legal topological relationships among cells on texts. In addition, layout descriptions axe often error-prone. To describe correct layout structures easily, graphical tools to draw the layout structure are provided. Using commands on the graphic display, various relationships between cells w t arbiih traq sizes and terminal positions can be described. Each command assures legal relationships between two cells. Layout structures can be checked visually and layouts can be modified easily on the graphic display. Figure 3 shows the system configuration for the proposed module generator. As described above, layout descriptions can be made by using a graphical interface. These graphic layout descriptions are transformed into intermediate forms automatically. The layout description environment is set up from the intermediate forms, by using a command sequence generation program. The intermediate forms, which have been made previously and stored in the database,

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can be used to make a new layout structure on the graphic display. The intermediate forms are interpreted to layout descriptions in C language, by using layout functions. The descriptions can be modified in the C language, if necessary. Moreover, it is effective to describe logical information, such as ROM pattems, PLA pattems, etc., directly in the C language, which is difficult to be represented on graphics. Parameten can be set at any stage on the module design, as shown in Fig.3. Figure 4 shows an example of layout descriptions on graphic displays. Parameters and temporary values for them can be set on panels, as shown in the figure. Layout structures are made by using these parameters.

In the proposed generator, layout structures can be described using temporary cells, and after the actual cells are designed, mask pattems are generated, by using actual cells as follows (shown i n Fig.5):
Design temporary cells on graphics. Describe layout structures with temporary cells. Note that the layout structures should be described, by using relativeplacement commands (or functions) for leaf-cells, since the size of the temporary cells is not equal to the corresponding actual cells. Make case files, which represent the correspondencebetween temporary cells and actual cells.

,
sequence gen.

& & 1

*(Graphical interface

............ ............

After completing the actual cell design, choose a case file and generate the mask patterns. Several mask patterns with actual cells can be generated, according to the relationship between temporary cells and actual cells on the case file.

Intermediate forms generator

Layout generator ............ ............

Data flow

Operation flow

r..l.;l-.-y
cayout description

Describe layout structure with temporary cells

, ,

\I

Map temporary cells to actual cells

CASE-1

Fig. 4 Layout structure descriptions using a graphical interface Fig. 5 Layout generation with temporary cells

4.2 Layout description with temporary cells

Many existing cell-based module generators assume that leafcells are prepared or generated before making the layout descriptions. In actual chip designs, however, leaf-cells are often completed after the layout descriptions are made. In this case, it is necessary to describe layout structures using temporary leaf-cells: the size and terminal positions of temporary cells may be changed. Moreover, many of the leaf-cells in the modules are sometimes replaced in the same layout structure, when the parameters are changed. It is difficult to describe such layout structures with a usual layout description language.
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5 Results
Three kinds of FIR filters have been designed using the system, as shown in Table 1. Structures for these filters fall into two categories: one is for the symmetric coefficient FIR filter and the other is for FIR decimation filters. A band-pass filter for color signals, called CBPF, has been designed with the symmetric coefficient FIR filter structure, and two low-pass filters for color signals and a low-pass filter for luminance signals, called CLPFs and YLPF respectively,

have been designed with the FIR decimation structure. Decimation rates for the CLPFs and the YLPF are 1/4 and 1/2, respectively. The entire filter design process takes from 200 to 400 seconds on an NEC EWS4800 workstation (3.2 Mips), depending on the filter order for the filter. The basic layout structures, which consist of leaf-cells, such as inverters, adders, selectors, flip-flops, etc., were designed, by using a graphical interface with temporary cells described in the previous section. Filter coefficients are represented with wired logic on layouts. Layout structures for basic structures and the wired logic were written in C language, and stored in a database in a parameter expansible format. By using the system, fast and error-free VLSI development was realized. Figure 6 indicates the layout produced for a CLPF. Figure 7 is a micro-photograph of chrominance/luminance separation VLSI Table 1 Produced FIR filters

chip for NTSC composite TV signals at 13.5 MHz CCIR standard sampling rate. Four FIR filters, which are major functional modules in the chip, were designed, using the system. The VLSI chip was fabricated in 10.4 x 11.7 die size, using 1.2pm CMOS technology, and achieves about 860 MOPS ( Million Operations Per Second) operation speed.

6 Conclusion
A silicon compiler for FIR filters and a chrominance/ luminance separation VLSI chip, employing four FIR filters generated by the synthesis system, have been presented. Starting &om filter specifications, such as cut-off frequency,pass-band ripple, stop-band attenuation and coefficient word length, the synthesis system generates optimal filter mask pattems correctly in a short time. The module generator, which accomplishes layout design in the system, provides graphical layout description tools and includes mechanisms to permit describing layout structures before leaf-cells are completed. The synthesis system can be used by system designers who are inexperienced in filter design and LSI chip design, because the system requires only filter specifications and processing word lengths to generate the target filter.

1 Name 11
CLPF YLPF CBPF

I Fil. ord. I *DR 1 Num. 1 Function 15 114 2 LPF for color signals 19 1/2 1 LPF for luminance signals 15 1 1 BPF for color signals

*Decimation Rate

Acknowledrrments
The authors would like to thank T. Ishiguro, A. Morino, S. Goto, K. Watanabe, B. Hirosaki, Y. Nagai, H. Nakamura and M. Hirata for their continuous encouragement and valuable suggestions.

References
D. Gajiski, Silicon compilation, Addison Wesley, 1987. Fig. 6 Produced layout (CLPF)

G. De Micheli, et al., Design Systems for VLSI Circuits: Logic Synthesis and Silicon Compilation,Martinus Nijhoff, 1987. P. Denyer, et al., A Silicon Compiler for VLSI Signal Processors, Proc. ESSCIRC 82, pp. 215-218, 1982.
M. Glesner, et al., A Flexible Silicon Compiler for Digital Signal Processing Circuits, Proc ICCD84, pp. 845-850, 1984.

H. De Man, et al., Cathedral-D. A Silicon Compiler for Digital Signal Processing, IEEE Design & Test, pp. 13-25, Dec. 1986.
J. Rabaey, et al., An Integrated Automated Layout Generation System for DSP Circuits, IEEE Trans. CADDCAS, vol. CAD-4, no. 3, pp. 285-296, 1985. J. Schuck, et al., The ALGIC Silicon Compiler System: Implementation, Design Experience and Results, Proc. 24th DAC, pp. 370-375, 1987.

T. Miyazaki, et al., A Single Chip Chrominance/ Luminance Separator Based on a Silicon Compiler, Proc. ICASSP89, 1989.
J. McClellan, et al., A Computer Program for Designing Optumum FIR Linear Phase Digital Filters, IEEE Trans. Audio Electroacoustics, AU-21-6, 1973.
Fig. 7 Chrominance/luminance separator chip micro-photogragh

M. Ishikawa, et al., A New Module Generator with Structural Routers and Graphical Interface, Proc. ICCAD87, pp. 436439, 1987.
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