******************************************************************************** ** ******************************************************************************** ** ======================== ** Some Global family rules ** ======================== ** (A) In all CMOS family members, each series

connection of two transistors ** maps into an AND operator while each parallel connection maps into an ** OR operator. ** (B) In all PASS family members, each drain-gate connection for NMOS and ** each drain-gate connection with the gate input variable inverted for ** PMOS maps into an AND operator.Each source-source connection maps ** into an OR operator. ** (C) Before simplification, all SOP terms in any 1 or 0 tree must have ** the same number of literals even if you have to use 1 or 0 as a factor. ** which correspond to VDD or GND. ** ******************************************************************************** ** ******************************************************************************** ** ================================= ** Tribute to the Reinforcement Army ** ================================= ** ============== ** 1. Static CMOS ** ============== ** Given any arbitrary Boolean function Y=f(x1,x2,x3,...,xn), then ** (i) Choose to work with Y and the output will be Ybar while ** working with Ybar gives Y at the output. ** (ii) Draw the truth table for the chosen function ** (iii) Translate the truth table into a K-map. ** (iv) Form a 1-tree expression and a NMOS 0-tree expression **

out of the K-map, making sure that all cells are ** covered. ** (v) ** PMOS type by inverting each literal. ** (vi) ** two transistors and each OR operator maps into a parallel ** connection of two transistors. The 1-tree expresssion ** maps into the PDN while the PMOS 0-tree expression maps ** into the PUN. ** =============== ** 2. Static DCVSL ** =============== ** Given any arbitrary Boolean function Y=f(x1,x2,x3,...,xn), then ** (i) Draw the truth table for the given function ** (ii) Translate the truth table into a K-map ** (iii) Form a 1-tree expression and a 0-tree expression ** out of the K-map, making sure that all cells are ** covered. ** (iv) Each AND operator maps into a series connection ** of two transistors and each OR operators maps into a ** parallel connection of two transistors. The 1-tree ** expression maps into Qbar network while ** the 0-tree expression maps into the Q network ** (v) Attach the cross-coupled PMOS static load ** ====== ** 3. CPL ** ====== ** Given any arbitrary Boolean function Y=f(x1,x2,x3,...,xn), then ** (i) Draw the truth table for the given function ** (ii) Add a pass-function column to the truth table where ** Each AND operator maps into a series connection of Translate the NMOS 0-tree expression to the required

the general pass-function algorithm is: ** if (Y==1) ** OR together the inputs without inversion; ** else if (Y==0) ** invert each input and OR them together; ** (iii) ** for each set of input variables, pass-functions are entered ** into corresponding cells in the K-map without the "+" signs ** (iv) ** looping common signals within each column. Further ** simplification is possible by grouping loops common to more ** than one column. ** (v) ** where each AND operator maps into the drain-gate connection of ** a transistor and each OR operator map into a common source ** connection of two transistors. ** ================================== ** 4. Dual-Rail Domino or DCVS Domino ** ================================== ** Given any arbitrary Boolean function Y=f(x1,x2,x3,...,xn), then ** (i) Draw the truth table for the given function ** (ii) Translate the truth table into a K-map ** (iii) Form a 1-tree expression and a 0-tree expression ** out of the K-map, making sure that all cells are ** covered. ** (iv) Each AND operator maps into a series connection of two ** transistors and each OR operator maps into a parallel ** connection of two transistors.The 1-tree expression maps ** into Qbar network while the 0-tree expression maps ** into the Q network ** Map the pass equivalent expression for Y into a pass network Obtain the pass equivalent expression for Y by vertically Translate the truth table into a pass-function K-map i.e

(v) ** **

Attach a clocked static load of gate-to-gate PMOS transistors, the output inverters, the keeper transistors

and the foot transistor. ** ====================== ** 5. Shared Static DCVSL ** ====================== ** Given any arbitrary Boolean function Y=f(x1,x2,x3,...,xn), then ** (i) Draw the truth table for the given function ** (ii) Translate the truth table into a K-map that allows ** at least one literal to stand alone. ** (iii) Cover the K-map with 1-loops, 0-loops and 10-loops ** which are just single column loops since any column ** must be either of these three loop types. ** (iv) Attach a parallel connection of two NMOS transistors ** to Qbar and Q with the gate inputs being the true and ** inverted forms of the K-map standalone literal ** (v) Generate the nodes to be shared by mapping the 10-tree ** expression into the network to be attached to the common ** source of the parallel connection in step (iv). Again,each ** AND operator maps into a series connection of two transistors ** while each OR operators map into a parallel connection ** of two transistors ** (vi) Implement the 1-tree expression by attaching series (AND ** operator) and parallel (OR operator) connections of ** transistors between the Qbar node and appropriate shared ** node ** (vii) Implement the 0-tree expression by attaching series (AND ** operator) and parallel (OR operator) connections of ** transistors between the Q node and appropriate shared ** node **

============================================ ** 6. NORA Domino(Supplementary functionality) ** ============================================ ** Given any arbitrary Boolean function Y=f(x1,x2,x3,...,xn), then ** (i) Same steps from (i) to (iv) in the dual-rail domino ** algorithm ** (ii) Attach a clocked static load of gate-to-gate PMOS ** transistors, clocked output inverters, the keeper ** transistors and the foot transistor. ** ==================================== ** 7. DSL(Supplementary functionality) ** ==================================== ** Given any arbitrary Boolean function Y=f(x1,x2,x3,...,xn), then ** (i) Same steps from (i) to (iv) in the DCVSL algorithm ** (ii) Attach the cross-coupled pair of PMOS static load ** with an additional pair of NMOS transistors ** in cascode with the PMOS pair and their gates ** connected to Vref=(Vdd/2+Vth). ** =================================== ** 8. TG(Supplementary functionality) ** =================================== ** Given any arbitrary Boolean function Y=f(x1,x2,x3,...,xn), then ** (i) Same steps from (i) to (iv) in CPL algorithm ** (ii) Map the pass equivalent expression for Y into a TG ** network where each AND operator maps into a TG drain** gate connection and each OR operator maps into a source** source connection. ** =================================== ** 9. DPL(Supplementary functionality) ** =================================== **

Given any arbitrary Boolean function Y=f(x1,x2,x3,...,xn), then ** (i) Same steps from (i) to (iv) in CPL algorithm ** (ii) Map the pass equivalent expression for Y into a DPL ** network where each AND operator maps into a DPD symmetrical ** drain-gate connection and each OR operator maps intp a source** source connection.The symmetry restriction is lifted once the ** inputs are more than two or else a triple, quadruple etc pass ** logic must be implemented ** ============= ** 10. DCVSL-PG ** ============= ** Given any arbitrary Boolean function Y=f(x1,x2,x3,...,xn), then ** (i) Same CPL steps from (i) to (v) for the 1-tree ** (ii) Same CPL steps from (i) to (v) also for the 0-tree except ** that each pass literal in the K-map in step (iii) is ** inverted. ** (iii) The 1-tree is attached to Q-bar while the 0-tree is attached ** to Q. ** (iv) Attach the cross-coupled PMOS static load ** ** ******************************************************************************** ** ******************************************************************************** **