ADC - A 10bit 100Msps ADC With Folding Interpolation and Analog Encoding - Thesis

A 10-bit, 100 MS/s A/D Converter using Folding, Interpolation, and Analog Encoding
EPORT FINAL REPORT
William T. Colleran
Integrated Circuits & Systems Laboratory Electrical Engineering Department University of California Los Angeles, CA 90095-1594
December 1993
Funded by TRW Electronics Systems Group, TRW LSI Products Group, and the State of California MICRO Program.
Table of Contents
Chapter 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 Applications for High-Speed Low-Power A/D Converters . . . . . . . . . . . . . . . 3 1.1.1 1.1.2 1.1.3 1.1.4 1.2 Ultrasound Imaging Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 HighDefinition Television . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Radar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Digital Sampling Oscilloscopes . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Design Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.2.1 SHPi Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.3
General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.3.1 1.3.2 1.3.3 Terminology and Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Fundamental Limits to Performance . . . . . . . . . . . . . . . . . . . . . . . . 63 77
References
Chapter 2
Pipelined Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
2.1 Architectural Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 2.1.1 2.1.2 2.1.3 2.1.4 Flash Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Feedback or Multi-pass Converters . . . . . . . . . . . . . . . . . . . . . . . . 81 Feedforward Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Pipelined Feedforward Converters . . . . . . . . . . . . . . . . . . . . . . . . . 85
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2.1.5 2.1.6 2.1.7 2.2 Folding Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Algorithmic (Cyclic) Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Architecture Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
10Bit HighSpeed Converter Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 2.2.1 Timing Scheme for Pipelined Converter . . . . . . . . . . . . . . . . . . . . 94
2.3
Pipelined Feedforward Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 2.3.2 2.3.3 Hardware Complexity (Parts and Power) . . . . . . . . . . . . . . . . . . . 98 Performance (Yield and SNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 107
References
Chapter 3
Sample-and-Hold Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
3.1 3.2 Sampling Bridge Topology and Operation . . . . . . . . . . . . . . . . . . . . . . . . 116 Error Sources in Diode Sampling Bridges . . . . . . . . . . . . . . . . . . . . . . . . . 125 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 Aperture Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SmallSignal Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Preamplifier TrackMode Distortion . . . . . . . . . . . . . . . . . . . . . . 133 Diode Bridge TrackMode Distortion . . . . . . . . . . . . . . . . . . . . . . 141 Finite Aperture Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Hold Pedestal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Droop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
3.2.10 Thermal Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 3.3 Track-and-Hold Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
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3.3.1 3.3.2 3.3.3 3.3.4 3.4 Preamplifier and Sampling Bridge . . . . . . . . . . . . . . . . . . . . . . . . 195 Postamplifier Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 Design Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
Interstage TrackandHold Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 212
References
Chapter 4
Coarse Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
4.1 4-Bit Flash Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 4.1.1 4.1.2 4.1.3 References Differential Reference Ladder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 Layout and DAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 224
Chapter 5
DigitaltoAnalog Converter and Residue Amplifier . . . . . . . . . . . .229
5.1 5.2 5.3 5.4 Segmented Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 Effects of Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 Residue Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 239
References
Chapter 6
Folding Fine Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
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6.1 Concept of Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 6.1.1 6.2 Linear Folding Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Sinusoidal Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 6.2.2 Sinusoidal Folding Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
6.3 6.4
Non-uniform Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Folding and Interpolating A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 256 6.4.1 6.4.2 6.4.3 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Cycle Pointer (Coarse Quantizer) . . . . . . . . . . . . . . . . . . . . . . . . 258 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 259
References
Chapter 7
Gain Stabilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
7.1 7.2 Gain Matching Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 267
References
Chapter 8
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
8.1 8.2 8.3 Circuit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 284
References
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Chapter 9
8Bit A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
9.1 9.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
Chapter 10
Conclusions and Suggested Further Research . . . . . . . . . . . . . . . .301
10.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 10.2 Further Research Opportunities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 References 307
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
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List of Figures
Figure 1.1. Examples of increasing DSP complexity in communications systems. (a)
A classical system with analog demodulator followed by baseband A/D conversion and DSP. (b) Advanced system with IF A/D conversion using digital demodulation and signal processing. (c) Emerging system with RF A/D conversion followed by digital downconversion, demodulation, and baseband signal processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 1.2. Basic Reflection imaging system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 1.3. Phased array imaging system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 1.4. Current medical ultrasound imaging system utilizing one A/D converter
after the received signals have been delayed and summed. . . . . . . . . . . . . . . . . 6
Figure 1.5. Emerging medical ultrasound imaging system with an array of ADCs
with digital delays and summation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 1.6. A typical digital television system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 1.7. Proposed MUSE encoder system.Note the complexity of the digital circuitry following the A/D conversion consistent with the trend depicted in figure 1.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 1.8. Typical phased array radar system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 1.9. Typical sampling oscilloscope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 1.10. A/D converter performance comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 1.11. Fill codes for SHPi mask layers. Layer names refer to those listed in table 1.6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 1.12. Cross-section and plan view of minimum-size SHPi device. . . . . . . . . . . . . . . . 16
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Figure 1.13. Cross-section and plan view of SHPi device. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 1.14. SHPi transistor model used for SPICE simulations. . . . . . . . . . . . . . . . . . . . . . . 17 Figure 1.15. Track-and-hold terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Figure 1.16. Quantizer transfer functions or quantization characteristics. (a) Uniform
quantizer. (b) Non-uniform quantizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 1.17. Unipolar (a) and bipolar (b) quantization characteristics. . . . . . . . . . . . . . . . . . . 21 Figure 1.18. Ideal quantizer transfer functions. (a) Midtread characteristic. (b) Midriser characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 1.19. Quantizer notation, threshold and quantization levels. . . . . . . . . . . . . . . . . . . . . 24 Figure 1.20. Quantization transfer functions including error sources (a) Offset error.
(b) Gain error. (c) Linearity error. (d) Missing codes.. . . . . . . . . . . . . . . . . . . . . . 25
Figure 1.21. Quantizer models. (a) Nonlinear model. (b) Statistical model. . . . . . . . . . . . . . . 27 Figure 1.22. Quantization noise models. (a) Ideal quantizer. (b) Quantizer with
threshold level errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 1.23. Distribution of quantization error.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 1.24. The functions, , and . By plotting the normalized versions,, and
versus the shapes of the above functions become independent of . Also, equals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 1.25. NPR of ideal midriser quantizer with Gaussian noise input. Quantizer
resolution indicated on curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 1.26. Optimum loading factor and NPR for Gaussian noise input. . . . . . . . . . . . . . . . . 39 Figure 1.27. The functions ,, and . By plotting the normalized versions,, and versus
the shapes of the above functions become independent of . . . . . . . . . . . . . . . . 40
Figure 1.28. SNR of ideal midriser quantizer with sinusoidal input. Quantizer resolu-
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tion indicated on curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 1.29. SNR of ideal midriser quantizer plotted versus sinusoidal input amplitude. Approximation is based upon equation 1.17.. . . . . . . . . . . . . . . . . . . . . . . 45
Figure 1.30. Difference between actual SNR and approximated SNR from figure
1.29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 1.31. The inverse cosine function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 1.32. The function for several values of n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 1.33. Harmonic levels for an ideal 8-bit midriser quantizer.. . . . . . . . . . . . . . . . . . . . . 55 Figure 1.34. Harmonic levels for an ideal 10-bit midriser quantizer.. . . . . . . . . . . . . . . . . . . . 56 Figure 1.35. Peak harmonic number versus analog input amplitude.. . . . . . . . . . . . . . . . . . . 57 Figure 1.36. Peak harmonic power for ideal midriser quantizer.. . . . . . . . . . . . . . . . . . . . . . . 58 Figure 1.37. The function evaluated at for peak harmonics. (lower) . (upper) . . . . . . . . . . . . 59 Figure 1.38. Harmonic levels for an 8-bit midriser quantizer with 1/4 LSB rms threshold errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 1.39. Thermal limit to achievable resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 1.40. Aperture uncertainty causes amplitude errors. . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 1.41. Maximum aperture jitter consistent with 1/2 LSB errors for various values
of resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 1.42. Maximum attainable resolution limited by aperture jitter. . . . . . . . . . . . . . . . . . . 67 Figure 1.43. Quantization error waveforms. (a) Ideal quantizer. (b) Quantizer with
threshold level errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 1.44. Segment of quantization error waveform with non-zero threshold

errors, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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Figure 1.45. Achievable resolution as limited by metastability errors. . . . . . . . . . . . . . . . . . . . 76 Figure 2.1. Flash or parallel A/D converter topology.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 2.2. Feedback or multi-pass A/D converter topology.. . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 2.3. Successive approximation A/D converter topology. . . . . . . . . . . . . . . . . . . . . . . 83 Figure 2.4. Feedforward A/D converter topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Figure 2.5. Pipelined A/D converter topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Figure 2.6. Folding A/D converter topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Figure 2.7. Algorithmic A/D converter topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Figure 2.8. Bit serial A/D converter topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Figure 2.9. SNR degradation in folding A/D converters due to mismatches. Quantizer resolution indicated on plot.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Figure 2.10. Yield in folding A/D converters for 8 (lower) or 16 (upper) folds per stage.
is 64 mV (left) or 128 mV (right). The normalization of the independent variable to INL refers to maximum specified INL above which point a converter fails the performance test, e.g. if maximum specified INL is 1/2 LSB, and is 1/2 mV; then the appropriate value on the independent axis for determining yield is 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Figure 2.11. Typical 2 stage pipelined A/D converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 2.12. Alternative implementation of 2-stage pipelined A/D converter. . . . . . . . . . . . . . 94 Figure 2.13. Conventional timing scheme for pipelined A/D converter.. . . . . . . . . . . . . . . . . . 95 Figure 2.14. Output signals from converter elements in pipelined A/D employing conventional timing scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Figure 2.15. Modified timing scheme for pipelined A/D converter. . . . . . . . . . . . . . . . . . . . . . 97
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Figure 2.16. Output signals from converter elements in pipelined A/D employing
modified timing scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 2.17. Comparison of A/D converter complexity versus fine quantizer resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 2.18. 5-6 pipeline partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 2.19. 4-7 pipeline partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 2.20. 10 bit A/D converter yield (upper) and mean SNR (lower) versus
segmented DAC current source mismatch for both 4-7 and 5-6 partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 2.21. 10 bit A/D converter yield (upper) and mean SNR (lower) versus coarse
quantizer INL for both 4-7 and 5-6 partitioning. . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 2.22. 10 bit A/D converter yield (upper) and mean SNR (lower) versus fine
quantizer INL for both 4-7 and 5-6 partitioning. . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 2.23. 10 bit A/D converter SNR (upper) and gain error (lower) versus DAC gain
error for both 4-7 and 5-6 partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 2.24. 10 bit A/D converter SNR (upper) and gain error (lower) versus fine
quantizer gain error for both 4-7 and 5-6 partitioning. . . . . . . . . . . . . . . . . . . . 106
Figure 2.25. Histogram of A/D converter SNR for 4-7 (upper) and 5-6 (lower)
partitionings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 2.26. Block diagram of selected A/D converter architecture.. . . . . . . . . . . . . . . . . . . 108 Figure 3.1. Track-and-hold building-blocks (a) and operation (b). . . . . . . . . . . . . . . . . . . . 116 Figure 3.2. Prototype diode bridge track-and-hold circuit with emitter follower
preamplifier and postamplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 3.3. Diode-bridge track-and-hold with differential pair controlling bridge

current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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Figure 3.4. Diode-bridge switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 Figure 3.5. Diode-bridge models in track mode. (a) Large-signal model. (b) Smallsignal model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Figure 3.6. Diode bridge operation in track mode. (a) t. (b) . (c) . . . . . . . . . . . . . . . . . . . . . 123 Figure 3.7. T/H topologies. (a) Single-ended. (b) Differential. . . . . . . . . . . . . . . . . . . . . . . . 124 Figure 3.8. Aperture jitter gives rise to amplitude error.. . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figure 3.9. SNR as limited by clock jitter and quantization noise. Quantizer resolution labelled on curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Figure 3.10. Small-signal models of diode-bridge in track mode. (a) Full model. (b)
Simplified model when parallel networks are combined. . . . . . . . . . . . . . . . . . . 131
Figure 3.11. Emitter follower preamplifier with capacitive load used to simulate dynamic distortion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Figure 3.12. Simulated THD of the emitter follower preamplifier with capacitive load
versus load capacitance, , bias current, , amplitude, , and input frequency, . In each case, the parameter is varied in a 1, 2, 5, 10 pattern which approximates exponential spacing (i.e. each value is about twice the previous one) while maintaining integer values. . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 3.13. Large-signal model of diode bridge in track mode with finite bias impedances, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
Figure 3.14. Diode bridge with current perturbations caused by dynamic current
into. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Figure 3.15. Linear, time-varying model of diode bridge and hold capacitor used for
finite aperture analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Figure 3.16. Response of bridge current (a) and small-signal bridge resistance (b)
over finite aperture time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
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Figure 3.17. Frequency response induced by finite aperture time assuming a linear
small-signal bridge model. Upper curves represent frequency response with constant bridge resistance, . Lower curves include the effect of bridge turn-off governed by .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 3.18. Large-signal model for simulating finite aperture effects. . . . . . . . . . . . . . . . . . 153 Figure 3.19. Simulated THD due to finite aperture time as a function of input amplitude, , input frequency, , aperture time, , and bridge slew rate, . Parameters are swept in a 1, 2, 5, 10 fashion to approximate an exponential sweep with integer values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 3.20. Charge injection at bridge turn-off gives rise to hold pedestal distortion.
(a) Typical bridge circuit showing auxiliary diodes which control bridge bias voltages in hold mode. (b) Diode small-signal capacitance-voltage characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 3.21. Comparison between distortion due to hold pedestal predicted by analysis and simulation (upper); and between distortion predicted by simple approximations and simulation (lower). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 3.22. A bootstrapped bridge center-tap reduces hold pedestal distortion. (a)
Unity-gain buffer drives bridge center-tap from output node. (b) Diode CV characteristic still determines residual charge injection. . . . . . . . . . . . . . . . . 166
Figure 3.23. Diode-bridge track-and-hold with differential pair controlling bridge current. Diodes D5 and D6 conduct during hold-mode while diodes D1 through D4 are cut-off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 3.24. Small-signal models of bridge in hold mode. (a) Model including all components. (b) Equivalent model simplified through symmetry. . . . . . . . . . . . . . . 172
Figure 3.25. Small-signal frequency response of diode bridge in hold mode. . . . . . . . . . . . 174 Figure 3.26. Cross-coupled capacitors between complementary bridges reduce
feedthrough and hold pedestal error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 3.27. Feedthrough versus cross-coupling capacitance normalized to optimum
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value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
Figure 3.28. Cross-coupling scheme for reduced feedthrough with series connected
diodes as coupling elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
Figure 3.29. Feedthrough versus area of cross-coupled diode structure normalized to

the optimum area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
Figure 3.30. Cross-coupling can partially cancel hold pedestal error by cancelling
charge expelled by bridge diodes during bridge turn-off. Note that charge injection from a bridge diode connected to the top node of one bridge is cancelled by the cross-coupled element connected to the bottom node of the complementary bridge. Likewise, injection from a diode connected to the bottom of one bridge is cancelled by the cross-coupled element connected to the top of the complementary bridge. . . . . . . . . . . . . . . . . . . . . . 180
Figure 3.31. Noise sources affecting track-and-hold operation. represents the total
jitter noise power on the drive signals to the diode bridge including the jitter on the incoming clock and that added by the clock buffer circuitry. represents the mean-square noise voltage at the hold capacitors. This is an approximation assuming that the dominant component is thermal noise and exists during both track mode and hold mode. causes base shot noise which is integrated on the hold capacitor during hold mode giving rise to voltage noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
Figure 3.32. Single-pole RC low pass filter for analysis of kT/C noise. . . . . . . . . . . . . . . . . . 184 Figure 3.33. kT/C noise at the hold capacitors. In the differential implementation the
two independent sources contribute to the total noise power perturbing the held voltage, resulting in doubled noise power compared to a singleended version. Signal amplitude is also doubled, thus quadrupling signal power and increasing SNR by 3 dB over the single-ended case. . . . . . . . . . . . 185
Figure 3.34. Base shot noise integrates on the hold capacitors during the hold interval
adding a noise component to the held voltage. . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 3.35. Postamplifier input bias current causes droop on hold capacitor. . . . . . . . . . . . 187
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Figure 3.36. A differential T/H implementation largely cancels droop effects. . . . . . . . . . . . 189 Figure 3.37. Thermal contour of minimum-size SHPi device (2 m X 8 m emitter
area) dissipating 1 mW on a 250 m thick substrate. . . . . . . . . . . . . . . . . . . . 191
Figure 3.38. Thermal contour of large device (75 m X 75 m emitter area) dissipating 200 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 3.39. Emitter follower buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Figure 3.40. A single-ended T/H circuit based on a diode-bridge with emitter follower
preamplifier, differential pair current switch with resistive loads, and emitter follower postamplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 3.41. A differential track-and-hold implementation with linearity compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 3.42. Differential preamplifier and bridge with compensation. . . . . . . . . . . . . . . . . . . 198 Figure 3.43. Layout of differential preamplifier and diode bridge with feedforward
compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 3.44. Postamplifier implementations. (a) An operational amplifier connected

as a voltage follower. (b) A differential pair configured as a voltage follower. (c) A differential pair-based follower with enhanced performance. (d) An open-loop unity-gain postamplifier with linearity compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 3.45. Differential postamplifier implementation.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Figure 3.46. Layout of differential postamplifier with feedback bootstrapping. . . . . . . . . . . . 203 Figure 3.47. Clock buffer schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Figure 3.48. Layout of first track-and-hold clock buffer circuit. . . . . . . . . . . . . . . . . . . . . . . . 205 Figure 3.49. Complete track-and-hold circuit (with postamplifier shaded). The clock
buffer has not been drawn for simplicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
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Figure 3.50. Layout of first track-and-hold circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 Figure 3.51. Simulated T/H output spectrum. Fs=100 Msps, Fin=43.75 MHz. . . . . . . . . . . . 207 Figure 3.52. Second stage track-and-hold block diagram with feedback to bridge center-tap nodes to reduce gain-loss due to hold pedestal error. . . . . . . . . . . . . . . 208
Figure 3.53. Second track-and-hold with bootstrapped center-tap.. . . . . . . . . . . . . . . . . . . . 209 Figure 3.54. Layout of second T/H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 Figure 3.55. Interstage postamplifier schematic which provides high input impedance and voltage gain of 2. Output emitter followers are not shown for simplicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
Figure 3.56. Second T/H postamplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 Figure 3.57. Second T/H with replica. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 Figure 4.1. Flash or parallel A/D converter topology.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Figure 4.2. Differential reference ladder with comparators. . . . . . . . . . . . . . . . . . . . . . . . . . 219 Figure 4.3. Differential reference ladder showing comparator input bias
currents.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
Figure 4.4. Three dimensional depiction of differential reference ladder with comparator connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
Figure 4.5. Interpolation between preamplifiers reduces loading on differential reference ladder and reduces power by halving the number of comparator pre-amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
Figure 4.6. Differential reference ladder drawn to emphasize circular symmetry, and
including reference to interpolated thresholds in grey. . . . . . . . . . . . . . . . . . . . 223
Figure 4.7. Coarse quantizer preamplifier array driven by differential reference ladder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
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Figure 4.8. Coarse quantizer comparator with internal DAC current switch. . . . . . . . . . . . 226 Figure 4.9. Coarse quantizer latch array with current segment inputs and differential
DAC output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 5.1. Fully-segmented current-output reconstruction DAC.. . . . . . . . . . . . . . . . . . . . 231 Figure 5.2. 10-bit yield for a fully-segmented DAC with 4 bit resolution versus current segment mismatch assuming maximum INL is 1/2 LSB. . . . . . . . . . . . . . 232
Figure 5.3. 10 bit A/D converter yield (upper) and mean SNR (lower) versus
segmented DAC current source mismatch for both 4-7 and 5-6 partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 5.4. Segmented DAC current source array with scrambled wiring matrix at
top. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 5.5. Segmented DAC current source array with common centroid
layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 5.6. Segmented DAC current source array with trimmable layout. . . . . . . . . . . . . . 237 Figure 5.7. Residue amplifier implementations. (a) Typical approach using
transconductance cell and subtracting currents at output. (b) Improved approach subtracting currents at transconductor emitter. . . . . . . . . . . . . . . . . 238
Figure 5.8. Residue amplifier and its replicas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Figure 6.1. Architecture of feedforward quantizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Figure 6.2. Folding A/D converter architecture. Analog folding with F folds reduces
fine quantizer resolution to . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 6.3. Reduction in dynamic range seen be comparator array for (a) sawtooth
and (b) triangle folding characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 6.4. Translinear-based current-mode folding circuit. . . . . . . . . . . . . . . . . . . . . . . . . 246 Figure 6.5. Current-mode folding circuit using cascodes.. . . . . . . . . . . . . . . . . . . . . . . . . . 247
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Figure 6.6. A folding function which is not piece-wise linear. The transfer function
shown is sinusoidal for convenience but could be any non-saturating, periodic function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
Figure 6.7. An array of phase-shifted, non-linear folding blocks with comparators detecting zero-crossings can circumvent the need for an inverse-sine quantizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
Figure 6.8. Linear superposition implements non-uniform interpolation to generate

multiple sinusoids equally-spaced in phase from two quadrature sinusoids. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
Figure 6.9. Translinear sinusoidal folding circuit with voltage drive. . . . . . . . . . . . . . . . . . . 250 Figure 6.10. Translinear sinusoidal folding circuit with current drive. . . . . . . . . . . . . . . . . . . 251 Figure 6.11. Folding circuit based upon hyperbolic tangent transfer function of voltage driven differential pairs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
Figure 6.12. Folding circuit based on wired-OR interconnection. . . . . . . . . . . . . . . . . . . . . . 253 Figure 6.13. Fully-differential sinusoidal folding circuit with differential reference ladder, overflow compensation, and common-mode de-bias circuitry.. . . . . . . . . . 253
Figure 6.14. Differential non-uniform interpolation ladder generates sinusoids equally

spaced in phase from quadrature inputs. Distortion is minimized due to symmetry of circuit enabling use of simple, low-power emitter follower buffers.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
Figure 6.15. (a) Differential non-uniform interpolation ladder. (b) Phasor representation of quadrature and interpolated signals. (c) Corresponding voltage waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
Figure 6.16. Threshold error at interpolated thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Figure 6.17. Folding, interpolating, and analog encoding fine quantizer using quadrature folded waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
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Figure 6.18. Improved encoding scheme significantly reduces hardware complexity.

All circuits are differential but are shown single-ended for simplicity.. . . . . . . . 258
Figure 6.19. Cycle pointer incorporating analog encoding. Actual circuit is differential
but is shown single-ended for simplicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 6.20. Layout of fine quantizer analog circuitry including differential reference
ladder, folding amplifiers, interpolation ladder, and analog multipliers from the encoding block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 7.1. Effects of component gain errors on A/D transfer function. (a) Effect of
fine quantizer gain error. (b) Effect of DAC gain error. . . . . . . . . . . . . . . . . . . . 264
Figure 7.2. 10 bit A/D converter SNR (upper) and gain error (lower) versus DAC gain
error for both 4-7 and 5-6 partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 7.3. 10 bit A/D converter SNR (upper) and gain error (lower) versus fine
quantizer gain error for both 4-7 and 5-6 partitioning. . . . . . . . . . . . . . . . . . . . 266
Figure 7.4. Gain-matching replica circuits and feedback loops which adjust component gains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 8.1. 10-bit A/D converter with constituent components highlighted. Die size is
approximately 4 mm X 4 mm (160 mil X 160 mil). Analog input is at top, left of chip. Digital outputs are at bottom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 8.2. Die photograph of 10-bit A/D converter with nominal DAC layout. Unused area surrounding DAC degeneration resistors is reserved for use in other ADC versions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 8.3. Die photograph of 10-bit A/D converter with common centroid reconstruction DAC layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 8.4. Die photograph of 10-bit A/D converter with trimmable reconstruction
DAC layout.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 8.5. A/D converter test setup. All synthesizers are phase-locked to one master synthesizer. Pulse generator supplies ECL clock signal to DUT upon
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trigger from low phase-noise synthesized source. Four pulse generators are used to supply clocks to DUT, but only one is shown for simplicity. Off-chip reconstruction DAC is helpful for real-time debugging of system. Digitized data is captured in fast, deep memory and analyzed on workstation off-line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
Figure 8.6. A/D converter test setup. Synthesizers, pulse generators, spectrum analyzer, and filter bank are housed in rack on left. High-speed memory and workstation are on right. Power supplies, oscilloscopes, and test fixtures are on bench in rear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
Figure 8.7. Digital output spectrum from A/D converter when sampling a 5.87 MHz
sinusoidal input at 75 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
Figure 8.11. Differential linearity as measured by a histogram test with fin = 6MHz
and fs = 75Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280
Figure 8.12. Integral linearity as measured by a histogram test with fin = 5.87MHz
and fs = 75Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
Figure 8.13. Differential linearity as measured by a histogram test with fin = 49.6 MHz
and fs = 75 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
Figure 8.14. Integral linearity as measured by a histogram test with fin = 5.87 MHz
and fs = 75 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
Figure 8.15. Beat frequency test. fS = 75 Msps, fin = 37.501 MHz. ADC output is
decimated by 2 then applied to reconstruction DAC and displayed on oscilloscope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
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Figure 9.1. 8-bit A/D converter architecture. T/H derives from input T/H in 10-bit
ADC. Quantizer is based upon 7-bit fine quantizer, also from 10-bit converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 9.2. 8-bit A/D converter with overlays to indicate location of constituent components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 9.3. Die photograph of 8-bit A/D converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Figure 9.4. Measured SNR and harmonic distortion versus input frequency at
25 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 9.5. Measured SNR and harmonic distortion versus input frequency at
50 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
100 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
125 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
150 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
175 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
200 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
200 Msps with T = -40 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 9.12. Measured SNR and harmonic distortion versus input frequency at 25
Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Figure 9.13. Measured SNR versus input frequency at several sample rates.. . . . . . . . . . . 298
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Figure 9.14. Measured integral linearity error versus power supply variation at several temperatures with fS = 100 Msps. Upper curves plot peak INL. Lower curves plot RMS INL.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
List of Tables
Table 1.1.
Comparison of performance requirements for HDTV and medical ultrasound imaging applications along with design goals for this work. . . . . . . . . . 3
Table 1.2. Table 1.3. Table 1.4. Table 1.5. Table 1.6. Table 1.7. Table 1.8. Table 2.1. Table 3.1.
Requirements for medical ultrasound imaging applications. . . . . . . . . . . . . . . . . 7 Requirements for HDTV applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Performance goals for this development. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SHPi NPN characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SHPi mask layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SHPi NPN transistor SPICE model parameters. . . . . . . . . . . . . . . . . . . . . . . . . 18 Optimum quantizer loading and NPR for Gaussian noise input. . . . . . . . . . . . . 38 Comparison among several A/D converter architectures. . . . . . . . . . . . . . . . . . 89 Bias voltages across bridge elements in track mode and hold mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
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ACKNOWLEDGEMENTS
I am grateful to the many people who supported and encouraged me during the work leading to this thesis: professors, colleagues, friends, and family. My advisor at UCLA, Dr. Asad A. Abidi, helped select a challenging and worthwhile research topic and guided me throughout this endeavor. I am grateful to him and the other members of my committee, Henry Samueli, Gabor C. Temes, Siegfried G. Knorr, Milos D. Ercegovac, and William E. Slater. My colleagues at UCLA have been a constant source of support, contributing in innumerable ways to the work described here. I feel privileged to have worked with these stimulating researchers, especially John Angell, James Chang, Ramon Gomez, Eric Holmberg, Patrick Pai, Gary Sullivan, and Tyson Tuttle. In addition to their other contributions, Pat Pai and James Chang assisted greatly in the preparation of this manuscript. TuongLong Huy Phan proved invaluable, tirelessly laying out the integrated circuits, and Maryam Rofougaran skillfully drew many of the gures appearing in this manuscript. Several people outside of UCLA were also supportive of my efforts. Binoy Rosario, Brian Boso, Wink Gross, Ken Weigel and Jim Marsh made fabrication of the circuits possible at Tektronix Integrated Circuit Operation. Fred Weiss provided access to TriQuint Semiconductors Gallium Arsenide MESFET process for a precursor to this project which led to our benecial relationship with Tektronix. K.C. Wang, Peter Asbeck, Randy Nubling, and Derrick Cheung funded a parallel development of a Gallium Arsenide HBT A/D converter at the Rockwell International Science Center and shared results of their work with me. Tino Gomez of TRWs Analog and Digital Products department assembled all of the xtures required during the evaluation of the integrated circuits. His expert abilities eased the difculty of testing greatly. Throughout my graduate studies at UCLA I received nancial support from TRW, Inc. and through the University of California MICRO program. My management at TRW, especially Bill Ashley, Fred Carper, Ken deGraaf, and Keith Kelley, has been consistently supportive during this arduous process. Most importantly, my family, Mom and Dad, Bud, Beth, and Brian gave me constant moral support and encouragement more than they realize. Without their faith and inspiration this work very likely would not have been completed. I cannot adequately express the love and gratitude I feel for them.
xxxi
VITA
1961 1983 Born, Bangor, Maine B. S., Electrical Engineering (Magna Cum Laude) University of Notre Dame Notre Dame, Indiana 19831985 Member of Technical Staff Electronic Systems Group TRW, Inc. Redondo Beach, California 1985 M. S., Electrical Engineering University of Southern California Los Angeles, California 19851987 MICRO Fellow Department of Electrical Engineering University of California Los Angeles, California 19871992 TRW Fellow Department of Electrical Engineering University of California Los Angeles, California 19921993 Department Staff Electronic Systems Group TRW, Inc. Redondo Beach, California
xxxii
PUBLICATIONS
W. T. Colleran and A. A. Abidi, A 10-Bit 75MHz Two-Stage Pipelined Bipolar A/D Converter, to appear in IEEE Journal of Solid-State Circuits, vol. 28, no. 12, Dec. 1993.
W. T. Colleran, T. H. Phan, and A. A. Abidi, A 10b 100Ms/s Pipelined A/D Converter, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers, vol. 36, San Francisco, CA., pp.68-69, Feb. 1993.
W. T. Colleran and A. A. Abidi, A 26dB Wideband Matched GaAs MESFET Amplier, IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 10, pp. 1377-1386, Oct. 1988.
W. T. Colleran and A. A. Abidi, A 26dB Wideband Matched GaAs MESFET Amplier, IEEE International Solid-State Circuits Conference Digest of Technical Papers, vol. 31, San Francisco, CA, pp. 196197, Feb. 1988.
W. T. Colleran and A. A. Abidi, Wideband Monolithic GaAs Amplier using Cascodes, Electronics Letters, vol. 23, no. 8, pp. 951952, Aug. 27, 1987.
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ABSTRACT OF THE DISSERTATION
A 10-bit 100 Megasample-per-Second Analog-to-Digital Converter Utilizing Folding, Interpolation, and Analog Encoding Techniques
by
William Thomas Colleran
Doctor of Philosophy in Electrical Engineering University of California, Los Angeles, 1993 Professor Asad A. Abidi, Chair
Monolithic implementations of data converters at the 10 bit, 100 megasample-per-second (Ms/s) level are considered a high priority for many applications today including ultrasound imaging, high denition television, radar signal processing, and instrumentation. Several drawbacks including excessive power consumption and die size prevent current high-speed conversion methods from being extended to the 10-bit level. The purpose of this research project was to develop more efcient architectures for highspeed, mediumresolution converters, and to evolve the circuit designs necessary for these architectures. Analog-to-digital (A/D) converters that are known to work at the highest speed typically involve a ash architecture, preceded by a diode-bridge sample-and-hold (S/H) circuit. However, single-chip implementations of ash converters with resolution greater than 8 bits are difcult to attain because these topologies involve large device count and large power dissipation. Further,
xxxv
xxxvi multichip realizations yield degraded performance and increased power dissipation compared to monolithic approaches due to the overhead incurred when driving signals between chips. Innovative architectures which include subranging, pipelining, analog encoding, folding, and interpolation have been investigated for a monolithic A/D converter which includes an on-chip S/H function to enhance overall converter performance. These techniques resulted in a topology which is highly integrable yet which approaches the performance of a fully parallel or ash A/D converter. The integrated circuit dissipated 800 mW while digitizing 50 MHz input signals at 75 Ms/s with 56 dB signal-to-noise-plus-distortion ratio.
Chapter 1
Introduction
Analog-to-digital (A/D) conversion and digital-to-analog (D/A) conversion lie at the heart of most modern signal processing systems where digital circuitry performs the bulk of the complex signal manipulation. As digital signal processing (DSP) integrated circuits become increasingly sophisticated and attain higher operating speeds more processing functions are performed in the digital domain. Driven by the enhanced capability of DSP circuits, A/D converters (ADCs) must operate at ever-increasing frequencies while maintaining accuracy previously obtainable at only moderate speeds. This trend has several motivations and poses important consequences for analog circuit design. The motivations for processing most signals digitally are manifold: digital circuits are much less expensive to design, test, and manufacture than their analog counterparts; many signal processing operations are more easily performed digitally; digital implementations offer exibility through programmability; and digital circuitry exhibits superior dynamic range, thereby better preserving signal delity. As a consequence of the aforementioned advantages accrued by DSP, fewer and fewer operations benet from analog solutions. Figure 1.1 illustrates the evolution towards systems relying upon more sophisticated DSP hardware with a concomitant reduction in analog circuit content. This move portends two important ramications for the role of analog circuitry in future systems. First, only Radio Frequency (RF) processing and data conversion (including anti-aliasing lters) will remain as important niches where analog implementations exhibit advantages over digital approaches. Data converters will continue to play a signicant role
Chapter 1 Introduction
RF Signal
Analog Demodulator
Baseband Signal
A/D Converter
DSP
(a) RF Signal IF Signal
RF Mixer
A/D Converter (b)
Digital Demodulator & Processing
RF Signal
A/D Converter (c)
Digital Mixer, Demodulator, & Processing
Examples of increasing DSP complexity in communications systems. (a) A classical system with analog demodulator followed by baseband A/D conversion and DSP. (b) Advanced system with IF A/D conversion using digital demodulation and signal processing. (c) Emerging system with RF A/D conversion followed by digital downconversion, demodulation, and baseband signal processing. in advanced electronic systems operating in the RF and Intermediate Frequency (IF) regimes. Further, since A/D conversion generally requires more power and circuit complexity than D/A conversion to achieve a given speed and resolution, ADCs frequently limit performance in signal processing systems. This fact underscores the second consequence of enhanced DSP performance on the role of analog circuit design. That is, since A/D conversion limits overall system performance, development of improved A/D conversion algorithms and circuitry represents an extremely important area of research for the foreseeable future. This dissertation describes the results of research into the development of new techniques for achieving high-speed, low-power A/D conversion where high-speed refers to converters capable of operation in excess of 50 megasamples per second (Ms/s) and low-power implies dissipation below one Watt. Important parameters of ADCs in addition to speed and power dissipation such as resolution, linearity, dynamic distortion, and yield are addressed. Since, generally one of these
Figure 1.1.
1.1 Applications for High-Speed Low-Power A/D Converters
aspects of ADC performance can be improved at the expense of others, design techniques utilized when approaching high-speed A/D conversion have historically required large power dissipation. Conversely, many applications which require low power dissipation such as portable digital voltmeters (DVMs) led to designs which are fundamentally limited in speed. The purpose of this research was to develop new A/D conversion techniques which are inherently fast yet which consume low power. Table 1.1. compares the performance goals for this project along with the
Parameter
Resolution Sample Rate Input Bandwidth Power INLa DNL SNR SFDR S/(N+D)
Units
bits Msps MHz mW bits bits dB dB dB
HDTV Ultrasound Requirement Requirement

10 75 30 1000 1 1 52 56 50 10 40 15 500 1 1/2 56 58 54
Design Goal
10 100 50 750 1 1/2 59 65 58
Table 1.1. Comparison of performance requirements for HDTV and medical

ultrasound imaging applications along with design goals for this work.
a. INL and DNL are dened in section 1.3.1.
requirements for two important applications of high-speed A/D converters which served as motivations for this work: High-Denition Television (HDTV) and medical ultrasound imaging systems. These and other applications for high-speed, low-power ADCs are next described in detail.

As mentioned previously, the ever-increasing speed and sophistication of monolithic DSP hardware is enabling unprecedented improvements in system performance. Frequently, however;
such enhancements are limited by the attainable A/D converter capabilities. In such instances, increased ADC performance is particularly advantageous (and valuable) since system viability is directly impacted. Several applications where high-speed, low-power A/D converters play a pivotal role in determining overall system performance are detailed below. The converter requirements for these applications helped determine practical design goals for this research project.
1.1.1 Ultrasound Imaging Systems

Medical ultrasound imaging is by far the most important commercial application of highspeed, low-power ADCs of the type described here. In this application, A/D converters digitize electrical signals from an array of piezo-electric transducers which respond to acoustic echoes from a patients body. The digitized data from the converter array can then be combined to form an image of the tissue within the body. The diagnostic utility of such real-time imaging is obvious, leading to an impressive commercial market. Currently over 10,000 medical ultrasound machines are sold worldwide annually. Systems now under development use arrays of 128 A/D converters generating a worldwide annual market of over 1 million chips. Suitable ADCs must meet stringent performance criteria such as listed in table 1.1 and at present no such component exists. A basic reection imaging system (Fig. 1.2) [1], [2] utilizes a piezo-electric transducer
Transducer T Patient
Signal Processor
Display
Pulse Generator
Figure 1.2. Basic Reection imaging system.
which emits acoustic energy when excited electrically or conversely electrical energy when excited acoustically. With the switch in the transmit position a pulse generator excites the transducer resulting in propagated wavefronts emanating from the transducer. Immediately following pulse
transmission the switch is changed to the receive position using the same transducer. When the wavefront encounters a discontinuity, as shown, a scattered wave is produced indicated by the reected vectors. This scattered wave is received by the transducer and the resultant electrical signal is processed and displayed giving information about the size and location of the discontinuity. The processing usually comprises bandpass ltering, gain control, and envelope detection. Although conceptually simple, such a system can only form one-dimensional images containing information describing the distance a discontinuity lies from the transducer. Two-dimensional images can be formed by physically scanning the transducer across the region of interest, but a superior approach relies on an array of transducers which can be electrically controlled to scan a two-dimensional eld. In array imaging systems which use electronic deection and focusing, or phased array systems as they are often called, each transducer receives reected signals from every point in the eld of view (Fig. 1.3). The outputs of all transducers are appropriately delayed and summed to
Controlled Controlled Delay Controlled Delay Controlled Delay Delay Transducer Array Control Unit
Signal Processor Summer
Display
Figure 1.3. Phased array imaging system.
represent the energy reected from a specic point within the view eld. In this manner signals from the desired point undergo constructive interference, while those signals from other points sum in an uncorrelated manner. By electronically controlling the delay elements in the array, the beam is steered through the region of interest forming a real-time two-dimensional image. Current medical ultrasound systems employ analog delay-lines and summing electronics with A/D conversion occurring after the received signals have been summed (Fig. 1.4). Such systems place only modest restrictions on A/D performance usually requiring 8-bit resolution at video sample rates while
Delay Delay Delay Delay Transducer Array Control Unit
ADC
Signal Processor
Display
Figure 1.4. Current medical ultrasound imaging system utilizing one A/D converter after the received signals have been delayed and summed.
tolerating power dissipation well above one Watt. However, the analog delay-lines and summing electronics are cumbersome, difcult to control, and degrade signal delity. Therefore, ultrasound systems currently under development incorporate one ADC per transducer channel enabling use of digital delays and summation (Fig. 1.5) [1], [2], [3]. Image resolution in phased array systems
Digital ADC Digital Delay ADC Digital Delay ADC Digital Delay ADC Delay Transducer Array
Digital Summer
Signal Processor
Control Unit
Display
Figure 1.5.
Emerging medical ultrasound imaging system with an array of ADCs with digital delays and summation.
increases with the number of array elements and the frequency of emitted pulses. To enhance image quality, emerging ultrasound units use larger arrays (128 to 256 elements) and higher RF pulse frequencies (up to 15MHz) than their predecessors. This type of system gives superior image quality, but because of the large number of ADCs required, the power dissipation and price of each converter must be minimized. Additionally, sample rates and input bandwidths must increase to accommodate the increased transducer frequencies and amplitude resolution must improve to 10 bits. This combination of performance specications (summarized in table 1.2) represents a very
Parameter
Resolution Sample Rate Input Bandwidth Power INL DNL SNR SFDR Power Supplies Die Cost Selling Price
Ultrasound Requirement
10 40 15 500 1 1/2 56 58 +/ 5 <10 <40
Units
bits Msps MHz mW bits bits dB dB V $ $
Table 1.2. Requirements for medical ultrasound imaging applications.

stringent and as yet elusive goal, but the magnitude of the ultrasound market provides compelling motivation to develop such A/D converter technology. Note that the modest die cost of $10 per screened component places a restriction on the die size and yield of the converter given a certain wafer cost.
1.1.2 HighDenition Television

Debate rages today over what form future television systems will assume. Unquestionably the next generation of video equipment will deliver unprecedented picture quality with spatial resolution increasing to millions of pixels and amplitude resolution improving to better than one part-per-thousand. Because of this dramatic improvement, the inchoate system has been dubbed HighDenition Television or HDTV. Almost certainly HDTV will rely upon a digital transmission standard taking advantage of the powerful image compression algorithms developed to reduce the required amount of transmitted data. Such a system (Fig. 1.6) requires A/D conversion of the incoming rasterized signal from a video camera at rates far in excess of current video signals. After modulation and transmission, the received signal is demodulated, digitized, and processed for display. The exact form of the receiver system depends on available technology and will follow the
CAMERA
A/D
RASTERIZED SIGNALS
MODULATION
TRANSMISSION CHANNEL
D/A
DISPLAY
DIGITAL PROCESSING
A/D
DEMODULATION
Figure 1.6. A typical digital television system.

trend depicted in gure 1.1. Therefore, the A/D converter in the receiver will migrate towards the antenna eventually operating at RF sample rates. At present, broadcast studio equipment places more demanding constraints on ADCs than home television units. An operational broadcast encoding system has been in use in Japan for several years. This system, the Multiple Sub-Nyquist Sampling Encoding (MUSE) system, (Fig. 1.7) [4] requires one A/D converter operating above 40
S LPF HDTV in RGB LPF LPF 21~22 MHz A/D A/D A/D
1
M T X
Interfield Pre-filter Time compression LPF LPF TCI Encoder M Interfield Pre-filter 8 MHz Field Offset Subsampling (24.3 MHz)
12 MHz LPF
44.55 MHz Sampling Conversion 48.6 32.4 48.6 Ms/s Sampling Conversion 48.6 32.4 M S 16.2 Ms/s M I X Frame Offset Subsampling Emphasis Control Synchronize, and Add
Motion Area Detection Audio (4 Channels), Independent Data Input Audio Encoder 1,350 Kb/s Time Compression
Motion Vector Detection
16.2 Ms/s Transmission Equalization LPF
32.4 Ms/s MUSE OUT D/A LPF FM Modulation
TX
LPF 12.15 MBd Audio/VIT Signal Adder 13 MHz 32.4 MHz
Figure 1.7.
Proposed MUSE encoder system.Note the complexity of the digital circuitry following the A/D conversion consistent with the trend depicted in gure 1.1.
Ms/s for each of the 3 signals comprising an HDTV image in RGB format. Digitization at even higher rates is required for an HDTV composite signal. Increased dynamic range of the HDTV
video signal also mandates digitization with 10-bit resolution. Table 1.3 summarizes the A/D
Parameter
Resolution Sample Rate Input Bandwidth Power INL DNL SNR SFDR Power Supplies Die Cost Selling Price
HDTV Requirement
10 75 30 1000 1 1 52 56 +/ 5 <25 <100
Units
bits Msps MHz mW bits bits dB dB V $ $
Table 1.3. Requirements for HDTV applications.
converter requirements for HDTV. Note that the sample rate and input bandwidth are higher than those required for ultrasound systems (Table 1.2), but that higher power consumption and die cost are tolerable.
1.1.3 Radar
Radar and electronic warfare (EW) systems represent another important application of high-speed, low-power A/D converters. Many modern systems employ phased-array techniques such as those used in ultrasound machines (Fig. 1.5) with the piezo-electric transducers replaced by RF antennas. At present, digitization usually occurs after downconversion (Fig. 1.8) so this application incorporates baseband A/D conversion [3]. The sample-rate and resolution of the ADC depend upon the desired spatial resolution and discrimination of the radar image. Sample-rates above 50 Msps with greater than 8 bit resolution are often desirable. Jam resistant radars require higher resolution A/D converters to enable detection of small signals in the presence of highpowered interference.
10
"I" (In-Phase) Channel Detector ADC
RF Weighting, Delay, and Combining Network
Local Oscillator Digital Processor 90 degree Phase Shifter Detector ADC
Antenna Array
"Q" (Quadrature) Channel
Figure 1.8. Typical phased array radar system.

EW systems often place more stringent requirements on ADCs than radars by employing IF and RF A/D conversion. In such systems an incoming radar signal is digitized (preferably at RF frequencies) then stored in a high-speed memory called a digital RF memory (DRFM). This digital data can then be converted back to analog form and transmitted to the originator confusing its signal processing algorithms. Alternatively, the stored radar signature can be used later for threat analysis. Similar techniques are used in radar range nders and terrain mapping systems. In each of these applications higher sample-rates and digitizable signal bandwidths improve performance; therefore, radar systems always serve as an application for faster A/D converters.
1.1.4 Digital Sampling Oscilloscopes

Much instrumentation in general and digital sampling oscilloscopes (DSOs) in particular rely upon fast, accurate A/D converters to perform their functions. A DSO comprises an ADC (preceded by signal conditioning circuitry), a buffer memory, and a display (Fig.1.9) [5], [6]. Some
Analog Input
Signal Conditioning
ADC
Buffer Memory
Low Rate Digital Play back
Clock & Control Gain Adjust Write Read
Figure 1.9. Typical sampling oscilloscope.
1.2 Design Goals
11
DSOs require only 8-bit A/D conversion because the display is limited to that resolution; however as more emphasis is placed upon digital storage and analysis of captured waveforms, limitations of display resolution no longer determine ADC accuracy. Therefore, newer DSOs are migrating to 10 and 12 bit A/D converters and are functioning as digital waveform recorders, not merely oscilloscopes. Some sampling oscilloscopes utilize high-speed sampling gates with very small aperture times to effect extremely high input bandwidths, often in the tens of GHz. The sample-rates of these circuits, however, are usually quite slow, around a few megasamples/second. This technique, sometimes called equivalent-time sampling, introduces aliasing whose effects can be tolerated if a narrowband, periodic signal is being viewed. In many instances, however, aperiodic or broadband signals must be digitized mandating Nyquist rate sampling which implies a samplerate greater than twice the bandwidth of the incoming signal. To properly digitize such waveforms, very high sample-rate A/D converters are desirable. Because some DSOs are portable batterypowered units, low-power ADCs are mandatory. The combination of the above converter requirements; 10 to 12 bit resolution, high-speed, and low-power form a formidable set of specications.
1.2 Design Goals

The design goals for this project were established based upon the requirements of the applications described above and upon the capabilities of other A/D converters extant. A summary of reported performance (Fig. 1.10) shows no 10-bit resolution converters capable of 50 Msps operation while consuming less than 1 Watt. To address this need, development of a 10-bit, 100 Msps A/D converter consuming 750 mW was undertaken with the goal of achieving in excess of 9.5 effective bits of resolution for analog input signals at 50 MHz. To ensure that commercially viable techniques were utilized throughout, untrimmed operation was required from standard +5 V and 5.2 V power supplies using a conventional oxide-isolated silicon bipolar process. These performance goals are summarized in table 1.4 along with more explicit specications for measures of dynamic linearity such as signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR). Notice that the SFDR requirement is quite stringent at 65 dB. This is consistent though with the ideal SFDR for a 10-bit ADC which is approximately 90 dB. The bipolar process used for this project provides lateral PNP transistors and trimmable thin-lm Nichrome (NiCr) resistors; however, to keep the design as generally applicable as possible, PNP transistors were not used nor was trimming of resistors allowed.
12
12
650mW [18] 400mW [26]
3.5W, AD 9005
11
Bipolar CMOS BiCMOS This work

2.5W [23]
Resolution (Bits)
10
500mW [19] 150mW [17] 900mW [20]
750mW, Design Goal
180mW [21]
300mW [22] 2.0W [28] 2.7W [27]
75mW [17]
300mW [24]
800mW [12]
2.5W, AD 9028
7
2.0W [13] 12mW [25] 1.6W Siemens SDA 8200
10 100 Sampling Frequency (Msps)
1000
Figure 1.10. A/D converter performance comparison.
Parameter
Resolution Sample Rate Input Bandwidth Power INL DNL SNR SFDR S/(N+D)
Performance Goal
10 100 50 750 1 1/2 59 65 58
Units
bits Msps MHz mW bits bits dB dB dB
Table 1.4. Performance goals for this development.
1.2 Design Goals
13
1.2.1 SHPi Process

The semiconductor process used for this project is called SHPi provided by Tektronix, Inc. of Beaverton, Oregon. SHPi is an oxide-isolated bipolar process with NPN transistors which exhibit a maximum cutoff frequency, ft, of approximately 8.5 GHz. The process provides NPN, PNP, and JFET transistors as well as Schottky diodes, trimmable thin-lm resistors, implanted resistors, and two-level gold interconnect metal. Only NPN transistors, Schottky diodes, and untrimmed resistors were used during this development. Minimum size devices exhibit approximately 4GHz ft at the low bias conditions used. A summary of SHPi NPN device parameters is included in table 1.5.
Parameter
Minimum Device Size Minimum Emitter Size Ic for peak ft ft rb re rc VA tf Cje Cjc Ccs
Value
27 X 15 1.6 X 8 1.0 8.5 100 275 10 100 25 12 33 34 18
Units
m2 m2 m GHz
V ps fF fF fF
Table 1.5. SHPi NPN characteristics.
. The information contained in this section was drawn largely from the SHPi Full Custom Integrated Circuit Design Guide published by Tektronix Integrated Circuits Operation. This document is available as part number 070-7035-00 from Bipolar Products Group, Integrated Circuits Operation, Tektronix, Inc. P.O. Box 500 Beaverton, Oregon 97077.
14
The SHPi process was developed for high-performance analog applications and delivers
excellent component matching. For example, adjacent minimum-size transistors exhibit VBE mismatches with 200V standard deviation. Likewise, mismatches show standard deviations of 1%. Thin-lm resistor matching depends upon geometry and device separation, but with proper design can be reduced to less than 0.5% standard deviation. The complexity of the SHPi process limits integration to only modest levels (810 thousand components for reasonable yield). This limit arises from the large number of mask steps required (14 as shown in table 1.6) when NiCr resistors
Mask Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Layer Name
Buried Layer Isolation Channel Stop Substrate Contact Deep Collector p+ Contact Active Base Emitter Contact Nichrome 1st Metal 1st Via 2nd Metal Passivation
Mnemonic
bl is ch sc dc pp ab e ct ni 1m 1v 2m pa
Table 1.6. SHPi mask layers.
and two layer interconnect are used. An additional mask is necessary to manufacture JFETs on the same substrate, but this option was not invoked. Both layers of interconnect metal are gold with 4m pitch and 60 m/sq sheet resistance. This implementation provides for dense layouts with excellent current-carrying capability and minimal parasitic resistance. To facilitate description of integrated circuit layouts the SHPi mask layers will be consistently drawn as depicted in gure 1.11.
ppp ### ppp ### ppp ###
bl sc ab ni 2m is dc e 1m pa ch pp ct 1v
Figure 1.11.
Fill codes for SHPi mask layers. Layer names refer to those listed in table 1.6. emitter and collector stripes (Fig. 1.13).
1.2 Design Goals
15
A plan view (using the layer ll-patterns shown in gure 1.11) and a cross-section of a minimumsize SHPi NPN transistor is shown in gure 1.12. Larger devices are created by adding multiple
Accurate computer simulation is critical to the successful development of highperformance integrated circuits. Accurate simulations in turn depend upon accurate modeling of device behavior. The transistor model used for simulations during this development was provided by Tektronix and is a macrocell (Fig. 1.14) based on the standard SPICE BJT model. The parameters used with this subcircuit are listed in table 1.7.
16
Figure 1.12. Cross-section and plan view of minimum-size SHPi device.
1.3 General Considerations 1.3.1 Terminology and Notation

Much of the nomenclature commonly used to describe data converters and their related circuits is idiosyncratic to the eld. Therefore, a brief discussion of the more important terminology will now be undertaken. A sample-and-hold (S/H) or track-and-hold (T/H) circuit is frequently required to capture rapidly varying signals for subsequent processing by slower circuitry. Although a S/H refers to a device which spends an innitesimal time acquiring signals and a T/H refers to a device which spends a nite time in this mode, common practice will be followed and the two terms will be used interchangeably throughout this discussion as will the terms sample and track. The function of a track-and-hold circuit is to buffer its input signal accurately during track mode providing at its output a signal which is linearly proportional to the input, and to maintain a constant output level
ppppp p p ppppp p p ppppp p p ppppp p p p p pp p p p p
27 m 15 m
N C2 B E N2 Size: 27 x 15 microns
metal
Oxide p+ ch
n+dc n+ buried layer p- Substrate

Thin Oxide n emitter p+ p n EPI n+ bl p+
Oxide p+ ch
1.3 General Considerations
17
42 m
Oxide p+ ch
p p ppp p p ppp p p p p p p p p p ppp p ppp p p
18 m
N4C C E1 E2 N4 Size: 42 x 18 microns
c Metal
Metal
n+dc n+ buried layer
n+dc
Oxide p+ ch
p-
Substrate
Thin Oxide n emitter p+ p n EPI n+ bl p+
Figure 1.13. Cross-section and plan view of SHPi device.
c rcx dcb rbx b q1 dsub
sub
Figure 1.14. SHPi transistor model used for SPICE simulations.

during hold mode equal to the T/H output value at the instant it was strobed from track to hold by an external clock signal (Fig. 1.15). Several parameters describe the speed and accuracy with which this operation is performed. The track mode is the state when the T/H output follows the T/H input. The hold mode refers to the period when the T/H output is maintained at a constant value. The track-
18
Parameter
ise isc bf br vaf var ikf ikr ne nc rbx rb rbm rcx rc re irb
Value
1.91e16 7.9e16 100 24 25 4.5 5.962 3.084 1.5 1.5 35 237 .1 95 9 9 70
Units
A A
Parameter
tf tr cje cjc
Value
12 12 33 5.7 .65 .65 0.4 0.4
Units
ps ns fF fF V V
V V mA mA
vje vjc mje mjc
dcb A cjo vj mj cjo vj mj 28 .65 0.4 dsub 18 .65 0.4 fF V fF V
Table 1.7. SHPi NPN transistor SPICE model parameters.

to-hold transition is the instant when the circuit switches from the track mode to the hold mode and the hold-to-track transition refers to the switch from hold mode back to track mode. The time between successive track-to-hold transitions is the sample period whose reciprocal is the sample rate. While in trackor samplemode, the T/H functions as a simple buffer amplier. Operation in this mode is described by the same specications which characterize any analog amplier such as gain, offset, bandwidth, nonlinearity, distortion, slew rate, and settling time. These parameters are not peculiar to T/H circuits and need not be elaborated upon further. While in the hold mode two effects are of primary importance. The rst is droop which
19
Amplitude
Acquisition time Track time Settling time A/D Conversion time
Track/Hold Output
Track/Hold Input
Hold
Sample
Hold
Time
Figure 1.15. Track-and-hold terminology.

describes the decay of the output signal as energy is lost from the storage element (usually a capacitor) within the T/H circuit. Droop is frequently caused by leakage or bias currents discharging a capacitor and manifests itself as an approximately constant increase or decrease of output voltage with time. The second important aspect of hold mode performance is feedthrough which describes the unwanted presence at the T/H output of a signal component proportional to the input signal. The feedthrough signal is usually described as the ratio of the unwanted output signal to the input signal amplitude. The acquisition time is the duration during which the T/H must remain in the track mode to enable the circuit to accurately replicate the input signal, thereby ensuring that the subsequent hold mode output will lie within a specied error band of the input level that existed at the track-to-hold transition (after gain and offset effects have been removed). The remainder of time during the track mode exclusive of acquisition time is called the track time during which the T/H output is a replica of its input. The settling time describes the interval between the track-to-hold transition and the time when the T/H output has settled to within a certain error band of its nal value. The remainder of the time during the hold mode represents the maximum time available for A/D conversion if the T/H is used for that purpose. Conversion time of an A/D converter is the interval between the convert command and the instant when the digital code is available at the ADC output. Therefore, the minimum sample period of a practical A/D converter system is the sum of acquisition time,
20
settling time, and conversion time. The track-to-hold transition determines many aspects of T/H performance. The delay time is the time elapsed from the execution of the external hold command until the internal track-to-hold transition actually begins. In practical circuits this switching occurs over a non-zero interval called the aperture time measured between initiation and completion of the track-to-hold transition. Practical circuits do not exhibit precisely the same sample period for each sample. This random variation from sample to sample is caused by phase noise on the incoming clock signal and further exacerbated by electronic noise within the T/H itself. The standard deviation of the sample period is termed the aperture jitter and limits amplitude resolution in A/D conversion. Finally, at the trackto-hold transition, circuit effects frequently give rise to a perturbation at the T/H output. This effect which manifests itself as a discontinuity in the T/H output waveform called hold jump or hold pedestal can depend on the input signal giving rise to distortion. A quantizer is a device which maps a continuous range of input levels onto a nite set of discrete digital code words. An analog-to-digital converter (A/D converter) comprises a quantizer along with other signal conditioning circuitry such as ampliers, lters, T/H circuits etc. In spite of this difference, the terms quantizer and A/D converter are often used synonymously. A quantizer can be uniquely described by its transfer function or quantization characteristic which indicates the devices discrete outputs as a function of the continuous input signal. The quantization characteristic therefore contains two sets of information: the rst includes the digital codes associated with each output state, and the second includes the threshold levels which are the set of input amplitudes at which the quantizer transitions from one output code to the next (Fig. 1.16). The digital coding can take on one of several forms including natural binary, sign plus magnitude, offset binary, ones complement, twos complement, binary coded decimal (BCD), and Gray code each of which has advantages in particular applications. An ADCs actual threshold levels are denoted by Tk where the index k ranges from 0 to M giving a total of M + 1 values. Correspondingly, ideal thresholds levels are denoted Tk*. The ideal thresholds can be located arbitrarily along the abscissa; however, evenly spaced thresholds are most common. (Such devices are called uniform quantizers.) In general, optimum performance results when the threshold locations match the probability density function of the incoming signal. However, in the absence of a priori knowledge of the input signal statistics, uniform quantization outperforms other arrangements. Therefore, uniform quantizers are most commonly used and will be dealt with exclusively here. Quantizers whose ideal thresholds are
21
Output
111
Output 1110
1111
Quantization Levels
101
110
Quantization Levels
1101 1100
100 Input
Output Codewords
010
011
Input
Output Codewords Threshold Levels
001
Threshold Levels
0001 0000
0011 0010
000
(a)
(b)
Figure 1.16. Quantizer transfer functions or quantization characteristics. (a)

Uniform quantizer. (b) Non-uniform quantizer. located symmetrically about the origin are called bipolar quantizers while those whose thresholds are restricted to positive (or negative) values are termed unipolar (Fig. 1.17). Note that these
Output 7/2
Output
5/2
+FS
5
FS FSR
-3 -2 -1
3/2
1/2 1 2 3 Input
-1/2
-3/2
-FS
-5/2
FSR
0 0 1 2 3 4 5 6 7 Input -7/2
(a)
(b)
Figure 1.17. Unipolar (a) and bipolar (b) quantization characteristics.
characteristics differ only in the location of their respective origins. The Full-Scale Range, FSR, of a uniform quantizer represents that portion of the transfer function domain spanned by M equal-
22
length intervals between adjacent ideal thresholds. The length of these intervals is called the quantization step or simply Q. The relationship between the Full-Scale Range and the quantization step can be stated succinctly:
Q =
FSR M
(1.1)
A term related to Full-Scale Range is Full-Scale, FS, which is the magnitude of the Full-Scale Rangess maximum excursion from the transfer function origin. Because bipolar and unipolar quantization characteristics differ in their denition of the origin, the meaning of Full-Scale varies when applied to differing types of characteristics. In a unipolar quantizer the Full-Scale Range spans from 0 to FSR, so FS = FSR while in a bipolar quantizer the Full-Scale Range is centered at the origin spanning from FSR 2 to FSR 2 , so FS = FSR 2 . Figure 1.17 illustrates these differences. Quantization levels, ( Q k* , k = 0, , M 1 ), are assigned values midway between adjacent ideal thresholds, i.e. Q k* = ( T k* + T k + 1* ) 2 . These outputs must be so assigned because the corresponding digital code words have no specic analog value. Therefore, the gain of the A/D converter is implicitly dened. Figure 1.18 illustrates the two most common quantization
Output 3
Output 7/2
5/2 2 3/2 1 1/2 -5/2 -3/2 -1/2 1/2 -1 -3/2 -2 -5/2 -3 -7/2 3/2 5/2 Input -3 -2 -1 -1/2 1 2 3 Input
(a)
(b)
Figure 1.18. Ideal quantizer transfer functions. (a) Midtread characteristic. (b) Midriser characteristic.
23
characteristics, the midtread characteristic and the midriser characteristic. For an N-bit bipolar (unipolar) quantizer, a midtread characteristic has M + 1 = 2 thresholds and has one quantization level with value zero ( FSR 2 ). A midriser characteristic has M + 1 = 2 + 1 thresholds, one of which has value zero ( FSR 2 ). By convention, T 0 and T M for each characteristic so N only M 1 physical thresholds actually exist. Midriser quantizers have M = 2 quantization levels which map neatly onto the 2 binary output codes expressible with an N-bit digital word. For this reason midriser quantizers are utilized more frequently than their midtread counterparts. The ideal thresholds and quantization levels for a uniform quantizer whether bipolar or unipolar, midtread or midriser can be dened by the following relationships:
N N N
T k* = kQ Off T Q k* = kQ Off Q Q, M, Off T, and Off Q are related as follows:
for for for for
k = 0 1kM1 k = M 0kM1 .
(1.3) (1.2)
Midriser: Midtread: Q=
M = 2
M = 2 1 FSR M Off T = 0 Off Q = 0 M Q 2 ( M 1) Q Off Q = 2 Off T =
(1.4)
Unipolar:
Bipolar:
Figure 1.19 depicts an ideal (bipolar, midriser) quantization characteristic showing the relationship
24
between these values.
QM 1 QM 2
T0
T1
TM
2
TM
2
+1
TM 1
TM =
TM
2 Q1 Q0
Figure 1.19. Quantizer notation, threshold and quantization levels.
Real quantizer transfer functions fall short of the ideal because imperfections in fabrication cause actual thresholds to deviate from their desired placement. Such non-idealities can be expressed in several ways (Fig 1.20). An error which causes all thresholds to shift from their ideal positions by an equal amount is called an offset and is usually denoted . Non-ideality which results in an erroneous quantizer step size, Q, is called gain error or scale-factor error. Q can be dened as a function of FSR (equation 1.1) or alternatively Q can be assigned the value which minimizes threshold errors as calculated by linear regression. In the latter case equation 1.1 still holds, but FSR is a function of Q instead of vice-versa. Linearity error refers to the deviation of the actual threshold levels from their ideal values after offset and gain errors have been removed. Excessive linearity error results in missing codes, a condition wherein a valid output code, say Qj, never occurs because its dening interval [ T j, T j + 1 ] has become vanishingly small, T j + 1 T j . Linearity error is quantied by the threshold level errors,
k = T k T k*
(1.5)
25
Output 7/2 7/2
Output
5/2 Ideal Actual 3/2 Ideal Actual
5/2
3/2
1/2 -3 -2 -1 -1/2 1 2 3 Input -3 -2 -1
1/2 1 2 3 Input
-1/2
-3/2 Offset Error
-3/2
-5/2
-5/2
-7/2
-7/2
(a)
Output 7/2
(b)
Output 7/2
Ideal Actual
5/2
Ideal Actual
5/2
3/2
3/2 Missing Code -1/2 1 2 3 Input
1/2 -3 -2 -1 -1/2 1 2 3 Input -3 -2 -1
1/2
-3/2
Threshold Errors
-3/2
-5/2
-5/2
-7/2
-7/2
(c)
(d)
Figure 1.20.
Quantization transfer functions including error sources (a) Offset error. (b) Gain error. (c) Linearity error. (d) Missing codes. where k is dened for thresholds 0 through M but has meaning only for the real thresholds 1 through
M 1 . This array of error terms, also called Integral Nonlinearity or simply INL, is frequently
described by its peak value or its root-mean-square (rms) value:
M1
e =
1 2 k M 1 k = 1
(1.6)
26
Related to INL is the Differential Nonlinearity or DNL:
dk = Tk Tk 1 Q .
(1.7)
Since DNL is dened by a rst-order difference equation, it is valid only for the range 1 k M and only has physical meaning over 2 k M 1 . The M 2 element array of DNL values is also frequently described by its statistical properties such as peak and rms. The terms integral and differential arise when describing the above two error measures because DNL can be dened as the rst-order difference of the INL sequence.
dk = Tk Tk 1 Q = T k T k 1 ( T k* T k 1* ) = ( T k T k* ) ( T k 1 T k 1* ) = k k 1
(1.8)
Several terms are commonly used to describe the relative power of the analog input to an A/D converter. The loading factor, LF, expresses the rms amplitude of the input waveform relative to the quantizer FSR:
LF =
rmsamplitudeoftotalinput FSR 2
(1.9)
The reciprocal of loading factor is referred to as crest factor, CF, which is in turn related to the signal factor, SF. Signal factor differs from crest factor by including the rms value of only the signal input while crest factor includes the rms of the signal plus noise input.
SF =
FSR 2 rmsamplitudeofsignalinput
(1.10)
1.3.2 Quantization
The quantization process can be described by a nonlinear inputoutput transfer function as depicted in gure 1.21 and described in section 1.3.1. The quantized output signal, Q ( x ) , is the
27
Nonlinearity Input x Output Q ( x)
(a) Input x Quantization Noise (b) Figure 1.21. Quantizer models. (a) Nonlinear model. (b) Statistical model.
sum of the original input signal, x, and a quantization error, U ( x ) where
Output Q ( x) = x + U ( x) U ( x)
U ( x) = Q ( x) x .
(1.11)
Here U ( x ) is the error resulting when the input signal, x, is quantized with nite resolution. This quantization error, as shown in gure 1.22, is a deterministic function of the input signal, x. However, subject to certain simplifying constraints [7], [8]; U ( x ) can be approximated as a random noise component. The constraints necessary to justify this statistical model are:
U ( x ) is a stationary process U ( x ) is uncorrelated with x

The elements of U ( x ) are uncorrelated with each other The probability density function of U ( x ) is uniform over ( Q 2, Q 2 )
. The description of quantization in this section follows that given in by Martin and Secor in High speed analogtodigital converters in communication systems: Terminology, architecture, theory, and performance, D. R. Martin and D. J. Secor, tech. rep., TRW Electronic Systems Group, Redondo Beach, CA, Nov. 1981.
28
U ( x) Q2 FSR/2 x -FSR/2 Q 2 (a) U ( x) Q2 FSR/2 x -FSR/2 Q 2 (b) Figure 1.22.

Quantization noise models. (a) Ideal quantizer. (b) Quantizer with threshold level errors.
Under these constraints U ( x ) is often modelled as a uniformly distributed random variable thereby simplifying the analysis of quantizer performance. Quantizer operation is frequently characterized by signal-to-noise ratio (SNR) which expresses (usually in decibels) the ratio of the output signal power to the output noise power. Since the quantization noise is assumed to be uniformly distributed on ( Q 2, Q 2 ) (Fig. 1.23) the
1Q
pQ ( x)
x Q 2 Q2
Figure 1.23. Distribution of quantization error.

output noise power, or variance, can be easily calculated.
29
2 Q
x pQ ( x ) dx
2 Q2
= =
Q 2
1 dx Q
(1.12)
Q2 Q 2
1 1 3 x Q 3
1 Q3 Q3 = ( ) 8 3Q 8 = Q 12
2
The power of the output signal (assuming a quantizer with unity gain) can be calculated as a function of the loading factor, LF.
2 = LF ( FSR 2 ) S
= LF ( 2 Q 2 )
= LF Q 2
2 2N
(1.13)
where a midriser characteristic has been assumed. The quantizer SNR is therefore given by:
SNR Q =
2 S 2 Q
LF Q 2
2
2 2N
Q 12
= 32
2N
LF
(1.14)
where the subscript Q modifying SNR refers to quantization noise as distinct from thermal noise or other deleterious error sources which compromise overall signal to noise ratio. In decibels, this expression simplies to
SNR Q = 6.02N + 4.77 + 20 log ( LF ) dB .
(1.15)
When evaluated for a sinusoidal input with amplitude equal to Full-Scale (i.e. LF = 1 2 ) the
30
SNR expression evaluates to
SNR Q = 6.02N + 1.76dB
(1.16)
which is a frequently used equation for predicting optimum A/D performance. For a 10-bit converter maximum SNR is 61.97 dB. Another formulation based upon equation 1.14 and using the input amplitude to determine the signal power gives the following alternative expression for quantizer SNR under the condition of a sinusoidal input:
SNR Q =
2 S 2 Q
A 2 Q 12
2
= 6 ( A Q)
(1.17)
which when expressed in decibels simplies to
SNR Q = 20 log ( A Q ) + 7.78dB .
(1.18)
This formula, equivalent to equation 1.15, emphasizes that under the present assumptions, SNR depends only upon the input amplitude relative to the quantizer step, Q. A quantizer at peak loading (i.e. with the input amplitude, A = ( 2 2 ) Q ) gives maximum signal-to-noise ratio
N
SNR Max =
2 S 2 Q
A= 2 Q 2
N
= 6
( 2 2) Q Q
3 2N 2 2
(1.19)
which equates to equation 1.16. Because they express the relationship between quantizer resolution and maximum achievable SNR, equations 1.16 and 1.19 can be used to assess the performance of any quantizer relative to the ideal. By replacing the maximum achievable SNR by the actual SNR and solving for the equivalent resolution, N, a gure of merit called the number-of-effective-bits, Neff, results.
N eff = log 2 (
2 SNR ) Actual 3
12
1 2 log 2 ( SNR ) Actual 2 3
(1.20)

or if SNR is known in decibels,
31
N eff =
SNR Actual 1.76

dB
6.02
(1.21)
The number-of-effective-bits (sometimes referred to as effective-number-of-bits, ENOB) is a commonly used metric for summarizing the performance of non-ideal quantizers. Equation 1.15 predicts that the SNR in dB will increase linearly with increasing loading factor (also in dB). This relationship holds until maximum SNR is achieved at LF = 1 2 for sinusoidal inputs. Further increases in loading factor yield decreasing SNR because the quantizer becomes overloaded (i.e. the quantizer input exceeds Full-Scale) thereby producing a severely distorted output. In practice, A/D converters encounter inputs which are more complicated than simple sinusoids. Under conditions with such complicated signal environments, the A/D converter input can be simulated by a Gaussian noise source. The ratio of the input noise power to the quantization noise power can then be used as a measure of quantizer delity. This performance metric is call noise-power-ratio, NPR, and is calculated in a manner similar to SNR. Equations 1.12 and 1.13 are again used to predict the quantization noise power and signal noise power respectively with the modication that the signal power is due to a Gaussian noise input as characterized by its power relative to the quantizer loading factor, LF. Therefore, equation 1.15 predicts NPR as well as SNR if the proper value of LF is used. To minimize overload with a Gaussian input, a substantially reduced LF as compared to the sinusoidal input case must be used. For example, reducing the Gaussian input standard-deviation to one fourth of the Full-Scale amplitude (LF=1/4) reduces the probability of overload to 0.0064%, 1 erf (4 2) . This selection results in the following simplied expression for NPR:
NPR Q = 6.02N 7.27 dB
(1.22)
The above simplied analyses are based upon the assumptions that quantization noise is uniformly distributed and uncorrelated with the input signal. These assumptions are only approximated in practice, and to the extent that such approximations are invalid the preceding derivations will produce erroneous results. In particular, the preceding equations for SNR and NPR neglect overloading effects and therefore predict unbounded performance for increasing loading
32
factor. A more accurate analysis of quantizer distortion based on work by Max [9] and modied by Martin and Secor [10] which avoids the aforementioned simplifying assumptions follows. The mean-square quantization error for a quantizer whose input is x with probability density function P x ( x ) and whose output is U ( x ) can be expressed as
2 Q
[ U ( x ) x ] P x ( x ) dx
2
(1.23)
= E { [ U ( x) x] }
where E { } represents the expectation operator. Note that the quantization error depends on the probability density of the input and is not assumed to be uniformly distributed. If we dene the quantizer output as a noise component plus a signal component with a possibly non-unity gain term, i.e.,
U ( x ) u = gs + n Q
(1.24)
then by suitable selection of the signal gain, g, we can ensure that the quantization noise, n Q , is uncorrelated with the output signal, gs. Zero correlation between output signal and output noise means
0 = E { gs n Q } = E { gs ( u gs ) } = E { gsu } E { gsgs }
which implies (1.25)
gE { su } = g E { s }
Therefore,
(1.26)
g =
E { su } E {s }
2
(1.27)
33
This value of g ensures that gs is a minimum mean-square estimate of the input, u. Note that the quantization error, n Q , is not assumed to be uncorrelated with the input as in the previous simplied analysis. The SNR of the quantizer is given by
SNR =
PS PT PS PN
(1.28)
where PS is the output signal power,
P S = E { ( gs ) } = E {g s } = g E {s } = = E { su } E {s } [ E { su } ] E {s }
2 2 2 2 2 2 2 2
E {s }
(1.29)
PT is the total output power,
PT = E { u }
(1.30)
and PN is the output noise power resulting from input noise. PN can be calculated in exactly the same manner as PS with the input, s, taken to be the noise component of the total input. This substitution results in an expression for PN corresponding to equation 1.29:
PN =
[ E { nu } ] E {n }
2
(1.31)
The SNR of a quantizer can be calculated given the statistical properties of its input by determining PS,
2
PT,
2
and
2
PN
which
in
turn
requires
evaluation
of
E { s } , E { u } ,E { n } ,E { su } ,andE { nu } . This procedure will be performed for a

sinusoidal input and for a Gaussian input. A quantization characteristic, f(x), can be represented by
34
M1
f ( x) =
i=0
Qi I (x,Ti, Ti + 1)
(1.32)
where I ( x, a, b ) is the indicator function dened by
I ( x, a, b ) = {
1if a x < b 0otherwise
(1.33)
and M, Qi, and Ti are as dened previously in section 1.3.1. For concreteness a bipolar, midtread quantizer characteristic will be assumed resulting in M = 2
N
quantization levels and
M = 2 1 threshold levels, Q i* = ( i M 1 + )Q 2 2 M T i* = ( i ) Q 2 0iM1 i=0 1iM1 i=M

(1.35) (1.34)
For a Gaussian input with probability density function

x 22
2
Pn ( x ) =
1 2
2
(1.36)
35
(which is plotted in normalized form in gure 1.24) the total output power from the quantizer is
.75
P n ( x )* Pn(x) A Fn ( x ) Fn(x) Gn(x)/A Gn ( x ) ff(x) (x)

.5
1 2
Pn ( x ) = Gn ( x )
.25
-3
-2
-1
0 x x/sigma
The functions P n ( x ) , F n ( x ) , and G n ( x ) . By plotting the normalized versions P n ( x ) , F n ( x ) , and G n ( x ) versus x the
Figure 1.24.
shapes of the above functions become independent of . Also, P n ( x ) equals G n ( x ) .
36
PT =
M1
[ f ( x ) ] P n ( x ) dx
i=0 2
Qi [ Fn ( Ti ) Fn ( Ti + 1 ) ]
2 M1 i=1 2
(1.37)
M1 j=1
= Q0 Fn ( T0 ) +
M1
Qi Fn ( Ti )
Qj 1 Fn ( Tj ) QM 2 Fn ( TM )
2 2
2 Q0
i=1
( Qi Qi 1 ) Fn ( Ti )
where F n ( x ) (also plotted in gure 1.24) is the complementary integral of the Gaussian probability density function, related to the familiar complementary error function.
Fn ( x ) =
Pn ( u ) du
x
(1.38)
Here the dependence upon has been left implicit for clarity. In the reduction of equation 1.37 to its most simplied form the identities F n ( ) = 1 and F n ( ) = 0 were used to replace F n ( T 0 ) and F n ( T M ) respectively. Note that if ideal thresholds are used T i is replaced by T i* , Q i is replaced by Q i* , and ( Q i* ) ( Q i 1* ) simplies to 2T i* Q . The correlation between the input Gaussian noise, u, and the output noise, n, is
2 2
E { nu } =
xf ( x ) Pn ( x ) dx
i=0
M1
= =
Qi
Ti + 1
xP n ( x ) dx
(1.39)
Ti
M1 i=1
( Qi Qi 1 ) Gn ( Ti )
where G n ( x ) , the complementary integral of the weighted Gaussian probability density function,

is given by:

37
G n ( x ) = uP n ( u ) du =
x
2
2
e dz
(1.40)
2 2
and is plotted in gure 1.24. The input noise power is E { n } = which can be combined
2
with E { nu } to give the output noise power,
Pn =
[ E { nu } ] E {n }
2
[ E { nu } ] 2
(1.41)
The resultant NPR at the quantizer output is
NPR Q =
Pn PT Pn
(1.42)
where Ps from equation 1.28 is ignored since a Gaussian noise source is being used. Note that this calculation requires approximately M evaluations of F n ( x ) , the complementary integral of
P n ( x ) , and M evaluations of G n ( x ) , the complementary integral of xP n ( x ) for each value of

the input parameter , hence LF. A plot of the NPR based upon this method (Fig. 1.25) indicates an approximately linear dependence of NPR on LF for small values of LF in agreement with the simplied result in equation 1.15. Also evident in this region is the 6 dB per bit dependence of NPR upon resolution. However, the new plot more accurately predicts NPR at high LF by accounting for the effects of overloading. These overloading effects are ignored by the previous approach leading to erroneous results. Efcient system design mandates judicious selection of loading factor to optimize quantizer NPR, and the above results serve as a guide in this regard. Optimum loading factor, crest factor (the reciprocal of loading factor), and NPR are tabulated in table 1.8 This information, also presented graphically in gure 1.26, can be used when selecting system gain parameters to achieve desired performance in a complex signal environment where A/D overloading is unavoidable. Similar analysis to that performed for Gaussian noise inputs can be applied for the case of
38
70
N=12
60
11 10 9
50
NPR (dB)
40
8 7
30
6 5 4
20
10
3 N=2
0 -20
-18
-16
-14 -12 Loading Factor (dB)
-10
-8
-6
Figure 1.25.
NPR of ideal midriser quantizer with Gaussian noise input. Quantizer resolution indicated on curves.
Resolution (Bits)
2 3 4 5 6 7 8
Optimum Loading Factor (dB)

5.98 7.40 8.57 9.57 10.45 11.22 11.90
Optimum Crest Factor

1.99 2.34 2.68 3.01 3.33 3.64 3.94
Optimum NPR (dB)

8.70 14.10 19.33 24.55 29.82 35.17 40.57
Table 1.8. Optimum quantizer loading and NPR for Gaussian noise input.
39
Resolution (Bits)
9 10 11 12 13 14 15 16
Optimum Loading Factor (dB)

12.51 13.06 13.55 14.00 14.42 14.80 15.14 15.47
Optimum Crest Factor

4.22 4.50 4.76 5.01 5.26 5.49 5.72 5.94
Optimum NPR (dB)

46.03 51.55 57.11 62.71 68.35 74.01 79.70 85.41
Table 1.8. Optimum quantizer loading and NPR for Gaussian noise input.
0 -2 -4 Optimum Loading Factor (dB) -6 -8 -10 -12 -14 -16 -18 -20
100 90 80 70 Maximum NPR (dB) 60 50 40 30 20 10 0
8 10 Resolution (Bits)
12
14
16
Figure 1.26. Optimum loading factor and NPR for Gaussian noise input.
sinusoidal inputs to ascertain quantizer SNR under such conditions. For a sinusoidal input with
40
amplitude A the probability density function is
1 for x < A P s ( x ) = A2 x2 0otherwise
(1.43)
which is plotted in gure 1.27. Identical analysis which led to the use of F n ( x ) , the
1.5
1.25
P s ( x ) * A Ps(x) A Fs ( x ) Fs(x) Gs(x)/A Gs ( x ) A
ff(x)) (x
.75
.5
.25
-1
-.5
xx/A A
.5
Figure 1.27.
The functions P s ( x ) , F s ( x ) , and G s ( x ) . By plotting the normalized versions P s ( x ) A , F s ( x ) , and G s ( x ) A versus x A the shapes of the above functions become independent of A .
complementary integral of the Gaussian probability density function, in equation 1.37 necessitates
41
utilization of F s ( x ) , the complementary integral of the sinusoidal probability density (Fig. 1.27):
A
F s ( x ) = P s ( u ) du =
x
1 A u
2 2
du
(1.44)
1 1 x asin ( ) A 2 = 1 0
x < A x < A x> A
Likewise, calculation of the correlation between the input sinusoid and the output signal requires evaluation of the complementary integral of the weighted sinusoidal probability density function,
G s ( x ) , (Fig. 1.27) which has the form:

A
G s ( x ) = uP s ( u ) du =
x
u A u x A x >A
2 2
du
. (1.45)
1 A2 x2 = 0
These two functions, F s ( x ) and G s ( x ) , can be used with the following equations (analogous to equations 1.37 through 1.39 derived for the Gaussian input case) to determine the total output power, PT, and E { su } .
PT =
M1
[ f ( x ) ] P s ( x ) dx
(1.46)
i=0
2 Qi
[ Fs ( Ti ) Fs ( Ti + 1 ) ]
2 Q0
M1
i=1
( Qi Qi 1 ) Fs ( Ti )
42
Since F s ( x ) is 1 for x < A and 0 for x > A this expression for P T can be further simplied to
2 QJ 1
PT =
i=J
( Qi Qi 1 ) Fs ( Ti )
2 2
(1.47)
where J is the smallest integer such that A < T J and K is the largest integer such that T K < A . E { su } is calculated as follows:
E { su } =
xf ( x ) Ps ( x ) dx
i=0
M1
= =
Qi
Ti + 1
xP s ( x ) dx
(1.48)
Ti
M1 i=1
( Qi Qi 1 ) Gs ( Ti )
This expression can also be simplied if the input amplitude is less than V FS to
E { su } =
i=J
( Qi Qi 1 ) Gs ( Ti ) = Q Gs ( Ti )
i=J 2 2
(1.49)
where J and K are dened as above. Since the input signal power is known, E { s } = A 2 , the output signal power can be easily calculated
Ps =
[ E { su } ] E {s }
2
[ E { su } ] A 2
2
(1.50)

This expression can be expanded using equation 1.49 giving
43
Ps = =
Q Gs ( Ti )
i=J
A 2 2Q A
2 2
=
2
2Q A
2 2
i=J
Gs ( Ti )
(1.51)
i=J
A Ti
2Q
i=J
Ti 1 ( ) A
The signal to quantization noise ratio is then given by
SNR Q =
Ps PT Ps
(1.52)
where Pn from equation 1.28 is ignored since a noiseless source is assumed. As in the Gaussian noise input case, determination of the SNR requires M evaluations of F s ( x ) and M evaluations of G s ( x ) for each value of the sinusoidal input amplitude, A. By performing these calculations, the plot of SNR versus loading factor, LF, found in gure 1.28 results. Note the approximate linear dependence of SNR on loading factor (when both are expressed in dB) and the 6 dB per bit dependence of SNR on resolution. Both of these trends are predicted by the simple approximation of SNR found in equation 1.15. However, gure 1.28 indicates two additional characteristics not predicted by that equation. First, SNR degrades for loading factors which lead to clipping of the input sinusoid (LF greater than 3 dB). Second, SNR deviates slightly from linear dependence upon LF with each trace exhibiting a series of bumps along the SNR curve. These bumps arise because of the non-uniform probability density of the input sinusoid which is near its peak a high percentage of the time. As the loading factor increases, the sinusoid peak travels from one threshold to the next resulting in small variations in SNR. The local SNR minima occur when the input sinusoids peak equals a quantizer threshold while the local SNR maxima occur when the input peak is midway between thresholds. The data displayed in gure 1.28 is more exhaustive than might appear at rst glance because for unclipped sinusoidal inputs, SNR depends solely on the input amplitude and not on the quantizer resolution. Therefore, a quantizer with a given loading factor and resolution
44
80
N=12 11
60
10 9
SNR (dB)
40
7 6 5 4
20
3 N=2
0 -12
-10
-8 -6 Loading Factor (dB)
-4
-2
Figure 1.28. SNR of ideal midriser quantizer with sinusoidal input. Quantizer
resolution indicated on curves. behaves identically to another quantizer with different resolution but loading factor adjusted appropriately to maintain constant input amplitude (measured in LSBs or Q steps). Since loading factor is inversely proportional to the quantizer Full-Scale Range,
LF =
rmsofinput FSR 2
1 A 2 2 A 2 A = = ( ) = N ( ), M M Q 2 Q Q 2
N
(1.53)
maintaining constant amplitude, A, requires a constant LF 2 product. Therefore, if an increase in resolution by one bit is accompanied by a reduction in loading factor of 6.02 dB, identical SNR will be obtained. For example, referring to gure 1.28, the SNR indicated on the N=3 curve at LF= 4 dB (approximately 19.7 dB) is repeated exactly on the N=4 curve at LF= 10.02 dB. This technique can be used to ascertain the SNR for any resolution quantizer (up to N=12) with any
45
loading factor (assuming no clipping) from the gure. A 12-bit quantizer with 61 dB loading factor can be seen from the N=3 curve at LF= 6.82 (61 + 6.02(123)) to exhibit an SNR of 17 dB. Alternatively, the exclusive dependence of SNR on amplitude can be emphasized by plotting SNR versus amplitude, A, independent of quantizer resolution (Fig. 1.29). In this format, the SNR is seen
40
30 Actual SNR Approximation SNR (dB) 20
10
12 16 20 Amplitude (LSBs)
24
28
32
Figure 1.29. SNR of ideal midriser quantizer plotted versus sinusoidal input amplitude. Approximation is based upon equation 1.17.
to depend solely on input amplitude with local minima occurring when the amplitude equals a threshold value and maxima occurring between thresholds. The approximation for SNR included in this graph along with the actual SNR data follows equation 1.17 and is accurate to within 1/2 dB for amplitudes above 16 LSBs (Fig. 1.30). Similar analysis to that performed above for the Gaussian and sinusoidal input cases can determine quantizer SNR (or NPR) for any input signal whose statistics are known. Additionally, the above technique can be easily modied (by substituting T i* for T i and Q i* for Q i ) to predict
46
SNR (dB)
-1
-2
12 16 20 Amplitude (LSBs)
24
28
32
Figure 1.30. Difference between actual SNR and approximated SNR from
gure 1.29. performance of non-ideal quantizers. This procedure, although more accurate than other approaches, is mathematically tedious and numerically intensive. Therefore, the simple and intuitive approximation of equation 1.15 remains a powerful and frequently-used predictor of quantizer signal-to-noise ratio. Until now quantization noise power has been calculated without regard to spectral content while determining signal-to-noise ratio. However, in many applications the quantization noise spectrum of an A/D converter is of particular interest. The spectrum of an instantaneous nonlinear quantization characteristic can be determined by calculating the Fourier series expansion of a quantizer output in response to an input sinusoid. Since the quantizer is assumed to be timeinvariant, its output corresponding to an input sinusoid with period T will also be periodic with period T, thus permitting a Fourier series expansion. If an input signal x ( t ) = A cos ( 2t T ) is applied to an ideal quantizer (the rationale for selecting the amplitude A will become evident shortly), the resultant output waveform will be
47
Q ( t ) = f ( x ( t ) ) = f ( A cos ( 2t T ) )
(1.54)
where the function f ( ) represents the quantization characteristic previously described in equation 1.32 (and repeated here for convenience).
M1
f ( x) =
i=0
Qi I (x,Ti, Ti + 1)
(1.55)
and I ( x, a, b ) is the indicator function dened by
I ( x, a, b ) = {
1if a x < b 0otherwise
(1.56)
Using equations 1.54 through 1.56 the quantizer output can be expressed as
M1
Q ( t) =
i=0
Qi I ( t, ti, ti + 1 )
(1.57)
where the values t i represent the time at which the input sinusoid crosses the threshold T i .
ti =
Ti T 1 cos ( ) 2 A
(1.58)
The motivation for selecting the sinusoidal amplitude as A is now apparent. Since the inverse cosine function monotonically decreases with its argument, selecting a negative sinusoidal amplitude ensures that the values of t i will increase with the index, i, from the smallest value to the largest as the thresholds, T i , index from the most negative value to the most positive. This simple denition is problematic however, because the inverse cosine is undened for arguments whose magnitude is greater than 1, a condition which arises in equation 1.58 for any thresholds, T i , whose magnitude is greater than A. Since this situation implies that some thresholds are never crossed and their corresponding quantization levels never appear at the output, Q ( t ) , a simple solution lies in restricting the range of summation in equation 1.57 to those values of Q i which actually occur for a given input level, A. The range over which the time points t i are dened is likewise suitably limited by using the variables J and K where J is the smallest integer such that A < T J and K is
48
the largest integer such that T K < A . The quantizer output becomes
Q ( t) =
i = J1
Q i I ( t, t i, t i + 1 )
for 0<t<T 2
(1.59)
where the time instances t i are
ti =
Ti T 1 cos ( ) 2 A
JiK
(1.60)
The endpoints of the time interval are arbitrarily chosen to be t J 1 = 0 and t K + 1 = T 2 . Also, the symmetry of the input cosine can be used to dene the quantizer output over the interval
T 2 t T. Q ( t) = Q ( T t) for T 2 t T
(1.61)
The periodic quantizer output can be expressed as a Fourier series
a0 + Q ( t) = 2
n=1
an cos (
n2t n2t ) + b n sin ( ) T T
(1.62)
where the coefcients a n and b n of the expansion are:
2 an = T
Q ( t ) cos (
0 T
n2t ) T
(1.63)
2 bn = T
Q ( t ) sin (
0
n2t ) T
(1.64)

Substituting the expression for Q ( t ) (equation 1.59) into the denition for a n yields
T2
49
4 an = T 4 = T = =
0 i = J1
Q i I(t, t i, t i + 1) cos (
ti + 1
n2t ) dt T
i = J1
Qi
ti
cos (
n2t ) dt T n2t i + 1 n2t i ) sin ( ) T T n2t i ) T

(1.65)
2 n 2 n
i = J1 K i=J K
Q i sin (
( Qi 1 Qi ) sin (
i=J
2Q n
sin (
n2t i ) T
which can be further simplied by noting that each value of t i is multiplied by the term 2 T . By modifying the denition of t i to exclude the unnecessary term T 2 , a n simplies to
2Q an = n
with t i dened as
1
i=J
sin ( nti )
(1.66)
t i = cos
Ti ) A
for J i K
(1.67)
Because Q ( t ) is an even function, it is orthogonal to sin ( n2t T ) ; therefore, all of the b n coefcients are zero. The expansion for Q ( t ) is therefore
a0 Q ( t) = + 2
n=1
an cos (
n2t ) T
(1.68)
50
The power in each harmonic, P ( n ) , is simply related to its Fourier coefcient:
P ( n) =
1 2 a 2 n
(1.69)
When compared to the power in the fundamental component of the output signal the harmonic distortion results.
HD n =
P ( n) P ( 1)
1 2 2 a an 2 n = = 2 1 2 a1 a 2 1
(1.70)
which when expressed in dBc becomes
an an HD n = 10 log 2 = 20 log a a1
1
(1.71)
The coefcient of the fundamental component, a 1 , can be simplied as follows
2Q a1 = = 2Q
i=J K
sin (cos
i=J
(
2
Ti )) A
(1.72)
Ti 1 ( ) A
. Here the notation noise power,
P ( n ) is used for the power in the n-th harmonic to avoid confusion with the
Pn .

Using equation 1.69 with equation 1.72 to calculate the fundamental signal power gives
51
Ps = P1 = a1 2 = 1 2Q ( ) 2 2Q
2 K 2
i=J
Ti 1 ( ) A
2 2
(1.73)
i=J
Ti 1 ( ) A
Notice that this expression for signal power is identical to equation 1.51 which predicts quantizer output signal power based upon the statistics of the input signal Equation 1.73 indicates that P s is the weighted sum of positive ordinates along the unit circle as the abscissa is stepped uniformly within the range (1,1). It is instructive to examine the form of the Fourier coefcients, a n , to ascertain the nature of the distortion products emanating from the quantizer. The expressions for a n and t i can be combined to give the consolidated equation
2Q an = n
i=J
sin ( ncos
1
Ti )) A
(1.74)
The argument of this summation, sin ( ncos Polynomial, T n ( x ) , dened as:
( T i A ) ) , closely resembles the n-th Chebyshev
T n ( x ) = cos ( ncos
( x) )
(1.75)
which can also be expressed by the recurrence relation
T n + 1 = 2xT n ( x ) T n 1 ( x )
(1.76)
52
leading to the following polynomial forms for the rst 4 functions:
T0 = 1 T1 = x T 2 = 2x 1 T 3 = 4x 3x T 4 = 8x 8x + 1 sin ( ncos
1 4 2 3 2
(1.77)
( x ) ) can be expressed in terms of T n ( x ) by noting that dT n ( x ) 1 = T n ( x ) = sin ( ncos ( x ) ) dx n 1x

2
(1.78)
so that
S n ( x ) sin ( ncos
The rst few functions of sin ( ncos
1
1x ( x) ) = Tn ( x) n
(1.79)
( x ) ) , abbreviated S n ( x ) for simplicity, are
S0 = 0 S1 = 1 x
2 2 2 2
S 2 = 2x 1 x
2
(1.80)
S 3 = ( 4x 1 ) 1 x
3
S 4 = ( 8x 4x ) 1 x
The behavior of S n ( x ) can most easily be envisioned when kept in the form sin ( ncos ( x ) ) . 1 The argument of the sine function, cos ( T i A ) (plotted in gure 1.31 for reference), is a monotonically increasing function of its argument spanning from 0 to as the threshold index, i, sweeps from J to K. The sine of this argument (when the parameter n is equal to 1) exhibits one maximum when T i A is zero and is equal to zero itself at both endpoints ( T i A = 1 ). In
53
3/4
acos(-x) cos ( x )
/2
/4
-1
-.5
0 x
.5
Figure 1.31. The inverse cosine function.

fact, this function is the upper unit semi-circle discussed above in the calculation of P s . As the parameter n is increased, the range covered by the argument of the sine function increases from
( 0, ) to ( 0, n ) . Therefore, the number of extrema in the function sin ( ncos sin ( ncos
1
( Ti A ) )
increases to n. This function is plotted for several values of n in gure 1.32 where it can be seen that
( T i A ) ) is an even function for all n odd and an odd function for all n even. When
n is even, the odd symmetry exhibited by the sine function ensures that the summation used to calculate a n in equation 1.74 equals exactly 0. This brings out the important fact that a perfect quantizer produces no even harmonics whatsoever. The even symmetry of
sin ( ncos sin ( ncos
( T i A ) ) when n is odd enables the summation in equation 1.74 to be calculated ( T i A ) ) functions plotted in gure 1.32 is reminiscent of the passband ripple of
with half the original number of function evaluations. The quasi-periodic nature of the
1
Chebyshev lters whose characteristics are dened by the related Chebyshev polynomials.
. The absence of even harmonics in a quantizer output spectrum should not be surprising since the quantization characteristic itself is a purely odd function of its input variable and therefore has a polynomial expansion with only odd terms.
54
n = 1 n = 2
.5
sin(n*acos(-x)) sin ( ncos ( x ) )
n = 3
n = 4
-.5
n = 5
-1
-1
-.5
0 x
1
.5
Figure 1.32. The function sin ( ncos

n. sin ( ncos
1
( T i A ) ) for several values of
( Ti A ) )
Equation 1.74 can be used with equation 1.71 to calculate the harmonics comprising the spectrum of an ideal 8-bit quantizer (Fig. 1.33). The maximum harmonic distortion for lower-order harmonics is near 72 dBc, or 9N dBc. Additionally, a slightly higher power harmonic occurs of order approximately 800. This behavior can be compared to that of an ideal 10-bit quantizer (Fig. 1.34) which exhibits maximum power lower-order harmonics of approximately -90 dBc, again equal to -9N dBc. The peak harmonic, which is slightly higher in power than -9N dBc, occupies a harmonic position just above 3000. The relative power and position of the peak harmonic in quantizer output spectra generally follow the trends alluded to above for the specic 8-bit and 10-bit cases. In particular, the position of the peak harmonic is closely approximated by 2 as shown in gure 1.35 which plots the peak harmonic number versus input amplitude measured in LSBs. In the approximation 2 , N refers to the maximum number of effective bits for a given input amplitude. So, for example, an input amplitude of 16 LSBs equates to log 2 ( 2 16 ) = 5 maximum effective bits, or N = 5 while an amplitude of 25 LSBs corresponds to N = 5.64 . The maximum harmonic power generated by an ideal quantizer is approximately -9N dBc where again
N N
55
-60
-70
SDR (dB)
-80
-90
-100 0 10
10
10 Harmonic Number
10
Figure 1.33. Harmonic levels for an ideal 8-bit midriser quantizer.

N is the effective resolution assuming full loading with a sinusoidal input. Therefore, N = 7.5 implies that 2
7.5
= 181 thresholds are traversed by an input sinusoid with amplitude 90.5. This
quantizer, with 181 thresholds, will exhibit identical performance to any quantizer with higher resolution but the same input amplitude because thresholds which are not traversed by the input waveform do not enter into the SNR or distortion calculations which limit their summations to the range of activated thresholds. A plot of the peak harmonic distortion versus input amplitude as expressed by maximum effective resolution (Fig. 1.36) indicates very close conformance to the approximation -9N dBc. Also plotted in the same gure is the relative power in the third harmonic, HD3, which conforms to the -9N dBc approximation as well. The location of the peak distortion product at harmonic number 2 arises because of the quasi-periodic nature of the function sin ( ncos
1 N
( T i A ) ) as next explained. The power in
any distortion product (according to equation 1.74 which is repeated below for convenience) depends upon the sum of samples of sin ( ncos harmonic number, n.
1
( T i A ) ) which varies as a function of the
56
-85
-90
SDR (dB)
-95
-100
-105 0 10
10
10 Harmonic Number
10
10
Figure 1.34. Harmonic levels for an ideal 10-bit midriser quantizer.

K
2Q an = n
i=J
sin ( ncos
Ti )) A
(1.81)
To maximize the sum comprising a n , all of the samples, J i K , should be at or near a peak of 1 sin ( ncos ( T i A ) ) . Two examples which illustrate this principle are depicted in gure 1.37 where sin ( ncos
1
( T i A ) ) and its samples are plotted for the cases N = 4 whose peak
harmonic is number 47 and N = 5 whose peak occurs at n = 99 . Notice that in each case nearly all of the samples occur at or near a function extrema. The condition required for such sample placement, where the samples are located at the uniformly spaced locations T i A , is that the sample after the abscissa midpoint equal the sample at the abscissa midpoint. That is,
1
sin ( ncos
TM 2 + 1 1 T M 2 ) ) = sin ( ncos ( )) A A
(1.82)
57
800
Peak Harmonic Number Peak Harmonic Approximate 2N Approximation, Peak
600 Peak Harmonic Number
400
200
50
100 150 Input Amplitude (LSBs)
200
250
Figure 1.35. Peak harmonic number versus analog input amplitude.

This expression can be simplied by using the ideal values of T M 2 + 1 and T M 2 .
1
sin ( ncos
1 1 0 ( ) ) = sin ( ncos ( ) ) A A = sin ( n ) 2
(1.83)
Taking the inverse sine of both sides of equation 1.83 introduces an ambiguity characterized by the integer m which species by how many periods the arguments of the two sinusoids differ. The resultant condition for peak distortion becomes
1
ncos
1 ( ) = n + m2 2 A
(1.84)
58
0 -10 -20 -30 -40 -50 -60 -70 -80 Peak Harmonic Power 3rd Harmonic Power 9N Approximation
Peak Harmonic Power (dBc)
4 5 6 Quantizer Resolution (Bits)
Figure 1.36. Peak harmonic power for ideal midriser quantizer.

which simplies to
1 m = cos ( 2 + ) 2 A n . m = sin ( 2 ) n
Therefore,
(1.85)
n = m
2 sin
1
( 1 A)
2 = m2 A 1A
(1.86)
where the approximation used relies upon sin x = x for x small, a condition which holds for most values of A. If full loading is assumed, A can be expressed in terms of the quantizer resolution by using the relationship 2
N
= 2A + 1 which rearranges to give A = ( 2 1 ) 2 2 2 . Using
59
.5 sin(99acos(x)) sin(47acos(x))
-.5
-1 1
.5
-.5
-1
-1
-.5
0 x
1
.5
Figure 1.37.
( x ) ) evaluated at x = T i A for peak harmonics. (lower) N = 4, n = 47 . (upper) N = 5, n = 99 .
The function sin ( ncos
this expression for A in equation 1.86 gives the nal condition for maximum distortion:
n = m2
2 N = m 2 2
(1.87)
where m is any nonzero integer. Since the Fourier coefcients a n depend on the reciprocal of n as
60
1
well as the sum of the samples of the function sin ( ncos highest harmonic power resulting in
( T i A ) ) , the minimum value of n
which satises equation 1.87 will give the largest distortion power. Therefore, m = 1 yields the
n maxHD = 2
(1.88)
as predicted empirically from the plots of quantizer distortion spectra. Notice that local distortion maxima will occur at multiples of n maxHD as predicted by equation 1.87. Such maxima are easily 10 noticeable in gure 1.34 where the peak harmonic number is just over 3000 ( 2 ) and local maxima occur just above 6000 and 9000 corresponding to m from equation 1.87 taking on values of 1, 2, and 3, respectively. The magnitudes of the local maxima are approximately -6 dB and -10dB relative to the absolute maximum corresponding to 20log(1/2) and 20log(1/3) as expected. Martin and Secor [10] have shown that the relative power of the 3rd harmonic output from a fully loaded N-bit A/D, -9N dBc, can be predicted from the Fourier series expansion of the quantization error emanating from the converter in response to a sinusoidal input. The analysis relies upon an identity which expresses the Fourier coefcients in terms of Bessel functions with known approximations. Note that the 3rd harmonic is found empirically to lie within a few decibels of the peak harmonic for most cases (see gure 1.36) so that the -9N dBc approximation for HD 3 also serves as a good approximation for peak harmonic power. For a fully loaded quantizer the result is
HD 3 =
P3 P1
1 (2 )
N 3
= 2
3N
(1.89)
which when expressed in decibels simplies to
HD 3 = 10 log
P3 3N 10 log ( 2 ) = 30 N log ( 2 ) = 9 NdBc P1
(1.90)
When the quantizer is less than fully loaded, equation 1.89 can be generalized by expressing the number of quantization codes output from the converter as a function of the input amplitude, A , rather than as a function of the quantizer resolution, N . That is, 2 in equation 1.89 is replaced by
N
61
2A Q giving 1 dBc HD 3 10 log ( 2A Q ) 3 = [ 30 log ( A Q ) + 30 log ( 2 ) ] dBc = [ 30 log ( A Q ) + 9 ] dBc
(1.91)
Alternatively, the input amplitude can be expressed with the loading factor, LF (equation 1.9), as
2 LF A = Q 2
This expression can be substituted into the rst line of equation 1.91 giving
(1.92)
1 dBc HD 3 10 log ( 2A Q ) 3 = 10 log ( 22 LF )

N 3
dBc
(1.93)
= [ 9N + 30 log ( 2 ) + 30 log LF ] dBc = [ 9N + 4.5 + 30 log LF ] dBc

Notice that if the loading factor is expressed in decibels (i.e. LF indB = 20 log LF ) then 1.93 further simplies to
HD 3 [ 9N + 4.5 + 1.5 LF
indB
] dBc
(1.94)
Equation 1.94 gives the very simple and important result that the 3rd harmonic (empirically seen to be near the highest-power harmonic) can be approximated by -9N dBc at full loading
( LF = 3dB ). Also, the distortion degrades by 1.5 dB for each 1 dB decrease in the loading factor. This relationship leads to the counter-intuitive but correct conclusion that distortion increases for decreasing input signal power. The surprising correlation between distortion and signal power can be justied qualitatively by noting that the quantization error remains bounded by one quantization step, Q, regardless of input amplitude. Therefore, the xed distortion power is a larger fraction of smaller input signals than of
62
larger input signals; and harmonic distortion degrades for lower level inputs correspondingly.
The above results for quantizer distortion spectra assume ideal quantization characteristics described by uniform threshold placement. Real quantizers will exhibit imperfections in threshold locations which are generally characterized statistically or by a polynomial expansion which includes higher-order terms than the linear expansion describing the ideal thresholds. The effect of such non-idealities on quantizer output spectra can be ascertained by studying their corresponding impact on the summations which determine the Fourier coefcients, a n , as detailed in equation 1.74 and depicted in gure 1.32. First, since random perturbations of the ideal thresholds destroy the symmetry of the samples of sin ( ncos
1
( T i A ) ) , the even-order coefcients no longer sum to
exactly zero. Therefore, even harmonics are generated by non-ideal quantizers. Second, the relative signicance of higher-order harmonics is generally reduced because these terms become large only when a specic relationship holds between threshold placement and peaks of the function
1
sin ( ncos
( T i A ) ) . Such alignment is highly unlikely in the presence of random threshold
perturbations. These two assertions are borne out by the example below (Fig. 1.38) which depicts the output spectrum for an 8-bit quantizer having Gaussian distributed threshold errors with standard deviation equal to one quarter of an LSB. Clearly the even-order harmonics are signicant and the higher-order terms no longer limit the spurious-free dynamic range (SFDR). The dominant harmonic, however, remains near the predicted value of -9N dBc. As described in section 10.2, the effect of deterministic threshold perturbations on the spectra of quantized signals remains an important area where better understanding is needed. Certain A/D converter architectures give rise to predictable threshold errors which ultimately limit linearity; however, determining distortion spectra based upon these errors is still impractical. For example, bipolar ash converters typically exhibit threshold errors caused by bias currents owing through a resistive reference-generation ladder. This effect, sometimes called reference bowing, is predictable, but its effect on the converter output spectrum is difcult to ascertain. Also, multistage A/D converters with imperfect matching between stages exhibit threshold placement with periodic deviations from the ideal. Again, the threshold locations are predictable and even admit a simple polynomial expansion; however, the concomitant effect on the converters spectrum
. As in the case of an ideal quantizer, this result should not be surprising since threshold errors destroy the odd symmetry of the quantization characteristic upon which a polynomial expansion composed of purely odd harmonics is based.
63
-60
-70
SDR (dB)
-80
-90
-100 0 10
10
10 Harmonic Number
10
Figure 1.38. Harmonic levels for an 8-bit midriser quantizer with 1/4 LSB rms
threshold errors. is difcult to determine in analytic form. Development of techniques for predicting such effects would prove invaluable for high-performance data converter design.
1.3.3 Fundamental Limits to Performance

Many factors impact overall system operation and can limit performance below the ideal predicted in the previous section. Several such factors which present limits on A/D converter performance will now be discussed. In a 50 system, thermal noise induced by the source resistance limits A/D converter resolution to a sub-ideal value which can be calculated if the system bandwidth, f , and signal amplitude, V fsr 2 , are known [11]. The noise power available from the source resistance is
P n = kTf
(1.95)
64
where k is Boltzmanns constant, T is the temperature in degrees Kelvin, and f as previously dened is the bandwidth of the system. The maximum signal power is
2
1 V fsr 1 Ps = ( ) 2 2 R
(1.96)
where R is the source resistance and full-scale quantizer loading is assumed. The maximum achievable SNR of an A/D converter operating under such circumstances is:
2
SNR Thermal
1 V fsr 1 2 ( ) V fsr 2 2 R . = = 8kTRf kTf
(1.97)
By using this expression for SNR in equation 1.20 the maximum attainable quantizer resolution as limited by thermal noise is seen to be
12
N eff
V fsr 2 = log 2 3 8kTRf
(1.98)
For a given quantizer input range, V fsr , achievable resolution, N eff , is inversely proportional to bandwidth and absolute temperature as shown in gure 1.39. As can be seen from this graph, 10 bit resolution is within the thermal limit for bandwidths well above the 50MHz design goal. Aperture jitter, which is the noiseinduced uncertainty in the otherwise periodic sampling interval, also places a fundamental limit on achievable resolution [11], [12], [13], [14] for the following reason. If a signal is changing in time with a maximum slew rate equal to S, and its value is to be determined with accuracy dV, then the sampling instant, T must be dened with accuracy dT (Fig. 1.40 ) such that
dT
dV S
(1.99)
where the timing uncertainty, dT, is referred to as the aperture jitter, jitter .If the A/D converter requires N bit resolution, then to ensure amplitude error less than 1/2 LSB, dV must be limited
65
20
Vfsr=1.0V
T = -55C T = 25C T = 125C
18 Resolution (bits)
Vfsr=0.5V
16
Vfsr=.25V
14
Rsource=50
12
10 Bandwidth (MHz)
100
1000
Figure 1.39. Thermal limit to achievable resolution.

such that
dV
V fs 1 2V fs = N. 2 2N 2
(1.100)
The maximum slope of a sinusoidal input signal of amplitude V fs and frequency f in is S = 2f in V fs resulting in
( N + 1) V fs 2 2 dV = = . jitter = dT S 2f in V fs f in N
(1.101)
This constraint shows the maximum aperture jitter consistent with Nbit resolution and is plotted
66
V fs
V ( t ) = V fs sin ( 2f in t ) Slope = dV ( t ) dt V fsr = 2V fs ddV V T
Q = 2V fs 2 dt dT V fs
Figure 1.40. Aperture uncertainty causes amplitude errors.

versus bandwidth, f in , for various values of resolution, N, in gure 1.41.
1000
N=2 4
100
6
Aperture Jitter (ps)
8 10
10
12 14 N=16
0.1 0.1
10 100 Analog Input Bandwidth (MHz)
1000
Figure 1.41.
Maximum aperture jitter consistent with 1/2 LSB errors for various values of resolution.

Alternatively, equation 1.101 may be solved for N in terms of jitter giving
67
N eff log 2 (
1 ) 1. jitter f in
(1.102)
This relationship, plotted in gure 1.42 for various values of jitter , shows that to achieve 10
20 tap=1ps tap=10ps tap=100ps tap=1ns 15
Maximum Attainable Effective Bits
jitter = 1ps
10
10ps
100ps
jitter = 1ns
10 100 Analog Input Bandwidth
1000
Figure 1.42. Maximum attainable resolution limited by aperture jitter.
effective bits of resolution, jitter must be kept well below 10ps; and to maintain adequate margin for this parameter a value close to 1ps is desirable. This constraint on acceptable jitter mandates use of a track-and-hold circuit preceding the 10-bit quantizer and further implies that on-chip clock buffer circuitry must be designed specically to prevent degradation of the phase noise from that presented to the A/D converter from outside clock and signal sources. Unavoidable threshold level errors caused by device mismatches also reduce maximum achievable SNR. The effect of such imperfections on the quantization error waveform is shown in
68
gure 1.22 which is repeated here for convenience (Fig. 1.43). As seen in this gure, threshold
U ( x) Q2 FSR/2 x -FSR/2 Q 2 (a) U ( x) Q2 FSR/2 x -FSR/2 Q 2 (b) Figure 1.43. Quantization error waveforms. (a) Ideal quantizer. (b) Quantizer with threshold level errors.
errors increase the maximum amplitude and the variance of the quantization error waveform thereby increasing the power in the noise component of the SNR equation. To determine the quantization noise power in the presence of threshold errors, the quantizer error is now studied in more detail. The quantization error, U ( x ) , represents the difference between the quantizer output,
Q ( x ) , and the quantizer input, x, as dened in equation 1.11 and repeated here: U ( x) = Q ( x) x
(1.103)
The waveform Q ( x ) , and hence U ( x ) , is determined solely by the M 1 thresholds T i ,
i = 1, , M 1 which differ from the ideal thresholds, T i* , according to k = T k T k*

(1.104)
69
where is the quantizer offset. The quantization error, Q ( x ) ,equals zero when the input is equal to the output. Since the quantizer output takes on the M discrete values Q j* , j = 0, , M 1 , the quantization error vanishes for the M values of input equal to Q j*. These relationships are depicted succinctly for one quantizer step in gure 1.44. The noise power emanating from the
U ( x) Q 2 + j Q2 Q j* x
Qj 1
* Tj
j x T j* Q j*
Q 2 + j Q 2
Q j 1* x
Segment of quantization error waveform with non-zero threshold errors, j .
Figure 1.44.
quantizer can be calculated by dividing the input range into a discrete set of subranges and determining the variance of each corresponding output waveform. If the subranges comprise the set
A j, j = 1, , L then, 2 = E { U ( x) } n =
2
j=1
E { U ( x)
x Aj } Px ( x x Aj )
(1.105)
70
If the subranges, A j , are taken to be the regions between adjacent nulls in the quantization error, U ( x ) , and further, the input is assumed uniformly distributed on each such interval, then the noise due to the j-th interval, nj , can be calculated according to the following equation derived from gure 1.44.
2
2 = E { U ( x ) x Aj } nj
2 = E { U ( x ) Q j 1* < x Q j* } Q j* 2 ( Q j 1* x ) dx +
1 Q
Tj
(1.106)
Q j 1*
Tj
( Q j x ) dx
which can be simplied by using the substitution y = x Q j 1* in both integrals and recalling that Q j* Q j 1* = Q to obtain
Q 2 + j
1 2 = nj Q 1 = Q 1 = Q 1 = Q
2
0 Q 2
( y ) dy +
Q
Q 2 + j
( Q y ) dy
y dy +
0
( Q 2Qy ) dy
(1.107)
Q 2 + j
1 3Q 2 2 Q y 0 + ( Q y Qy ) Q 2 + 3 j 1 3 3 2 2 Q Q 2 Q j + Q ( Q 4 + Q j + 2 ) j 3
Q = + 2 j 12
The total quantizer output noise power, n , is calculated by using this result for nj in equation 1.105.
L
2 n
j=1
nj Px ( x x Aj )
2
(1.108)

which can be further simplied if a uniformly distributed input is again assumed.
L
71
2 n
1 = L =
Q + 2 e 12
j=1 2
nj
2
(1.109)
where e is the rms threshold error as dened in equation 1.6. The rst term on the right side of equation 1.109 is the quantization noise of an ideal quantizer as derived in equation 1.12. The second term is the added noise power brought on by imperfect placement of thresholds. This new expression for output noise power can be used in place of the simpler expression Q 12 in equations such as 1.14 and 1.17 to predict SNR for non-ideal quantizers. The preceding derivation assumes that the input signal exhibits a uniform probability density function. For many inputs this assumption is unjustied and more exhaustive analysis must be performed to obtain accurate predictions of quantizer performance under non-ideal conditions. In such cases, the techniques of section 1.3.2 can be applied with the actual threshold levels, T i , used in place of the ideal values, T i* , to accurately predict SNR performance. Comparator regeneration time also places a fundamental limit on achievable resolution [11], [15], [16] for the following reason. If a comparator is given a nite time to regeneratively produce a logic-level output, then for some range of differential input values near zero, the comparator output will not be large enough to be unambiguously interpreted by succeeding encoding logic. This logic can therefore produce erroneous output codes which increase the noise power in the quantizer output waveform thereby diminishing SNR. Such coding errors have been called conversion errors, rabbit errors, sparkle codes, and metastability errors. The nature of the digital output produced under conditions of metastability errors depends greatly on the output coding format used. With most forms of binary coding, metastability errors manifest themselves as output code errors which can be modelled as a random N-bit word. The power contributed to the quantizer output noise in this case is:
2 2
( 2 Q) E { n ConversionError } = 12
2
(1.110)
Note that this result follows directly from gure 1.23 and equation 1.12 which predict the quantizer output noise to be Q 12 for outputs uniformly distributed on ( Q 2, Q 2 ) . In the present
2
72
case, the output (under the conditions of a metastability error and binary coding) is presumed to be uniformly distributed on ( 2 Q 2, 2 Q 2 ) . Equation 1.110 follows directly. The output noise due to metastability errors becomes
N N
2 = E { n MetastabilityError } P ME n
2 ( 2 Q) Q 2N P ME = = 2 P 12 12 ME N 2
(1.111)
where P ME is the probability of a metastability error. If Gray coding is used rather than binary, metastability errors manifest themselves as a single bit error in an otherwise accurate output codeword. This benecial effect arises because in Gray coded A/D converters each comparator inuences one and only one output bit. Therefore, a metastable comparator causes the corresponding bit to become indeterminate, but all other bits behave correctly (ignoring the unlikely event of two metastable comparators during one conversion). In fact, this characteristic is the chief rationale for implementing Gray encoding in A/D converters. When a metastability error gives rise to an erroneous output bit, the amount of noise added to the output corresponds to an amplitude error equal to one quantizer step, Q; however, with probability 1/2 the bit in question will assume the correct value. Therefore, the expected meansquare noise given a metastability error is:
E { n MetastabilityError } =
1 2 2 (Q + 0 ) 2
(1.112)
so the noise power due to metastability errors in Gray coded converters becomes
2 = n
Q Q P ME = 6P ME 2 12
2N
(1.113)
which is less than the noise power in a binary converter (equation 1.111) by the factor 2
6 . This
factor represents an extreme noise reduction for even modest resolution A/D converters. The maximum SNR with metastability errors can be calculated by using the preceding expressions for noise power with equation 1.17 which gives SNR as a function of input amplitude and quantizer step-size.

2
73
SNR Q =
A 2 Q 12
N 2
( 2 2) Q 2 Q 12
2
2 Q 8 Q 12
2
2N
(1.114)
where full loading ( A = ( 2 2 ) Q ) has been assumed for maximum SNR. By replacing the denominator of equation 1.114 which is the noise due to quantization with the noise expressions developed for metastability errors (equations 1.111 and 1.113) the maximum achievable SNR given metastability errors results. For binary encoding:
SNR ME =
2 Q 8 ( Q 12 ) 2 P ME
2 2N
2N
3 2P ME
(1.115)
and for Gray encoding:
SNR ME =
2 Q 8 ( Q 12 ) 6P ME
2
2N
2 = 4P ME
2N
(1.116)
where the subscript ME modifying SNR distinguishes the noise as that caused by metastability errors. Equation 1.20 can be used to convert the above SNR expressions into effective bits. For binary encoding:
N eff
ME
1 1 log ( ) 2 2 P ME
1 = log ( P ME ) 2 2
and for Gray encoding
(1.117)
N eff
ME
1 2 log 2 6P ME 2
N
2N
1 2 = log 2 log ( P ME ) 6 2 2 1 = N log ( P ME ) log 2 ( 6 ) 2 2
(1.118)
The probability of a metastability error depends upon the statistics of the input signal, but if a
74
uniformly distributed input is assumed, P ME is given by [woodward]
P ME =
2V L AQ
(1.119)
where V L is the minimum amplitude voltage which will unambiguously be interpreted as an appropriate logic level (so 2V L represents the range of ambiguous voltages), A is effective gain of a comparator at the end of the latch mode, and Q is the quantizer step size. P ME is seen to be the ratio of the ambiguous voltage range (referred to the comparator input) divided by total input range seen by the same comparator. The effective comparator gain, A, which is dependent upon the dynamic comparator response and the time allowed to regeneratively establish an output state can be described as
A = A0 e
(1.120)
where A 0 is the DC gain of the comparator and is the time-constant (assumed rst order) which governs the comparator response during latch mode. The probability of metastability then becomes
P ME =
2V L t e A0 Q
(1.121)
where t, the amount of time the comparator is allowed to regenerate, is governed by the A/D converter sample rate, f s . The term 2V L A 0 Q is on the order of 10 for reasonable values of V L ,
A 0 , and Q. Additionally, is ideally equal to the reciprocal of t , the radian unity gain cut-off
frequency of the transistors comprising the latch; however in practical circuits is usually several times this value:
5 2f t
(1.122)
Equation 1.121 can be used with equation 1.117 to predict maximum effective resolution as limited

by metastability errors with binary encoding.
75
N eff
ME
1 = log 2 ( P ME ) 2 1 2V L t e = log 2 2 A0 Q 1 t 2V L = log 2 + log 2 e 2 A 0 Q 2
(1.123)
If the time allowed for regeneration, t, is equal to half the sample period, T s 2 , and the input bandwidth of the A/D converter is limited by Nyquists condition ( f in f s 2 = 1 ( 2T s ) ) then t in equation 1.123 can be replaced by 1 ( 4f in ) resulting in
N eff =
log 2 e 1 2V L log 2 8f in 2 A0 Q
1 1 2V L = log 2 8ln 2f in 2 A0 Q
(1.124)
where ln ( x ) is the natural logarithm function. N eff as calculated by equation 1.124 is displayed graphically in gure 1.45 which indicates that for an effective resolution of 10-bits and an input bandwidth of 50MHz, the comparator time-constant, , must be less than 300 ps. The achievable resolution for Gray encoding can be calculated in a similar fashion to equation 1.124 giving
N 2 + log 2 e 1 log 2V L = log 2 2 A Q 0 6 8f in 2
N eff
1 1 2V L = N+ log 2 log 2 ( 6 ) 8ln 2f in 2 A0 Q
(1.125)
where N is the number of bits in the Gray-encoded output word. Notice that the achievable resolution as limited by metastability errors in this case is greater than that achievable in the binary case so long as N > log 2 ( 6 ) = 1.29 ; that is, for all resolutions of practical interest. For a Gray encoded A/D converter to achieve 10 bits of resolution with a 50MHz input bandwidth can be slightly longer than 1ns, a factor of three higher than the binary encoded conguration. Alternatively, with the same comparator time constant the Gray converter exhibits three times the
76
20
= 100ps
Achievable Resolution (Bits) 15
2V L = 20 Ao Q
200ps
10
500ps
5
= 1000ps
0
10
100 Input Bandwidth (MHz)
1000
Figure 1.45. Achievable resolution as limited by metastability errors.

bandwidth as the binary converter. In some applications, notably video signal processing, SNR is not the most important measure of performance degradation due to metastability errors. Rather, peak error is the metric used for such characterization because large code errors when reconstructed via D/A conversion appear on a video monitor as noticeable pixel amplitude discontinuities. These momentary discontinuities, a white pixel on a dark background or vice-versa, seem to the human visual system like sparkleshence the name sparkle codes. Gray encoding helps greatly in this regard by limiting the maximum metastability-induced error to one LSB.
77
References
[1] [2] [3] [4] [5] [6] A. Macovski, Medical Imaging Systems. PrenticeHall, 1983. G. S. Kino, Acoustic Waves: Devices, Imaging, and Analog Signal Processing. Prentice Hall, 1987. D. H. Sheingold, ed., AnalogDigital Conversion Handbook. PrenticeHall, third ed., 1986. The Engineering Staff of Analog Devices. Y. Ninomiya, HDTV broadcasting systems, IEEE Communications Magazine, vol. 29, pp. 1522, Aug. 1991. K. Rush and P. Byrne, A 4GHz 8b data acquisition system, in International Solid State Circuits Conference, pp. 176177, IEEE, Feb. 1991. S. Swierkowski, D. Mateda, G. Cooper, and C. McConaghy, A sub-200 picosecond GaAs sample-and-hold circuit for a Multi-Gigasample/Second integrated circuit, in International Electron Device Meeting, pp. 272275, IEEE, 1985. W. R. Bennett, Spectrum of quantized signals, Bell System Technical Journal, vol. 27, pp. 446472, July 1948. A. Gersho, Principles of quantization, IEEE Transactions on Circuits and Systems, vol. CAS-25, pp. 427436, July 1978. S. Max, Quantizing for minimum distortion, IRE Transactions on Information Theory, vol. IT-6, pp. 712, Jan. 1960. D. R. Martin and D. J. Secor, High speed analogtodigital converters in communication systems: Terminology, architecture, theory, and performance, tech. rep., TRW Electronic Systems Group, Redondo Beach, CA, Nov. 1981. L. E. Larson, High-speed analog-to-digital conversion with GaAs technology: Prospects, trends and obstacles, in International Symposium on Circuits and Systems, pp. 2871 2878, IEEE, 1988. R. J. van de Plassche and P. Baltus, An 8-bit 100-MHz full Nyquist analog-to-digital converter, IEEE Journal of Solid State Circuits, vol. SC-23, pp. 13341344, Dec. 1988. T. Wakimoto, Y. Akazawa, and S. Konaka, Si bipolar 2-GHz 6 bit flash A/D conversion LSI, IEEE Journal of Solid State Circuits, vol. SC-23, pp. 13451350, Dec. 1988. M. Shinagawa, Y. Akazawa, and T. Wakimoto, Jitter analysis of high-speed sampling systems, IEEE Journal of Solid State Circuits, vol. SC-25, pp. 220224, Feb. 1990. C. E. Woodward, K. H. Konkle, and M. L. Naiman, A monolithic voltage-comparator array for A/D converters, IEEE Journal of Solid State Circuits, vol. SC-10, pp. 392399, Dec. 1975. B. Zojer, R. Petschacher, and W. A. Luschnig, A 6-Bit/200-MHz full Nyquist A/D converter, IEEE Journal of Solid State Circuits, vol. SC-20, pp. 780786, June 1985. M. K. Mayes and S. W. Chin, A multistep A/D converter family with efficient architecture, IEEE Journal of Solid State Circuits, vol. SC-24, pp. 14921497, Dec. 1989.
[7] [8] [9] [10]
[11]
[12] [13] [14] [15]
[16] [17]
78 [18] [19] [20]
M. P. Kolluri, A 12-bit 500-ns subranging ADC, IEEE Journal of Solid State Circuits, vol. SC-24, pp. 14981506, Dec. 1989. Y. Sugimoto and S. Mizoguchi, An experimental BiCMOS video 10-bit ADC, IEEE Journal of Solid State Circuits, vol. SC-24, pp. 997999, Aug. 1989. T. Shimizu, M. Hotta, K. Maio, and S. Ueda, A 10-bit 20-MHz two-step parallel A/D converter with internal S/H, IEEE Journal of Solid State Circuits, vol. SC-24, pp. 1320, Feb. 1989. S. H. Lewis and P. R. Gray, A pipelined 5-Msample/s 9-bit analog-to-digital converter, IEEE Journal of Solid State Circuits, vol. SC-22, pp. 954961, Dec. 1987. S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, A 10b 20Msample/s analog-to-digital converter, IEEE Journal of Solid State Circuits, vol. SC-27, pp. 351358, Mar. 1992. R. Petschacher, B. Zojer, B. Astegher, H. Jessner, and A. Lechner, A 10-b 75-MSPS subranging A/D converter with integrated sample and hold, IEEE Journal of Solid State Circuits, vol. SC-25, pp. 13391346, Dec. 1990. R. E. J. van de Grift, I. W. J. M. Rutten, and M. van der Veen, An 8 bit video ADC incorporating folding and interpolation techniques, IEEE Journal of Solid State Circuits, vol. SC-22, pp. 944953, Dec. 1987. M. Hotta, T. Shimizu, K. Maio, K. Nakazato, and S. Ueda, A 12-mW 6-b video-frequency A/D converter, IEEE Journal of Solid State Circuits, vol. SC-22, pp. 939943, Dec. 1987. B.-S. Song, M. F. Tompsett, and K. R. Lakshmikumar, A 12-bit 1 Msample/s capacitor error-averaged pipelined A/D converter, IEEE Journal of Solid State Circuits, vol. SC-23, pp. 13241333, Dec. 1988. Y. Akazawa, A. Iwata, T. Wakimoto, T. Kamato, H. Nakamura, and H. Ikawa, A 400MSPS 8b flash AD conversion LSI, in International Solid State Circuits Conference, pp. 9899, IEEE, Feb. 1987. C. W. Mangelsdorf, A 400-MHz input flash converter with error correction, IEEE Journal of Solid State Circuits, vol. SC-25, pp. 184191, Feb. 1990.
[21] [22]
[23]
[24]
[25] [26]
[27]
[28]
Chapter 2
Pipelined Architecture
2.1 Architectural Comparison

Several architectures were investigated to ascertain their suitability for implementing a 10bit, 100 Msps, low-power data converter. The following sub-sections present the results of this study, highlighting those features which pertain to selection of an appropriate architecture for this project. This discussion is not intended as an exhaustive description of A/D converter techniques. For such a treatment, the reader is referred to the text by Sheingold, [3], and the review paper by Gordon, [2].
2.1.1 Flash Converters

Traditionally, highspeed A/D converters have relied upon the parallel or ash architecture (Fig. 2.1) wherein the analog input signal is simultaneously compared to every threshold voltage of the ADC by a bank of comparator circuits [15], [4]. The threshold levels are usually generated by resistively dividing one or more references into a series of equally-spaced voltages which are applied to one input of each comparator. The collection of digital outputs from this comparator bank is called a thermometer code because every comparator output below some point along the array is a logic 1 (corresponding to the mercury-lled portion of a thermometer) while all comparator outputs above this position are logic 0 (corresponding to the empty portion of a thermometer).
80
Chapter 2 Pipelined Architecture
+Vref
Vin
Encoding Logic
N-bit Digital Output
-Vref
2 -1 Thermometer Comparators Code
Figure 2.1. Flash or parallel A/D converter topology.

The thermometer code is easily encoded into a binary output word with an array of simple logic gates and a read-only-memory (ROM). Although conceptually simple, and capable of very highspeed operation, the ash architecture suffers from several signicant deciencies described next. In parallel ADCs, one comparator is required for each threshold of the converter. Thus, the total number of comparators required is 2 1 , where N is the resolution of the ADC. Because this quantity grows exponentially with resolution, the required number of comparators is quite large, even for medium resolution components such as that considered here. All of the drawbacks of ash A/D converters stem from this exponential dependence of comparator count on resolution. Thus, increased ADC resolution leads to dramatic growth in the required number of comparators which in turn causes the following detrimental effects:
N

Large die size which implies high cost Large device count leading to low yield
81
Complicated clock and signal distribution with signicant capacitive loading (both device and parasitic)
Large input capacitance requiring high power dissipation in the T/H driving the A/D converter and degrading dynamic linearity
High power supply noise due to large digital switching current Signicant errors in threshold voltages caused by comparator input bias current owing through the resistive reference ladder
Although the ash topology is very effective for lower resolution converters [5], [25], [7], [16], [9], [10], [13], [12], [13], and has been used widely to implement 8-bit ADCs [27], [15], [16], [17], [18], [19], [4], [20], [21], [22], [23], [24], the above combination of factors make implementation of ash converters above 8-bits very difcult, especially if low power dissipation is required. Therefore, the fully parallel architecture was rejected for this project.
2.1.2 Feedback or Multi-pass Converters

The feedback, or multi-pass, A/D converter architecture reduces complexity compared to the ash arrangement by utilizing comparators multiple times during each quantization [25], [26], [17], [28], [29], [30]. In this architecture (Fig. 2.2), the full N-bit digitization process is divided into a series of lower resolution, m-bit quantizations. Each of these steps begins by amplifying the incoming signal appropriately, followed by a coarse m-bit quantization. The digital result from this operation is applied to a special accumulator called a Successive Approximation Register (SAR), the output of which drives an N-bit D/A converter. The analog output from the DAC subtracts from the input signal to form a residue signal which is ready for the next pass through the feedback loop. The N-bit resolution obtainable with this arrangement is governed by N = mp where m is the resolution of the coarse quantizer used, and p is the number of passes around the loop required to produce each N-bit output code. The gain of the amplier preceding the m-bit quantizer must be increased at each successive pass around the feedback loop to ensure that the coarse quantizer is driven with the proper amplitude. The gain required to meet this condition is
82
Input Signal Reconstructed Replica
Residue Signal A V =2
m
m(p-1)
m-bit Quantizer
Switchable Gain Stage N N-bit DAC Successive Approximation Register (SAR)
Figure 2.2. Feedback or multi-pass A/D converter topology. AV = 2

m ( p 1)
(2.1)
where m is the resolution of the coarse quantizer and p is the number of the pass through the loop. For example, on the 3rd pass through a loop with a 4-bit quantizer, the amplier gain should be
AV = 2
4 ( 3 1)
= 256 . Similarly, the digital words emanating from the coarse quantizer are
multiplied by the same factor inside the SAR (this weighting applied to incoming words distinguishes the SAR from a simple accumulator). When the coarse quantizer resolution, m , is unity, the quantizer itself reduces to a comparator and the amplier can therefore, be eliminated. This simplied feedback converter (Fig. 2.3) is called a successive approximation A/D converter and represents the lower bound on feedback ADC complexity for a given resolution [31]. Conversely, when the coarse quantizer resolution, m , equals the full ADC resolution, N , the SAR and reconstruction DAC become unnecessary, and the feedback architecture reduces to a ash implementation. Therefore, the feedback A/D converter architecture is a canonical structure, equivalent to a ash converter when
m = N and p = 1 ; and equivalent to a successive approximation converter when m = 1 and p = N . Clearly, intermediate values between these extremes represent different trade-offs between
complexity and speed of operation.
83
Vin
N-bit DAC N-bit Digital Output
Successive Approximation Register (SAR)
Figure 2.3. Successive approximation A/D converter topology.

The feedback A/D converter architecture can offer signicant hardware savings compared to a ash implementation because the coarse quantizer resolution, m , can be much smaller than the converter resolution, N . However, the feedback implementation suffers from several drawbacks reducing its suitability for the present application including the following: Requires p = N m passes to generate full N-bit output word, thus limiting maximum throughput rate Requires N-bit accurate DAC Requires switchable gain amplier which can be very difcult to realize in practice
Largely because of the limitation on maximum throughput rate, the feedback architecture was rejected for this project.
2.1.3 Feedforward Converters

[32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [20] [43] [44] [45] [46] [47] [18] [23] [19] [51] [52] [53] [54] [55] [22] By employing a cascade of coarse quantizer stages, the feedforward ADC topology (Fig. 2.4) mitigates the throughput limitations which constrain feedback converters. Each stage
84
Vin Stage 1 Stage i Stage p
+ _ m i -bit ADC m i -bit DAC
AV =2
mi
m i bits of N-bit digital output
Figure 2.4. Feedforward A/D converter topology.

comprising the feedforward A/D performs the same operations found in the feedback architecture, namely: coarse quantization, conversion back to analog format via D/A conversion, subtraction from the input signal to form a residue, and amplication. Rather than applying these operations p times in succession as in the feedback topology, p stages are cascaded to produce the same effect. The digital data from each of the p quantization stages must be suitably weighted before the words are summed to form the N-bit digital output. (This mechanism is akin to the weighting applied by the SAR in the feedback arrangement.) Several advantages accrue from this cascade arrangement. The architecture is inherently faster than the feedback topology, no switchable gain amplier is required, and digital error correction is possible to make accuracy virtually independent of threshold errors within the constituent coarse quantizers. However, two chief disadvantages compromise the suitability of this scheme for high-speed operation. First, since the feedforward converter utilizes p stages similar in complexity to the entire feedback ADC, its complexity is also approximately p times the complexity of the feedback case. Second, since each signal must ripple through a cascade of p substages, the net throughput is only marginally greater than in the feedback architecture. The pipelined

A/D topology, described next, circumvents this settling problem.
85
2.1.4 Pipelined Feedforward Converters

The pipelined feedforward A/D converter architecture (Fig. 2.5) alleviates the throughput
Vin Stage 1 Stage i Stage p
T/H m i -bit ADC m i -bit DAC
+ _ AV =2
mi
m i bits of N-bit digital output

Figure 2.5. Pipelined A/D converter topology.
limitations associated with the un-pipelined feedforward case by placing a T/H at the input of each of the p stages comprising the converter. In this way, while stage 1 is processing an input sample, stage 2 processes the preceding sample, stage 3 processes the sample before that, and so on; such that all stages process one sample per clock cycle. Although this operation produces a delay or latency of p sub-conversions before producing a valid output code, the throughput of the system is equal to that of each processing cell and can be signicantly higher than the corresponding throughput of any of the converters discussed previously. The pipelined feedforward architecture combines the advantages of high throughput demonstrated by ash converters along with low complexity, power dissipation and input capacitance characteristic of feedforward converters. The sole disadvantage associated with the pipelined approach is the requirement for p T/H circuits which can be very difcult to implement monolithically. Since analog switches (fundamental to T/H
86
operation) are difcult to implement using bipolar components (as discussed in chapter 3) most pipelined A/D converters have utilized CMOS semiconductor processes [57], [58], [21], [60], [61], [26], [63], [64], [65]. However, the benets of the pipelined architecture, high-throughput combined with low complexity, provide compelling motivation to utilize this topology. If monolithic T/H circuits with suitable performance can be developed, the pipelined A/D topology provides the technique for extending high-throughput, high-resolution conversion beyond those limits currently attainable.
2.1.5 Folding Converters

A folding A/D converter (Fig. 2.6) operates in a similar manner to a feedforward ADC by
Vout
Analog Folding Block
Fine Quantizer
(N-log 2 F)-bit Flash Vin
N
Vin cycle 1 cycle 2 cycle 3 cycle F-1 cycle F
ADC N-bit Digital Output
(2 / F Comparators) Encoding Residue Signal (log 2F)-bit ADC Logic
Coarse Quantizer
Figure 2.6. Folding A/D converter topology.
coarsely quantizing the incoming signal and generating a residue signal for further quantization by a lower resolution succeeding stage. However, in a folding converter, the residue signal is formed by a special analog circuit (the Analog Folding Block highlighted in gure 2.6) which operates simultaneously with the coarse quantizer [66], [45], [67], [68], [69], [24], [71], [72], [73], [12], [75], [52]. This arrangement obviates the need for a T/H between the coarse and ne quantizer by forming the residue signal without going through an A/D-D/A combination with its concomitant clock delay. The folding converter depicted in gure 2.6 corresponds to a 2-stage feedforward implementation with a log 2 F -bit coarse quantizer and an ( N log 2 F ) -bit ne quantizer, where
87
F is the number of periods or folds in the transfer function of the analog folding block. This analog
cell, details of which are described in chapter 6, performs the function of the DAC and the subtraction element from the feedforward architecture described previously, but does so in an unclocked manner enabling simultaneous operation of the coarse and ne quantizers. Since the folding A/D architecture offers low complexity along with potentially high-speed operation, this topology remains as a viable candidate for the 10-bit, 100 Msps converter designed here.
2.1.6 Algorithmic (Cyclic) Converters

[32] [38] [77] [78] [79] [80] [76] [61] [26] [81] [53] [82] A canonical ADC structure similar in form to the successive approximation topology is the algorithmic A/D converter (Fig. 2.7) which is sometimes referred to as a cyclic converter [76], [38].
Comparator Vin S/H + Vref/2 Amplifier X2 + Vref/2 Serial Output Bit-stream
Figure 2.7. Algorithmic A/D converter topology.
In this arrangement, conversion begins by comparing the input signal to a mid-scale value. If the input exceeds this mid-scale reference, the reference is subtracted from the input, and the result is amplied by 2 in preparation for further processing. This procedure is performed once for each bit of resolution required in the A/D conversion with the comparator output on the p-th pass representing the p-th MSB of the resulting codeword. An input multiplexor and T/H are necessary to coordinate signal ow and timing within the converter. Although extremely simple and potentially very accurate, the cyclic topology is not suitable for high-speed operation because of the
88
multiple comparisons necessary during each conversion. As in the transformation from the feedback to the feedforward architecture, several algorithmic structures can be placed in cascade to form a converter with higher complexity but accompanied by an attendant increase in maximum throughput rate. Such a topology has been termed a bit-serial A/D converter (Fig. 2.8) but is actually a special case of the pipelined
Vin Stage 1 Stage m Stage p
S/H
+ -
X2
Vref/2
1-Bit Output
Vref/2
Figure 2.8. Bit serial A/D converter topology.
feedforward architecture constructed from 1-bit stages. This conversion technique is very attractive because it is simple and can be easily extended to higher resolutions by adding more identical stages. However, since each stage requires a T/H circuit, the bit-serial approach has been largely limited to CMOS implementations [58], [21].
2.1.7 Architecture Selection

Table 2.1 includes a summary comparison among the architectures described above. Based on the relative advantages of these competing approaches, the topology for a 10-bit, 100 Msps lowpower A/D was selected. A ash architecture was rejected because its power dissipation for a 10bit implementation would exceed the 750 mW goal unless extremely low bias levels are used. Such
89
Quantizer Architecture Flash or Parallel
Advantages
Very fast Basically linear & monotonic No D/A required
Disadvantages
Very high transistor count Very high power dissipation Resolution limited by input range and transistor mismatch High input capacitance Feedback reduces maximum sample rate Subtraction element required Switchable gain amplier required D/A required Moderate sample rate
Feedback or Multi-pass
Low transistor count Single input T/H required Error correction possible
Feedforward
Moderate transistor count Error correction possible Low input capacitance Very high speed
Pipelined Error correction possible Feedforward

Low input capacitance High speed Low transistor count Folding circuit replaces coarse quantizer and D/A Low input capacitance
Multiple T/H circuits required
Folding
Resolution limited Folding circuit cannot realize ideal transfer function T/H required for high input frequencies Conceptually complex Difcult to layout Low speed
Algorithmic or Cyclic
Very low transistor count Low power
Table 2.1. Comparison among several A/D converter architectures.

low bias levels compromise comparator settling time, thus reducing maximum achievable samplerate. In contrast, the feedback architecture, although capable of low power operation, was deemed too slow to meet the 100 MHz sample-rate requirement. Likewise, because of its sequential nature of operation, the algorithmic topology was rejected for inadequate speed. Although capable of somewhat faster operation than the feedback or algorithmic architectures, the feedforward approach was deemed too slow for the demanding 100 Msps operating speed required. The remaining candidate converter types include the pipelined feedforward structure and the folding implementation. Both of these conversion methods show promise, however, as will be
90
demonstrated in the next section, the folding A/D converter in incapable of attaining 10-bit resolution without trimming. Therefore, a hybrid approach using a pipelined feedforward architecture with a constituent ne quantizer base on a folding topology was selected. The details of this architecture and rationale for its selection are discussed next.
2.2 10Bit HighSpeed Converter Topology

A folding A/D converter promises low-power dissipation and is capable of high operating speed; however, mismatches in transistor V BE within the analog folding block can lead to unacceptable threshold errors caused by perturbations in the resultant residue waveform from the ideal. These level errors manifest themselves as degradations in achievable SNR (see section 1.3.3 and equation 1.109) or alternatively as decreases in circuit yield given a maximum INL specication. If the cycle transitions of a folding characteristic such as that depicted in gure 2.6 are perturbed by transistor V BE mismatches, the resultant ADC thresholds will be similarly modied. Equation 1.109 predicts that when calculating the effect of such errors on A/D signal-tonoise ratio, the variance of the threshold errors adds to the quantization noise power. Comparing the expected SNR of a folding A/D converter including the effects of V BE mismatches with the maximum achievable SNR gives the expected SNR degradation from ideal (Fig. 2.9). SNR degradation is plotted in gure 2.9 for combinations of two parameters, F and V Tap . F is the number of folds in the analog residue waveform generated by the analog folding block, and V Tap is the voltage spacing between adjacent cycle transitions in the folding characteristic. For all combinations of these two parameters and assuming V , the standard deviation of V BE BE mismatch, is approximately 1 2mV ; SNR degradation is 1 2dB or less for ADC resolutions less than or equal to 8 bits. However, SNR degradation becomes much more signicant in the higher resolution converters, N = 9 and N = 10 . In the 9-bit case, SNR degradation is probably acceptable for some combinations of F and V Tap ; however in the 10-bit case, SNR degradation is unacceptably large for all combinations of these parameters. Alternatively, the detrimental effect of transistor V BE mismatch on folding A/D performance can be measured by circuit yield. Figure 2.10 depicts ADC yield normalized to maximum allowable INL for the circuit parameters F and V Tap , and for several values of converter resolution, N . For typical values of V (about 1/2 mV) and BE maximum INL (about 1/2 LSB), circuit yield is below 50% in all cases except F = 16 ,
91
0 SNR Degradation (dB)
-.5
-1
-1.5
N=9
-2 0
N=10
SNR Degradation (dB)
-.5 F=8, VTap=64mV F=8, VTap=128mV F=16, VTap=64mV F=16, VTap=128mV
-1
-1.5
N=7
-2 0 .25 .5 Vbe (mV) .75 1 0
N=8
.25 .5 Vbe (mV) .75 1
Figure 2.9.
SNR degradation in folding A/D converters due to V be mismatches. Quantizer resolution indicated on plot. V be
V Tap = 128mV . Note by contrast, that for N = 7 and N = 8 , yield is virtually 100% for all
combinations of F and V Tap . Intuitively, this condition arises because the converter full-scale range is determined by
V FSR = F V Tap
(see gure 2.6). Therefore, the threshold spacing, Q , is given by
(2.2)
Q =
V FSR 2
N
F V Tap 2
N
(2.3)
This voltage must be large compared with V
to prevent signicant threshold errors implying that

BE
V FSR should be increased to mitigate the effects of transistor mismatch. However, F cannot be
92
100 90 80 70 Yield (%) 60 50 40 30 20 10 0 100 90 80 70 Yield (%) 60 50 40 30 20 10 0 0

N=10 N=9 N=8 N=10 F=8 VTap=64mV F=8 VTap=128mV N=9 N=7 N=8 N=7 N=10 F=16 VTap=128mV N=10 N=9 N=8 N=7 F=16 VTap=64mV N=9 N=8
2 3 Vbe /INL (mV/LSB)
2 3 Vbe /INL (mV/LSB)
Figure 2.10. Yield in folding A/D converters for 8 (lower) or 16 (upper) folds per stage. V Tap is 64 mV (left) or 128 mV (right). The normalization of the independent variable to INL refers to maximum specied INL above which point a converter fails the performance test, e.g. if maximum specied INL is 1/2 LSB, and V is 1/2 mV; then the appropriate value on the independent
BE
axis for determining yield is 1. made arbitrarily large without unduly loading the T/H circuit which must drive the A/D converter. Likewise, V Tap is constrained to a small range of values because it must be a small multiple of V T , the thermal voltage, for proper operation of the folding circuits envisioned. (These two points will be made more clear when folding circuits are describe in detail in chapter 6). Therefore, V FSR is limited to a maximum value of approximately
V FSR = F V Tap = 16 128mV = 2.048V

The quantizer step-size, Q , then becomes 2 mV: not large enough relative to V to make BE (2.4)

transistor mismatch effects negligible.
93
The preceding discussion along with the data in gures 2.9 and 2.10 indicate that without trimming, a 10-bit folding A/D converter will exhibit very low yield coupled with degraded SNR because V BE mismatches signicantly perturb threshold positions from their ideal locations. Therefore, the second acceptable topology, the pipelined feedforward approach, was selected as the architecture for this project. However, since the folding A/D implementation offers signicant performance advantages over other approaches for medium-resolution applications, a folding converter was selected to realize the ne quantizer. The resulting ADC architecture (Fig. 2.11)
First Stage
Vin S/H 1 S/H 2 +
Second Stage
X2 (n1-1)
n2-bit Folding & Interpolating Fine Quantizer
n1-bit Flash Coarse Quantizer
n1-bit DAC
Delay Register
Error Correction, Encoding, and Output Registers
Combining Logic
Required linearity: = N bit = n2 bit = n1 bit
Figure 2.11. Typical 2 stage pipelined A/D converter.
comprises a 2-stage pipelined feedforward converter with an input T/H circuit and an interstage T/H circuit. The coarse quantizer drives a reconstruction DAC whose output is subtracted from the held input to form a residue signal. This residue is amplied appropriately and then digitized by a folding ne quantizer. The linearity required from the components of this circuit are indicated in gure 2.11. Both T/H circuits must exhibit linearity consistent with 10-bit operation. Similarly, the DAC and subtracter must be linear to this level. However, owing to the benets of digital error correction, the coarse quantizer needs linearity only consistent with its resolution, n1 , not the full 10-bit resolution of the converter [58], [21]. The amplier and ne quantizer must exhibit linearity consistent with
n2 bits, as expected.
As will be discussed in chapter 3, implementing T/H circuits in bipolar technology proves
94
to be very difcult and requires signicant power dissipation, particularly when wide dynamic range is necessary. Therefore, a modication to the typical pipelined architecture which reduces the required linearity of the second (or interstage) T/H was devised. This modication entails moving the interstage T/H to a location after the subtraction element (Fig. 2.12) where its linearity need only
First Stage
Vin S/H 1 + -
Second Stage
S/H 2 X2
(n1-1)
n2-bit Folding & Interpolating Fine Quantizer
n1-bit Flash Coarse Quantizer
n1-bit DAC
Delay Register
Combining Logic
Required linearity: = N bit = n2 bit = n1 bit
Figure 2.12. Alternative implementation of 2-stage pipelined A/D converter.
match that of the n2-bit quantizer which it drives. The corresponding timing changes necessary to implement this modication are next described.
2.2.1 Timing Scheme for Pipelined Converter

In a conventional pipelined feedforward ADC (Fig. 2.13), the coarse quantizer and the interstage T/H share inputs. These two elements also operate in-phase, meaning that during one clock phase both elements track their mutual input, and during the other clock phase the T/H freezes its output while the coarse quantizer switches its output to a new digital code. The timing signals necessary to produce this behavior are included in gure 2.13, and the resultant output signals from each of the converter blocks are shown in gure 2.14. From these diagrams the throughput delay is seen to be 1.5 clock periods. In the modied pipelined architecture, the interstage T/H is relocated after the subtracter circuit; therefore, the system timing is altered correspondingly (Fig. 2.15). In this arrangement, the
95
1
Vin
1 T/H 2 DAC ADC 1 1 1 1

H T T R R T
1 ADC 2
1 Error Correct & Latch Out

Digital Output
T/H 1
DELAY
(Master)
1 1
T R H T T R
1
H T T R R T
1
T R H T T R
1
H T T R R T
T/H 1 ADC 1 T/H 2 DELAY

Master
T R H T T R
ADC 2 Output
5ns
5ns
T = Track H = Hold R=Regenerate
Figure 2.13. Conventional timing scheme for pipelined A/D converter.

coarse quantizer and interstage T/H do not share a common input, nor do they operate in-phase. Rather, the input T/H and the coarse quantizer operate in-phase so that both elements operate in track mode simultaneously. Therefore, the coarse quantizers digital output word tracks the dynamic input signal (Fig. 2.16), and the DAC analog output forms a real-time (albeit coarse) replica of the input. The dynamically changing DAC output subtracts from the active output of the rst T/H to form the residue signal which drives the interstage T/H. The throughput delay in this arrangement is 1.5 clock periods as in the conventional case. Since the input T/H and the coarse quantizer operate in track mode simultaneously, the coarse quantizer must digitize a dynamic signal rather than a static one. The coarse quantizer is therefore susceptible to the nite aperture time effects described in section 1.3.3. Two factors mitigate these effects which would normally degrade coarse quantizer linearity severely. First, the resolution of the coarse quantizer is quite low (only 4 bits as will be seen shortly) so that large aperture-time induced errors are tolerable. And second, the clock to the coarse quantizer is retarded by 1 ns to allow the T/H output to settle before quantization begins.
96
n-1
n+1
n+2
T/H 1 Output ADC 1 Output T/H 2 Output DAC Output ADC 2 Output Delay Output Latch Output
n-2 n-1 n n+1
n-1
n+1
n-1
n+1
n-1
n+1
n-2
n-1
n+1
n-2
n-1
Output signals from converter elements in pipelined A/D employing conventional timing scheme. This rather unconventional clocking arrangement is motivated by the desire to replace the interstage T/H requiring 10-bit linearity with a simpler and lower power T/H requiring only m2-bit linearity. The new scheme does not degrade converter linearity because the coarse quantizer is very low resolution, only 4 bits, and because the coarse quantizer clock signal is delayed slightly to allow adequate settling before quantization. The low resolution coarse quantizer is made possible because the ne quantizer which uses the folding architecture is particularly efcient, realizing 7 bits of resolution with roughly the same number of transistors and power dissipation as the 4-bit coarse quantizer.
Figure 2.14.
2.3 Pipelined Feedforward Partitioning

In a pipelined feedforward A/D implementation without error correction, the converter resolution equals the sum of the resolutions of the individual stages. If error correction is used, the converter resolution diminishes by the amount of redundancy (in bits) used for the correction. In the present design, one bit of error correction or overrange is used so the sum of the resolutions of the individual stages must equal 11. The next sub-sections describes the rationale behind the
97
1
Vin
1 T/H 2 DAC
1 ADC 2
1 Error Correct & Latch Out

Digital Output
T/H 1
ADC 1 1 1 T/H 1 ADC 1 T/H 2 DELAY

Master H R T R T T
DELAY
Master
STAGE
Slave
1 1
H R T T R T H R T R
1 1
T T T T R T
1
H R
1
T T H R T R
1
H
T T R T
ADC 2 Output 1ns
5ns
5ns
T = Track H = Hold R=Regenerate
Figure 2.15. Modied timing scheme for pipelined A/D converter.

partitioning of this total resolution between the coarse and ne quantizers. Most feedforward converters use substantially identical architectures for each constituent quantizer. Therefore, dividing the complexity evenly between stages reduces the total complexity of the A/D converter. Since in this project a very efcient folding converter is used as the ne quantizer, evenly partitioning the resolution among stages does not minimize device count. Rather, a distribution with a very low resolution coarse quantizer followed by a higher resolution folding ne quantizer yields lower complexity. Circuit yield and expected performance also play a role in selecting the partitioning of resolution among stages. Some selections are more sensitive to errors induced by device mismatches and are therefore less robust than other partitionings. Optimized converter partitioning minimizes device count (hence power dissipation and die size) without degrading yield or expected performance given device mismatches.
98
n-1
n+1
n+2
T/H 1 Output ADC 1 Input DAC Output T/H 2 Output ADC 2 Output Delay Output Latch Output
n-2 n-1 n n+1 n+2
n-1
n+1
n+2
n-1
n+1
n-1
n+1
n-2
n-1
n+1
n-2
n-1
Figure 2.16. Output signals from converter elements in pipelined A/D employing modied timing scheme.
2.3.2 Hardware Complexity (Parts and Power)

The number of transistors in a ash quantizer is proportional to the number of comparators required, 2 1 , where the proportionality constant equals the number of transistors necessary for each comparator (including associated circuitry such as a preampliers and logic gates for encoding). Likewise, the number of transistors required for a folding quantizer equals the sum of the transistors comprising the analog folding block, the coarse quantizer, and the ne quantizer (see Fig. 2.6). The analog folding block and the coarse quantizer complexity depend only upon F , the number of periods in the folding characteristic, and not upon N , the quantizer resolution, whereas the ne quantizer complexity is proportional to 2 F . Therefore, the total complexity of an N-bit folding quantizer equals a constant proportional to F plus a term proportional to 2 F . The above results are summarized in gure 2.17 which plots total complexity (as measured by transistor count) of a 10-bit 2-stage feedforward A/D converter consisting of a ash coarse quantizer and a folding ne quantizer and assuming one bit of overrange for error correction. This
N N N
99
104
Transistor Count
10-Bit A/D
103
Second Quantizer (8 Folds) First Quantizer
Assumes 1-Bit Overrange 102 1 2 3 4 5 6 7 8 9 10
First Quantizer Resolution

Figure 2.17. Comparison of A/D converter complexity versus ne quantizer
resolution. plot shows that ADC complexity is minimized if the rst quantizer is selected to have 4-bit resolution. This is a broad minimum, however, so 3-bit and 5-bit coarse quantizers also produce low total converter complexity. As will be shown in the next sub-section, the 3-bit coarse quantizer partitioning is overly sensitive to component mismatching producing inadequate yield and excessive threshold errors. Therefore, only the partitionings based on 4-bit and 5-bit coarse quantizers are considered further. The A/D converter utilizing a 5-bit coarse quantizer (called the 56 partitioning) is depicted in gure 2.18 which indicates the linearity requirements of each component. The contending architecture based on a 4-bit coarse quantizer (the 4-7 partitioning) is depicted in gure 2.19. Since the 4-7 approach exhibits lower complexity than the 5-6 partitioning, the former should be utilized unless sensitivity to component mismatches proves otherwise.
2.3.3 Performance (Yield and SNR)

The 4-7 and 5-6 partitionings exhibit different sensitivities to component mismatches.
100
First Stage
Vin S/H 1 + -
Second Stage
S/H 2 X16
6-bit Folding & Interpolating Fine Quantizer
5-bit Flash Coarse Quantizer
5-bit DAC
Delay Register
Combining Logic
Required linearity: = 10 bit = 6 bit = 5 bit
10-bit Digital Output
Figure 2.18. 5-6 pipeline partitioning.
First Stage
Vin S/H 1 + -
Second Stage
S/H 2 X8
7-bit Folding & Interpolating Fine Quantizer
4-bit Flash Coarse Quantizer
4-bit DAC
Delay Register
Combining Logic
Figure 2.19. 4-7 pipeline partitioning.

These sensitivities can be ascertained by simulation, and an optimum partitioning can be selected based upon the results. Component mismatches which affect ADC performance include DAC current source error, coarse quantizer INL, ne quantizer INL, ne quantizer gain error, and DAC gain error. The effects of each of these error sources is investigating by simulating the ADC transfer function in the presence of the specied error. The threshold perturbations due to the error source can then be quantied by specifying the resultant A/D converter SNR.
101
DAC current source matching is largely determined by resistor matching which is usually expressed by the standard deviation of resistor mismatch normalized to the mean resistance value. That is, for resistors with mean value R , and standard deviation R , the resistor mismatch is
R R expressed in percent. In a well-controlled monolithic process R R is usually a small

fraction of 1%. The effect of DAC current source matching was determined via Monte Carlo analysis where, for a large number of test cases, a random distribution is selected for the DAC current source values. The resultant ADC transfer function is calculated, and SNR based upon threshold errors is determined. The distribution of SNR values associated with the ensemble is then specied by its ensemble average or yield, the percentage of test cases where SNR is above some specied value (in this case 59 dB). The dependence of A/D converter SNR on DAC current source mismatch (Fig. 2.20) is stronger for the 4-7 partitioning than for the 5-6 partitioning. However, the anticipated resistor mismatch in Tektronix SHPi process is approximately 0.1%. At this value of
R R , the difference in expected SNR between the two cases is negligible.

Coarse quantizer INL is largely due to transistor mismatches and is specied by its rms value in LSBs. The effect of this error source on converter SNR was investigated with the same method used for DAC current source mismatch phenomenon. Owing to the digital error correction used in the proposed topologies, coarse quantizer INL less than 1/2 LSB in magnitude does not affect A/D converter SNR (Fig. 2.21). Since 1/2 LSB rms INL is easily obtainable for both the 4bit quantizer and the 5-bit quantizer cases, coarse quantizer INL will not substantially impact overall A/D converter performance. Fine quantizer INL was investigated in identical manner to coarse quantizer INL resulting in the plots included in gure 2.22 which indicate that SNR sensitivity to ne quantizer INL is identical for the 4-7 and 5-6 partitionings. However, since a specied INL in a 6-bit ne quantizer is more readily obtained than in a 7-bit quantizer, this data indicates that the 5-6 partitioning is more robust in this regard. For the feedforward topology to operate correctly, the input-referred full-scale-output from the DAC must equal the full-scale input to the coarse quantizer. Likewise, the full-scale output from the amplier block must equal the full-scale input to the ne quantizer. Mismatches in these settings introduce systematic errors into the ADC transfer function.
102
100 90 80 ADC Yield at 59 dB (%) 70 60 50 40 30 20 10 0 62 61 60 Mean SNR (dB) 59 58 57 56 55 54 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 DAC Current Source Matching (%) 0.9 1.0
n1=5 n2=6 n1=4 n2=7
n1=5 n2=6 n1=4 n2=7
Figure 2.20. 10 bit A/D converter yield (upper) and mean SNR (lower) versus segmented DAC current source mismatch for both 4-7 and 5-6 partitioning.
If the DAC full-scale-output is set incorrectly; that is, if its gain is erroneous, threshold errors result which degrade SNR. Such threshold errors are a deterministic function of the DAC gain error and can be calculated via simulation. A/D converter SNR, calculated in this manner, is plotted for a range of gain errors in gure 2.23. This gure indicates that SNR degradation for the 4-7 partitioning is a stronger function of DAC gain error than for the 5-6 partitioning. However, for DAC gain errors of approximately 1%, the degradation is less than 2 dB and the discrepancy between the 4-7 partitioning and the 5-6 is even less.
103
100 90 80 ADC Yield at 59 dB (%) 70 60 50 40 30 20 10 0 65
n1=4 n2=7
n1=5 n2=6
60 Mean SNR (dB)
55
n1=5 n2=6
50
n1=4 n2=7
45
40 0.0
0.1
0.2
0.3 0.4 0.5 0.6 0.7 Coarse Quantizer INL (Bits)
0.8
0.9
1.0
Figure 2.21. 10 bit A/D converter yield (upper) and mean SNR (lower) versus coarse quantizer INL for both 4-7 and 5-6 partitioning.
Fine quantizer gain errors are treated in a manner analogous to DAC gain errors. Simulations of this deterministic phenomenon indicate that the sensitivity of the 4-7 topology to this effect is greater than the 5-6 case (Fig. 2.24). Again, however, the difference in sensitivities is small for the range of mismatches anticipated which is approximately 1%. To assess the cumulative effect of component mismatches on SNR, Monte Carlo simulations varying all of the above error sources were performed. The resulting histograms of SNR
104
100 90 80 ADC Yield at 59 dB (%) 70 60 50 40 30 20 10 0 62 61 60 59 58 57 56 0.0
n1=5 n2=6
n1=4 n2=7
Mean SNR (dB)
n1=5 n2=6 n1=4 n2=7

0.1 0.2 0.3 0.4 0.5 0.6 0.7 Fine Quantizer INL (Bits) 0.8 0.9 1.0
ne quantizer INL for both 4-7 and 5-6 partitioning. give insight into the expected operation of the 4-7 and 5-6 partitioned A/D converters. These histograms (Fig. 2.25) indicate that for the component mismatches anticipated, the expected SNR for the 5-6 partitioning will be clearly superior to that for the 4-7 partitioning. However, the 4-7 partitioned samples indicate adequate performance with nearly all samples exhibiting SNR equal to 59 dB or greater.
105
62 60 58 56 SNR (dB) 54 52 50 48 46 44 10
n1=5 n2=6
n1=4 n2=7
n1=4 n2=7
ADC Gain Error (%) 5
n1=5 n2=6
-5
-10 -10
-8
-6
-4
-2 0 2 DAC Gain Error (%)
10
Figure 2.23. 10 bit A/D converter SNR (upper) and gain error (lower) versus DAC gain error for both 4-7 and 5-6 partitioning.
Because the 4-7 partitioning offers a signicant complexity advantage over the 5-6 partitioning and delivers adequate insensitivity to expected component mismatches, this topology was selected over the more robust 5-6 approach. The nal 10-bit A/D converter architecture (Fig. 2.26) consists of a pipelined feedforward topology with a 4-bit coarse quantizer and a 7-bit folding ne quantizer. The interstage T/H is located after the subtracter element so that it needs to exhibit linearity consistent with 7-bit quantization. The input T/H and the coarse quantizer operate in track
106
62 60 58 56 SNR (dB) 54 52 50 48 46 44 0.05 0.04 0.03 ADC Gain Error (%) 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 -0.05 -10 -8 -6 -4 -2 0 2 4 Fine Quantizer Gain Error (%) 6 8 10
n1=5 n2=6
n1=4 n2=7
n1=4 n2=7
n1=5 n2=6
Figure 2.24. 10 bit A/D converter SNR (upper) and gain error (lower) versus ne quantizer gain error for both 4-7 and 5-6 partitioning.
mode simultaneously to enable this placement of the interstage T/H. Consequently, the coarse quantizer sample clock is retarded by 1 ns relative to the other A/D clocks to allow for adequate settling from the input T/H before coarse quantization. The one bit of overrange is used for error correction so that coarse quantizer threshold errors less than 1 LSB will not affect the A/D converter linearity.
107
40 35 Number of Occurrences 30 25 20 15 10 5 0 70 60 Number of Occurrences 50 40 30 20 10 0 58.0
n1=4, n2=7 Gain Error = 0.25% Offsets = 2 mV INL1 = 1/32 LSB INL2 = 1/4 LSB DAC Error = 0.2%
n1=5, n2=6 Gain Error = 0.25% Offsets = 2 mV INL1 = 1/16 LSB INL2 = 1/8 LSB DAC Error = 0.2%
58.5
59.0
59.5
60.0 60.5 SNR (dB)
61.0
61.5
62.0
Figure 2.25. Histogram of A/D converter SNR for 4-7 (upper) and 5-6 (lower)
partitionings.
References
[1]
D. H. Sheingold, ed., AnalogDigital Conversion Handbook. PrenticeHall, third ed., 1986. The Engineering Staff of Analog Devices.
108
First Stage
Vin T/H 1
Second Stage
T/H 2 X8
7-Bit
Folding & Interpolating Second Quantizer
4-Bit
Flash First Quantizer
4-Bit
DAC
Delay Register
Combining Logic
Figure 2.26. Block diagram of selected A/D converter architecture.

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Chapter 3
Sample-and-Hold Design
The function and specication of Sample-and-Hold (S/H) circuits was discussed in section 1.3.1. The hardware implementations of such devices which are also referred to as Track-and-Hold (T/H) circuits or Sample-and-Hold Ampliers (SHAs) will now be described. A T/H circuit comprises ve elements; an input preamplier, a sampling switch, a storage element which is assumed to be a capacitor, an output amplier or postamplier, and a clock buffer (Fig. 3.1a). The preamplier presents a high or well-controlled impedance to the signal source while maintaining a low output impedance for rapidly charging and discharging the storage or hold capacitor. Additionally, the preamplier can provide gain to maximize the dynamic range of the stored signal. The sampling switch, when closed, enables the preamplier to drive the stored signal on the hold capacitor; and, when open, disconnects the hold capacitor from the preamplier preserving a constant stored signal equal to the value at the instant the switch was opened. The postamplier presents a high impedance to the hold capacitor to minimize leakage of the stored charge and drives succeeding circuitry with a (possibly amplied) replica of the held signal. Frequently, the postamplier exhibits low output impedance thus ensuring adequate frequency response and distortion characteristics when driving capacitive loads. The clock buffer facilitates switch operation by providing suitable logic signals in response to the incoming clock. Such buffering
. T/H circuits which employ inductors as storage elements are possible in theory but for a variety of reasons have proven impractical. Superconducting coils have been investigated for this purpose.
116
Chapter 3 Sample-and-Hold Design
Amplitude
Acquisition time Track Settling A/D time time Conversion time
Vout
Sampling Switch
Vin
Output Buffer
Input Buffer
Vin
Hold Capacitor Clock Buffer Track/Hold Command
Vout
Hold
Sample
Hold
time
Track/Hold Command
Hold
Track
Hold
Track
time
(a)
(b)
Figure 3.1. Track-and-hold building-blocks (a) and operation (b).

requires adequate gain and frequency response without unduly exacerbating clock timing jitter. This operation is depicted graphically in gure 3.1b. Each of the elements described above can be easily implemented in a standard bipolar integrated circuit technology (such as Tektronix SHPi) with the exception of the sampling switch. High-performance switches are particularly difcult to realize in bipolar processes, and the availability of native integrated circuit switches in MOS technologies provides compelling motivation to use such processes when analog switching is necessary. The inferior capabilities of MOS devices in high-speed, high-accuracy applications; however, limits the utility of this option. Complementary processes combining both bipolar and MOS devices (BiCMOS) provide an adequate solution, but these processes are currently rare and expensive. Therefore, utilization of a high-performance bipolar switch is imperative. Such a circuit will be discussed in detail next.
3.1 Sampling Bridge Topology and Operation

The basis of almost all analog switches implemented in bipolar IC technologies is the diode sampling bridge (Fig. 3.2) which provides a low impedance between input and output when conducting, high isolation when not conducting, and very fast switching between the conducting and non-conducting states. This architecture has been widely used in sampling applications for many years owing to its simplicity and speed of operation [6], [7], [8]. The diode-bridge switch is
117
Vin
D1
D2
Vout D3 D4 CH
Preamplifier Diode Bridge
Postamplifier
Figure 3.2. Prototype diode bridge track-and-hold circuit with emitter follower
preamplier and postamplier. virtually a necessity in bipolar semiconductor technologies lacking eld-effect transistors (FETs) and has been popular in silicon technologies [9], [8], [10], [11], [12] and more recently in GalliumArsenide (GaAs) Heterojunction Bipolar Transistor (HBT) technologies [13], [14]. The diodebridge has frequently been used even in some technologies with native FET devices [15], [16], [17], [18] because of its superior switching properties, but the emerging preeminence of CMOS technology has driven many workers to pursue high performance track-and-hold circuits based upon CMOS switches [19], [20], [21], [22], [23], [24], [25]. Others have developed switches in bipolar technologies without diode-bridges [26], [27], [23] or have utilized FET switches in more exotic technologies such as GaAs [29], [30]. The diode-bridge switch offers speed and precision advantages over most other approaches but suffers from some disadvantages which must be contended with to develop high-performance T/H circuits. These drawbacks will be discussed in the next several sections. The preamplier and postamplier in gure 3.2 are simple emitter follower buffers, but any type of amplier fullling the characteristics described in the preceding introduction will sufce. Selection of amplier topologies for these functions depends upon practical considerations such as linearity, power dissipation, frequency response, complexity, etc. Since this section details operation of the diode bridge itself, the pre- and postampliers comprising the track-and-hold in gure 3.3 are depicted as ideal elements for simplicity while the bridge drive circuitry consists of a
118
Bridge
Bridge
D1 D6
D2
Vin
X1
VCT
D4
X1
Vout
D3
D5
CH
I1
I2 Q2
Hold
Q1
Track
2I
Bridge
Figure 3.3.
bridge current.
Diode-bridge track-and-hold with differential pair controlling
differential transistor pair and ideal current sources. The circuit operates in the following manner. When in track mode, transistor Q2 conducts all of the diff-pair current causing I1 = 0 and
I2 = 2I Bridge . Consequently, each of the diodes D1 through D4 conducts I Bridge 2 causing their
small-signal impedances to be very low, I Bridge 2V T . The preamplier can therefore charge or discharge the hold capacitor, C H , through the small impedance ( r d1 + r d2 )
( r d3 + r d4 )
enabling V out to track V in . Conversely, in hold mode transistor Q1 conducts the diff-pair current resulting in I1 = 2I Bridge and I2 = 0 . In this case diodes D1 through D4 conduct no current thereby interposing a large (ideally innite) small-signal impedance between the preamplier and the hold capacitor. Diodes D5 and D6 conduct I Bridge pinning the top and bottom of the bridge at
V CT V D and V CT + V D respectively where V CT is some convenient bias voltage and V D is the

forward diode voltage drop. In this state the output is effectively isolated from the input. Although fairly simple and capable of faithfully replicating analog switch operation, this topology suffers from several drawbacks which limit performance and which will be discussed in detail next. The nature of diode bridge operation during track mode is quite complicated and will be elaborated upon with reference to gure 3.4 which shows a diode bridge with ideal current drive. When the current sources in gure 3.4 are at value zero, all 4 diodes conduct no current and the
119
IBias 0 D1 Vin D2 Vout
D3
D4 IBias 0
Figure 3.4. Diode-bridge switch.

output terminal is isolated from the input terminal as described previously. When the current sources are at value I Bias , circuit operation depends upon the exponential relationship between diode voltage and current:
I D = I SA e
VD VT
= I S Ae
VD VT
(3.1)
where I S is the diode saturation current, A is the diode area and V T is the thermal voltage, kT q , which equals approximately 26mV at room temperature. Performing KVL around the loop of diodes gives
V D1 + V D3 = V D2 + V D4
which through the use of equation 3.1 becomes
(3.2)
V T ln
I D1 I D3 I D2 I D4 + V T ln = V T ln + V T ln A1 IS A3 IS A2 IS A4 IS
(3.3)
If all of the I S terms are assumed to be identical (the area parameters A1 through A4 can be suitably modied to account for any mismatches in saturation current) equation 3.3 can be
120
simplied to
A1 A3 I D1 I D3 = = I D2 I D4 A2 A4
(3.4)
where is dened as the ratio of areas as shown. If all diode areas are equal mandating = 1 equation 3.4 becomes
I D1 I D3 = I D2 I D4
(3.5)
Performing KVL around the upper (lower) half of the diode ring gives a constraint on V D1 and V D2 ( V D3 and V D4 ):
V in V out = V D2 V D1 ( V in V out = V D3 V D4 )
Using the diode I-V characteristic (Eq. 3.1) in the rst equation above yields
(3.6)
V in V out = V T ln = V T ln
I D2 I D1 V T ln A2 IS A1 IS I D2 A 1 I D1 A 2 I D2 I D1
(3.7)
= V T ln
where the last simplication assumes A1 = A2 . Solving for I D2 gives
I D2 = I D1 e
( V in V out ) V T
(3.8)
This surprisingly simple result is representative of all circuits in which a set of elements with exponential I-V characteristics form a closed voltage loop. The above relationship arises because the elements transconductances are linear functions of their branch currents. Such topologies have therefore been dubbed translinear circuits [1] and have seen widespread use in analog multipliers, dividers, and other function generators [2], [3], [4], [5].

An additional constraint is found by performing KCL at the top of the diode bridge producing
121
I D1 + I D2 = I Bias
Equations 3.8 and 3.9 can be solved for I D1 and I D2 .
(3.9)
I D1 = I Bias I D2 = I Bias
1 e
( V in V out ) V T
+1 +1
e e
( V in V out ) V T
(3.10)
( V in V out ) V T
The differential current I D2 I D1 can be easily found as well
I D2 I D1 = I Bias
e e
( V in V out ) V T ( V in V out ) V T
1 +1
(3.11)
V in V out = I Bias tanh 2V T
According to equation 3.6, V D4 and V D3 are related to V in V out in the same manner as V D1 and
V D2 respectively; therefore, I D3 , I D4 , and I D3 I D4 can be found by analogy to equations 3.10

and 3.11.
I D3 = I Bias I D4 = I Bias
e e e
( V in V out ) V T
( V in V out ) V T
+1 +1
(3.12)
1
( V in V out ) V T
I D3 I D4 = I Bias tanh
V in V out 2V T
The following two equivalencies stemming from equation 3.10 and 3.12 should be noted:
I D1 = I D4 I D2 = I D3
(3.13)
and can be used to determine I out in terms of I in (where I in and I out are dened to ow into the
122
diode bridge at the input and output nodes respectively),
I in = I D3 I D1 = I D2 I D4 = I out
Alternatively, equation 3.11 and 3.13 can be used to solve for I in (3.14)
I in = I D3 I D1 = I D2 I D1 V in V out = I Bias tanh 2V T

(3.15)
Equation 3.15 predicts that I in is a function of V in V out which implies that the diode bridge behaves identically to a non-linear resistor placed between the input and output ports. The incremental value of this conductance which depends upon the applied voltage can be found by differentiating equation 3.15 with respect to V in V out .
g Bridge =
d ( I ( V) ) = dV
2
d I Bias tanh ( dV 1 V ) 2V T 2V T
V ) 2V T
(3.16)
= I Bias sech ( =
I Bias V 2 sech ( ) 2V T 2V T
or alternatively
r Bridge =
I Bias 2
VT
cosh (
V ) 2V T
(3.17)
Comparing this expression to that generated via small-signal analysis is instructive. In the smallsignal equivalent circuit of the diode bridge in track mode (Fig. 3.5b) each diode is replaced by r d , the diode small-signal resistance, which is equal to V T I D . Since each diode is nominally biased at I Bias 2 , r d becomes V T ( I Bias 2 ) . The combination of the 4 resistors in gure 3.5b is equivalent to one resistor of value r d spanning from input to output also of value r d . The large-
123
rd V1 r eq rd r eq = r d cosh (a) V1 V2 VT rd = VT V2 V1
rd V2 rd
I Bias 2 (b)
Figure 3.5. Diode-bridge models in track mode. (a) Large-signal model. (b) Small-signal model.
signal model shown in gure 3.5a gives identical results; that is, a resistance of value
V T ( I Bias 2 )
when the voltage difference between input and output is 0 (since
cosh ( 0 ) = 1 ). The large-signal non-linear model more accurately predicts bridge behavior for V in V out 0 with an attendant increase in complexity.
Intuitively, the bridge operates by steering the bridge bias current under control of the applied voltage. When V out equals V in the bridge is balanced with equal current I Bias 2 owing in all diodes and I in = I out = 0 (Fig. 3.6a). If V in > V out , diodes D2 and D3 experience
D1
D2
D1
D2
D1
D2
Vin
D3 D4
Vout
Vin
D3 D4
Vout
Vin
D3 D4
Vout
(a)
(b)
(c)
Figure 3.6. Diode bridge operation in track mode. (a) V in = V out t. (b) V in > V out . (c) V in < V out .
124
larger voltage drops and consequently conduct more current than D1 and D4 resulting in current being drawn from the input node and delivered to the output (Fig. 3.6b). Conversely, if V in < V out , diodes D1 and D4 conduct more strongly than D2 and D3 with current sunk by the input and sourced by the output (Fig. 3.6c). In each of these cases I D1 = I D4 and I D2 = I D3 . Also, when one current exceeds another, it does so by the factor e
( V in V out ) V T
The diode-bridge as described above forms the basis of a practical switch which is supported by a preamplier and postamplier as well as circuitry to provide the bridge with the appropriate pulsed bias current. A block diagram of such a conguration is shown in gure 3.7
+ _
+ _
Bridge Driver
Bridge Driver
(a)
(b)
Figure 3.7. T/H topologies. (a) Single-ended. (b) Differential.
which also includes a differential realization incorporating two bridges and differential pre- and post-ampliers. Differential implementations enjoy several advantages over single-ended approaches including: rejection of common-mode errors such as power supply modulation and unwanted signals coupled onto differential signal nodes; elimination (ideally) of all even order distortion products; improved dynamic range since signal power quadruples (due to the doubled signal amplitude compared to the single-ended case) while noise power only doubles; and the availability of both signal polarities which can frequently be used advantageously to improve linearity or operating speed. These benets are countered by the disadvantages that the differential approach requires more components (and hence die area) and consumes more power than a single-
3.2 Error Sources in Diode Sampling Bridges
125
ended implementation. For the present application, the advantages accrued by the differential approach outweigh the disadvantages; therefore, the more complicated method was used as will be detailed in section 3.3.

T/H performance and hence A/D performance are limited by the operation of the diodebridge circuit. Understanding the factors constraining their behavior is therefore crucial to developing bridges with optimum specications. The next several sections analyze the various error sources which impinge upon diode-bridge T/H operation.
3.2.1 Aperture Jitter

Random variations in the otherwise periodic sampling interval caused by electronic noise will limit A/D converter performance because temporal errors in the sampling instant manifest themselves as equivalent amplitude errors at the quantizer output [10], [15], [16], [13], [14]. Whereas the explanation of this effect in section 1.3.3 predicted performance bounds as limited by 1/2 LSB amplitude errors, the present analysis predicts SNR degradation based upon the statistics of the signal and the sampling clock phase noise. If a T/H circuit operates with a sampling period
T = T nom + jitter where jitter is a zeromean Gaussian random variable such that 1 2 2
jitter 2
2 2
P ( jitter ) =
(3.18)
and an analog input signal V in ( t ) = A sin ( in t ) , then the voltage error due to the timing jitter is the product of the derivative of the input signal (with respect to time) and the jitter (Fig. 3.8). This relationship can be expressed using the notation of gure 3.8:
V =
dV in dt jitter = A in cos ( in t )
(3.19)
jitter
In this equation, arbitrary input amplitude, A , is assumed rather the full-scale amplitude assumed
126
V fs
V ( t ) = V fs sin ( 2f in t ) Slope = dV ( t ) dt V fsr = 2V fs ddV V T
Q = 2V fs 2 dt dT V fs
Figure 3.8. Aperture jitter gives rise to amplitude error.

in gure 3.8. The noise power due to jitter is
2 = E { V } jitter
(3.20)
where the expectation is calculated over all values of t such that 0 t T = 1 f in and over all

values of jitter . (In the equations below, jitter is replaced by for simplicity.)
127
2 jitter
1 = T =
T 0 T 0
( V ) P ( ) d dt
1 T
T
[ A in cos ( in t ) ] P ( ) d dt

1 2 = [ A in cos ( in t ) ] dt T
0 T
P ( ) d
2
1 2 [ A in cos ( in t ) ] dt T
0
2 P ( ) d
(3.21)
( A in ) T ( A in ) 2
2T
cos
0 2
( in t ) dt
2
2
= 2 ( Af in )
The above differs from Wakimoto et al [13] but agrees with Martin and Secor [10]. The SNR due to timing jitter is
SNR jitter = =
2 S 2 jitter
A 2 2 ( Af in )
2 2
(3.22)
1 ( 2f in )
which is independent of the input signal amplitude. For a given time jitter, jitter , the phase error, clock , is
clock = clock jitter
(3.23)
128
where clock is the radian clock frequency. Therefore,
= clock
Using this expression in equation 3.22, the SNR due to jitter becomes
(3.24)
SNR jitter =
1 ( 2f in )
2
1
2 in clock
(3.25)
or in decibels
SNR jitter = 20 log
clock 20 log ( ) dB in
f clock = 20 log 20 log ( ) dB f in

Under Nyquist conditions where f clock 2f in this expression simplies to
(3.26)
SNR jitter = 20 log ( 2 ) 20 log ( ) dB = 6 20 log ( ) dB
(3.27)
This very simple result is independent of input amplitude predicting SNR degradation solely in terms of sample clock spectral purity as specied by phase noise. To attain 62 dB SNR (consistent with 10 effective bits of resolution), equation 3.27 constrains the standard deviation of the integrated phase noise to be less than 1.6 milliradians. At 100 MHz clock rates this phase noise translates to 2.5ps standard deviation of jitter (using equation 3.24). Since this noise source will combine in a root-mean-square fashion with the quantization noise, total SNR will decrease by 3 dB under such circumstances. To maintain total SNR including effects of clock jitter and quantization at an acceptable level, SNR due to jitter alone must be reduced to a fraction of the above levels. To assess the combined effects of clock jitter and quantization noise, equation 3.22 can be modied to include both error sources resulting in:
129
SNR j + Q = = =
2 S 2 + 2 jitter Q
2
= 1
A 2 2 ( Af in ) + ( 2A 2 ) 12
2N 2 N 2
( 2f in ) + ( 2 3 ) 2 1
2
(3.28)
in 2N + ( 2 3) 2 clock
Expressed in decibels this equation becomes

2 in 2N + ( 2 3) 2 = 10 log clock
SNR j + Q
(3.29)
= 10 log ( 2 4 + ( 2 3 ) 2
2N
milliradians ( =0.8ps at f clock =100 MHz) is reasonable for a 10-bit quantizer. Phase noise or sample jitter exists on the clock signal driving the T/H but is increased by electronics within the clock buffer and bridge driver circuitry. A typical bridge drive implementation (Fig. 3.3) utilizes a differential transistor pair (Q1,Q2) to control the bridge current. The phase noise in equations 3.26 and 3.27 is that at the collectors of the differential pair. Consequently, noise contributions from the differential pair and from the preceding clock buffer must be referred to the collector nodes when calculating SNR loss. Such performance degradation constrains the clock buffer design and will be addressed in more detail in section 3.3.3.
where the last equality assumes clock = 2 in . Equations 3.27 and 3.29 are plotted in gure 3.9 from which can be read for a given quantizer resolution, N, and desired SNR. =.5
3.2.2 SmallSignal Bandwidth

Small-signal operation of the diode-bridge in track mode was discussed in some detail in section 3.1. Here the bandwidth of a track-and-hold based upon a bridge switch will be determined. The small-signal equivalent circuit of such a S/H in track mode (Fig. 3.10) replaces each diode with a resistor, r d , of value V T ( I Bridge 2 ) . Because the bridge is modelled by two Tee networks in parallel the simplied circuit of gure 3.10b can be used to determine its frequency response. In the
130
120
SNR jitter = 6 20 log ( ) dB

100
16 15 14
SNR (dB)
80
13 12 11 10
60
9 8 7
40
6 5 N=4
20 -5 .01 10
.1 10
-4
(radians)
1 10
-3
10 10
-2
100 10
-1
Figure 3.9. SNR as limited by clock jitter and quantization noise. Quantizer
resolution labelled on curves. analysis which follows the variables r d and R L from gure 3.10b will be written as r d and R L respectively to clarify the notation. Care will be taken to appropriately accommodate this change in notation once the desired results have been derived. The output voltage, V out , is developed through an impedance divider from node 1.
V out V1
1 sC H 1 = = 1 1 + sr d C H + rd sC H
(3.30)
V 1 is in turn developed through an impedance divider from V in : V1 Z1 = V in rd + Z1

(3.31)
131
RL rd Vin X1 rd RL
(a)
rd X1 rd CH Vout
Vin
X1 r d r = rd /2 d R = RL/2 L
V1 R L
(b)
X1 r d CH
Vout
Figure 3.10.
Small-signal models of diode-bridge in track mode. (a) Full model. (b) Simplied model when parallel networks are combined.
where Z 1 is the impedance seen from node 1 to ground.
Z1 = RL ( rd +
( 1 + sr d C H ) 1 ) = RL sC H ( 1 + s ( RL + rd ) CH )
(3.32)
132
V 1 V in can therefore be simplied to: ( 1 + sr d C H ) V1 ( 1 + s ( RL + rd ) CH) = V in ( 1 + sr d C H ) rd + RL ( 1 + s ( RL + rd ) CH ) RL = = = R L ( 1 + sr d C H ) r d ( 1 + s ( R L + r d ) C H ) + R L ( 1 + sr d C H ) R L ( 1 + sr d C H ) ( R L + r d ) + sC H ( 2R L r d + r d ) RL ( RL + rd ) ( 1 + sr d C H ) RL rd 1 + sC H r d + RL + rd

2
(3.33)
And the track mode small-signal transfer function becomes
V out V out V 1 = V in V 1 V in RL ( 1 + sr d C H ) 1 = ( ) 1 + sr d C H ( R L + r d ) RL rd 1 + sC H r d + RL + rd = RL ( RL + rd ) 1 RL rd 1 + sC H r d + RL + rd
(3.34)
To account for the notational change introduced earlier r d and R L must be replaced by r d 2 and
133
R L 2 respectively giving V out RL = V in ( RL + rd ) = 1 rd 1+ R L 1 + sC r d H2 1 1 + sC H r d
1 1 + sC H rd 1 RL rd + 2 2 RL + rd 1 1 1 + rd 1+ R
(3.35)
where the last approximation assumes R L r d . Since r d is a very low resistance (less than 50 in most cases) this assumption is well justied. Also, since the hold capacitance, C H , is generally much larger than the device intrinsic capacitances, the single-pole approximation of equation 3.35 is valid. Therefore, to a very close approximation, the diode-bridge will exhibit unity-gain at low frequency and a single-pole roll-off with time-constant, Bridge = r d C H . For values of bridge current on the order of 1 mA and hold capacitances of a few pF, bandwidths near 1 GHz are attainable. Therefore, small-signal frequency response is rarely a limiting factor for diode-bridge T/H performance.
3.2.3 Preamplier TrackMode Distortion

Dynamic distortion arises in the preamplier and sampling bridge during track mode because these elements must supply dynamic current to circuit capacitors (parasitic and nonparasitic) at the frequency of the input to the T/H. Conversely, the postamplier need not exhibit good linearity in track mode but must settle to a relatively distortion-free value during hold mode. In fact, this state of affairs is the motivation for preceding A/D converters with sample-and-hold circuits. Only the preamplier and switch need to exhibit dynamic linearity. All subsequent components, including the postamplier, comparators, and any other signal processing circuitry can have very poor dynamic linearity so long as they settle within the allotted time to an appropriate DC value. Since fast settling and good DC linearity are much easier to achieve than dynamic linearityconsiderable savings in power and circuit complexity can be achieved by isolating the
134
required dynamic performance to the preamplier and switch. These elements can then be suitably optimized to realize the desired performance with a net savings in power and circuit complexity. This section analyzes the dynamic distortion which affects the preamplier and bridge during track operation. Figure 3.11 depicts schematically the prototype preamplier used for this study which is an
50
Vin Vout
50
CLoad
V src =Asin int V = A sin int
src
IBias
Figure 3.11. Emitter follower preamplier with capacitive load used to simulate dynamic distortion.
emitter follower with an ideal current source and capacitive load. Computer simulations assessed the dynamic performance of this topology for various values of input amplitude and frequency, bias current, and load capacitance. Inspection of the resulting data (plotted in gure 3.12) reveals the following empirical relationship between total harmonic distortion (THD) and the various circuit parameters.
THD = 40 log
f in C Load + 20 log A 18dB I Bias
(3.36)
A theoretical basis can be found for this expression as follows. At the quiescent operating point the
. This statement is only true for frequencies which are signicant relative to the time-constants of the circuit under consideration. The term dynamic in this context, therefore, implies operation at such frequencies. . THD is taken to be the sum of the output power from all harmonics divided by the output power in the fundamental and is usually expressed in decibels.
135
-40 -50 THD (dB) -60 -70 -80 -90 -100 0.1
I Bias = 1mA f in = 50MHz
A = 500mV
C Load = 0.1pF A = 250mV f in = 50MHz C Load = 1pF
A = 50mV
1 Load Capacitance (pF) 10 0.1 1 Bias Current (mA) 10
-40 -50 THD (dB) -60
I Bias = 1mA f in = 50MHz 10pF
I Bias = 1mA A = 256mV
-70 -80 -90 -100 0.01
C Load = 1pF
C Load = 1pF
0.1 Amplitude (Volts) 1 10
C Load = 0.1pF
100 Frequency (MHz) 1000
Figure 3.12.
Simulated THD of the emitter follower preamplier with capacitive load versus load capacitance, C Load , bias current, I Bias , amplitude,
A , and input frequency, f in . In each case, the parameter is varied in a 1, 2, 5,

10 pattern which approximates exponential spacing (i.e. each value is about twice the previous one) while maintaining integer values. input and output voltages are related by
V out = V in V BE
Q Q
(3.37)
where the Q subscript denotes the quiescent value. At any other operating point the more general relationship holds:
V out = V in V BE
(3.38)
136
Subtracting equation 3.37 from equation 3.38 gives
V out = V in V BE
(3.39)
where V is the incremental value of V ; that is, its change from the quiescent condition. Expressing V BE in terms of the transistor current gives
IC V out = V in V T ln I CQ = V in V T ln I CQ + I C I CQ
(3.40)
V out Z L = V in V T ln 1 + IC Q
where Z L is the load impedance at the output of the emitter follower. By dening the parameter V B = I C Z L = I Bias Z L this expression further simplies to
Q
V out V out = V in V T ln 1 + VB
For clarity the V terms can be replaced by V giving
(3.41)
V out V out = V in V T ln 1 + VB
This expression can be expanded through use of the identity
(3.42)
1 2 1 3 1 4 ln ( 1 + x ) = x x + x x + 3 4 2
to give
(3.43)
V out = V in V T
V out 1 V out 1 V out + 2 VB 3 VB VB
(3.44)

or after rearrangement
137
V in
VT 1 V out 1 V out = 1+ V out + V T + 2 VB 3 VB VB
(3.45)
This relation expresses V in as nonlinear function of V out . To express V out in terms of V in series inversion is performed with the following useful formulae.
if then where
y = a1 x + a2 x + a3 x + x = A1 y + A2 y + A3 y + A1 = A3 = A4 = 1 a1 1
5 a1 2 2 3
A2 =
a2 a1
3
(3.46)
( 2a 2 a 1 a 3 ) ( 5a 1 a 2 a 3 a 1 a 4 5a 2 )
2 3
1
7 a1
This procedure gives

3 V 1 1 1 T 2 = ( V + )V + ( ) 1 + V T V B in 1 + V T V B 2 V 2 in B 5 ( V 2V V ) 1 1 T T B 3 + ( V in + ) 4 1 + VT VB 6 V B 2
V out
(3.47)
which upon rearrangement becomes

3 V 1 1 1 B 2 V + ) V in + ( ) 1 + VT VB 1 + V B V T 2 V 2 in T 5 2
V out = (
1 1 ( V B V T 2V B ) 3 + ( V in + ) 4 1 + VB VT 6 V
T
(3.48)
This polynomial expansion of V out as a function of V in can be related to harmonic distortion by
138
making the following observations. If y can be expressed as a polynomial expansion in x
y = a0 + a1 x + a2 x + a3 x +
and x is a sinusoidal function of time, x ( t ) = A sin ( t ) , then y can be expanded as
(3.49)
y ( t ) = a 0 + a 1 A sin ( t ) + a 2 A sin2 ( t ) + a 3 A sin3 ( t ) + = a 0 + a 1 A sin ( t ) + a 2 A + a3 A =

3
1 cos ( 2t ) + 2 3 sin ( t ) sin ( 3t ) + 4

2
(3.50)
a2 A 3 3 a0 + + ( a 1 A + a 3 A ) sin ( t ) + 4 2 a2 A a3 A cos ( 2t ) sin ( 3t ) + 2 4

2 3
The last expression in equation 3.50 can be simplied by noting that for weakly non-linear functions of the type under consideration, higher order coefcients are small compared to a 0 and a 1 . Under this assumption equation 3.50 becomes
a2 A a3 A y ( t ) a 0 + a 1 A sin ( t ) cos ( 2t ) sin ( 3t ) + 2 4
(3.51)
From this relationship, the ratio of second harmonic amplitude to the fundamental amplitude can be easily calculated in terms of the coefcients of the original polynomial expansion:
HD 2 =
amplitudeof2ndharmonic amplitudeoffundamental = 1 a2 A 2 a1
a2 A 2 = a1 A
(3.52)

similarly
139
HD 3 =
amplitudeof3rdharmonic amplitudeoffundamental = 1 a3 2 A 4 a1
a3 A 4 = a1 A
(3.53)
Higher order distortion products, HD n , can be found in like manner. Using the coefcients for the polynomial expansion of V out from equation 3.48 in the expressions for HD 2 and HD 3 gives
1 ( 1 2 ) VB VT HD 2 = ( 1 + VT VB ) A 2 (1 + V V ) 3 B T 1 A = 4V T ( 1 + V V ) 2 B T
and
(3.54)
1 1 6 ( V B V T 2V B ) ( 1 V T ) 2 HD 3 = ( 1 + VT VB ) A 5 4 (1 + V V )
B T
1
2
( 1 2V B V T )
4
(3.55)
24V T ( 1 + V B V T )
These distortion products can be calculated in terms of circuit parameters by noting that V B V T and recalling that V B = I Bias Z L . With capacitive loading V B = I Bias ( in C Load ) . Therefore,
HD 2 =
VT A 1 A 4V T ( 1 + V V ) 2 4 V 2 B T B
2
V T in C Load = A 4 I Bias f in C Load = VT A I Bias

2 2
(3.56)
140
or in decibels
HD 2 = 40 log
f in C Load + 20 log A + 20 log ( 2 V T ) dB I Bias
f in C Load = 40 log + 20 log A 11.8dB I Bias
(3.57)
Note that this expression is identical in form to that in equation 3.36 which empirically predicted THD based upon computer simulations. The sole discrepancy between the two is a 6 dB constant term which arises because the amplitude, A, in equation 3.36 refers to the applied signal which is attenuated by 6 dB before reaching the input to the emitter follower. Therefore, equation 3.57 accurately predicts dynamic distortion for a capacitively loaded emitter follower. Further, since the empirical THD matches the theoretical HD 2 , total distortion is dominated by the second order component which can be largely cancelled if a differential structure is used. The third-order distortion can be calculated easily as well.
HD 3 =
1
2
( 1 2V B V T )
24V T ( 1 + V B V T )
A 4
3
VT 1 2 A 12 V 3
B
V T in C Load 2 HD 3 A 12 I Bias 2 V T f in C Load 3 2 = A 3 I Bias

and in decibels
3
(3.58)
2 V T f in C Load + 40 log A + 20 log dB HD 3 = 60 log 3 I Bias f in C Load = 60 log + 40 log A 5.4dB I Bias
(3.59)
The above simple expressions for HD2 and HD3 can be used to design a T/H input preamplier which meets distortion specications while dissipating minimum power. Normally, complicated mathematical techniques such as Volterra series must be employed to predict dynamic distortion
141
requiring extensive analysis and simulation while affording little design insight. The method used above accurately extends from the simpler DC case to predict high-frequency distortion characteristics because one dominant storage element of constant value (in this case the hold capacitor) inuences circuit behavior at frequencies well below those where the intrinsic device capacitances become important. This technique would not accurately predict performance in RF systems where the non-linear device capacitances are important at frequencies of interest.
3.2.4 Diode Bridge TrackMode Distortion

Two phenomena adversely affect linearity of the diode bridge itself. Firstly, the nite impedances with which the bridge must inevitably be biased cause the quiescent current to vary with input signal, and secondly, the dynamic current which charges the hold capacitor enabling the output signal to track the input also perturbs the bridge operating point in a signal-dependent manner. These effects will be discussed separately. In an ideal biasing arrangement, such as that depicted in gure 3.4, perfect sources supply the operating current to the diode bridge. In actual implementations, circuit elements with nite impedance will drive the top and bottom nodes of the bridge. These impedances allow signal current to ow through and perturb balance of the bridge diodes in response to voltage variations at the bridge input. A large-signal model of the diode bridge in track mode including nite biasing impedances (Fig. 3.13) shows the relationships among these quantities. Here an approximation has been made that the incremental voltage seen at the top and bottom of the bridge is equal to the incremental input voltage. Using the result from section 3.1 that I D1 I D3 = I D2 I D4 (Eq. 3.5), the diode currents can be related as follows:
V in I Bias V in I Bias I Bias I Bias + I + I + = ( I ) ( I ) 2 2 ZB 2 ZB 2

This equation expands to give
(3.60)
I Bias I Bias V in = ( ( + I ) I ) 2 2 ZB
(3.61)
142
ZB I Bias I Bias V in + I 2 ZB V in ZB
ZB I Bias V in ZB
I Bias I 2 D1 D2 I Bias I 2 V out + V out
V in + V in 2V in Z B I Bias V in + I + 2 ZB
D3 D4
2I Bias
Figure 3.13. Large-signal model of diode bridge in track mode with nite bias impedances, Z B .
which can be solved for I I Bias .
I Bias I Bias V in = ( ( + I ) I ) 2 2 ZB I Bias I Bias V in ( + I ) ( I ) = 2 2 ZB 2I Bias I = I I Bias V in ZB

2 2 2 2
(3.62)
1 V in 1 V in = = 2 I Bias Z B 2 VB
where V B = I Bias Z L . At the quiescent point the output voltage can be expressed as the sum of the

input voltage and two diode voltage drops which are known functions of the diode currents.
143
V out V in = V BE4 V BE3

Q Q Q
(3.63)
At any other operating point the more general expression can be written:
V out V in = V BE4 V BE3
(3.64)
Subtracting these two equations (and using V = V Q + V ) gives the relationship between the incremental variables
V out V in = V BE4 V BE3 = V T ln = V T ln = V T ln I Bias 2 I I Bias 2 + I + V in Z B V T ln I Bias 2 I Bias 2 I Bias 2 I I Bias 2 + I + V in Z B 1 2I I Bias 1 + 2I I Bias + 2V in V B
2
(3.65)
Using the result of equation 3.62, 2I I Bias = ( V in V B ) , and dropping the notation for simplicity gives
1 ( V in V B ) V out V in = V T ln 2 1 + ( V V ) + 2V V in B in B = V T ln = V T ln ( 1 + V in V B ) ( 1 V in V B ) ( 1 + V in V B ) ( 1 + V in V B ) ( 1 V in V B ) ( 1 + V in V B )
(3.66)
Again, the polynomial expansion of ln ( 1 + x ) can be employed advantageously to express V out
144
as a polynomial function of V in .
V out = V in + V T VT = V in 2V T
1 V in 1 V in V in 1 V in + + 3 VB 4 VB VB 2 VB 1 V in 1 V in V in 1 V in + + 4 VB 3 VB VB 2 VB 1 V in V in 1 V in + + + 5 VB VB 3 VB
3 5 3 5 2 3 4
(3.67)
2V T 1 V in 1 V in = 1 + + V in 2V T 5 VB 3 VB VB
The absence of even-order components in the last expression in equation 3.67 implies that the nite impedances of the bias current sources give rise to only odd-order distortion products. The dominant 3rd-order component is
HD 3 =
1 a3 2 A 4 a1
3
1 2 3 ( VT VB ) 2 = A 4 [ 1 2V T V B ] 1 2 3 ( V T V B ) ( V B 2V T ) 2 = A 4 [ V B 2V T 1 ] 1 VB 1 2 = A 12 [ V B 2V T 1 ] 1 1 VB 2 A 12 V B 2V T = VT 1 2 A 6 V3
B 2 2 3
(3.68)
Where the approximation above assumes V B 2V T , a condition which always holds in practice, and the sign of the result can be ignored since only relative amplitudes are of interest. Recalling that
145
V B = I Bias Z B , the distortion becomes

3 VT 1 2 HD 3 = ( ) A 6 I Bias Z B
(3.69)
or in decibels
HD 3 = 40 log A 60 log ( I Bias Z B ) + 20 log ( V T 6 ) dB = 40 log A 60 log ( I Bias Z B ) 47.26 dB
(3.70)
In most cases Z B is resistive in nature, either because it is implemented with an actual resistor connected to an appropriate voltage supply or because the active current source exhibits a small parasitic output capacitance. Therefore, odd-order distortion products due to nite current source output impedances exist even at low frequencies and must evaluated to ensure they are acceptably low. Similarly to the output impedances discussed above, nite impedance at the bridge output causes signal current to ow through the bridge, thereby modifying the quiescent currents and leading to distortion. The incremental currents owing in this situation (Fig. 3.14) again adhere to the constraint of equation 3.5 resulting in the following relationship:
I Bias I Bias I Bias I Bias + I ) ( I ) ( I + I out ) + I + I in ) = ( 2 2 2 2
(3.71)
This expression can be solved for I as follows:
I Bias I +
I Bias I Bias I in + II in = I Bias I + I out II out 2 2 I Bias 2I Bias I + I ( I in + I out ) = ( I out I in ) 2 I Bias ( I out I in ) 2 I = 2I Bias + ( I in + I out )
(3.72)
146
I Bias I Bias + I 2 D1 D2 I out CH I Bias + I + I in 2 I Bias I Bias I + I out 2 I Bias I 2
V in + V in I in
V out + V out
D3
D4
Figure 3.14. Diode bridge with current perturbations caused by dynamic current into C H .
As in the previous cases the incremental input and output voltages are simply related
V out V in = V BE1 V BE2 = V T ln = V T ln I Bias 2 + I I Bias 2 I 1 + 2I I Bias 1 2I I Bias

(3.73)
Using the expression for I found in equation 3.72 and dispensing with the cumbersome

notation the above equation becomes
147
I out I in 1 + 2I Bias + I out + I in V out V in = V T ln I out I in 1 2I +I +I

Bias out in
2I Bias + 2I out = V T ln 2I Bias + 2I in = V T ln 1 + I out I Bias 1 + I in I Bias
(3.74)
Performing KCL on a closed surface enclosing all four bridge diodes leads to the conclusion that
I in = I out . Note also that I out in turn is constrained by the impedance connected between the
bridge output and ground, temporarily called Z L , to be V out Z L ; that is, I out = V out Z L . Therefore, equation 3.74 produces
V out V in = V T ln
1 V out V B 1 + V out V B
(3.75)
where V B = I Bias Z L . The right hand side of equation 3.75 is identical in form to the right hand side of equation 3.66 and therefore admits the same polynomial expansion arrived at in equation 3.67. The resulting relationship is
V out V in = V T ln
1 V out V B 1 + V out V B 1 V out V out 1 V out + + + 5 VB VB 3 VB

3 5
(3.76)
= 2V T
which upon rearrangement expresses V in as a polynomial function of V out
V in = V out + 2V T
1 V out V out 1 V out + + + 5 VB VB 3 VB
(3.77)
This equation can be inverted to give V out in terms of V in using the series inversion formulae
148
described earlier (Eq. 3.46).

4 V 1 1 2 T 3 = ( V ) V in ( ) 1 + 2V T V B 1 + 2V T V B 3 V 3 in B
V out
(3.78)
Since V out contains no even-order powers of V in , no even-order harmonics are generated from the bridge due to output current ow. The dominant odd-order harmonic, the third, is (3.79)
4 V 1 2 T ( ) 1 + 2V T V B 3 V 3 1 B 2 A HD 3 = 4 1 ( ) 1 + 2V T V B 3 V 1 1 2 T 2 = ( A ) 4 1 + 2V T V B 3 V 3 B
HD 3
1 VT 2 A 6 V3
B
where the approximation relies upon V B V T which usually holds in practical implementations. Substituting I Bias ( in C H ) for V B yields
V T in C H 2 HD 3 = A 6 I Bias 43 V T f in C H 3 2 = A 3 I Bias
(3.80)

or in decibels
3 4 V T f in C H HD 3 = 60 log + 40 log A + 20 log dB 3 I Bias
149
(3.81)
f in C H = 60 log + 40 log A + 0.6dB I Bias
3.2.5 Finite Aperture Time

Ideally, the track-to-hold transition occurs instantaneously at the sampling moment implying that the bridge diodes are switched from the conducting state to the non-conducting state spending no time in any intervening partially conducting mode. In a real T/H, such a discontinuity is impossible, and the bridge diodes spend some nite time in transition between these conditions. Two signicant effects arise from the non-zero transition or aperture time. First, high-frequency signals are attenuated because the resultant output signal is averaged during the aperture window. This averaging operation is linear but acts as a low-pass lter imposing a limit on the frequency response of the bridge. Second, the time-varying nonlinear impedance of the diode bridge introduces distortion into the held signal. These two effects will be discussed separately. Ignoring the nonlinear aspects of the switching process, the diode bridge can be modelled as a time-varying linear resistor, r d ( t ) , which charges the hold capacitor, C H (Fig. 3.15). If the
rd ( t) V in ( t ) CH V out ( t )
Figure 3.15. Linear, time-varying model of diode bridge and hold capacitor
used for nite aperture analysis.
bridge bias currents (Fig. 3.4) switch linearly from their nominal values, I o , to 0 over an aperture
150
time t A (Fig. 3.16a), the bridge resistance will increase from its nominal value to innity over the
I(t) IO
rd(t)
Aperture Time
tA
2V T IO 0
(b)
tA
(a) Figure 3.16.
Response of bridge current (a) and small-signal bridge resistance (b) over nite aperture time.
same period (Fig. 3.16b). The bridge current and small-signal resistance can be described analytically as:
I Bridge ( t ) = I o ( 1 t t A )
and
(3.82)
rd ( t ) =
2V T 2V T = I Bridge ( t ) Io ( 1 t tA )
(3.83)
Alternatively, the bridge can be described by its conductance which is
g Bridge ( t ) =
I Bridge ( t ) Io ( 1 t tA ) = 2V T 2V T
(3.84)
This function is not plotted but is a scaled version of the bridge current, I Bridge ( t ) , shown in gure 3.16a. The differential equation which governs the bridge turn-off behavior can be derived by

applying KCL to the output node of the RC circuit shown in gure 3.15 giving
151
V in ( t ) V out ( t ) = C H d V out ( t ) dt rd ( t)
which upon rearrangement results in
(3.85)
dV out ( t ) 1 1 + V out ( t ) = V ( t) r d ( t ) C H in dt rd ( t ) CH
(3.86)
The above relationship is a linear time-varying differential equation whose time-varying aspect is reected by the coefcients r d ( t ) C H which are not constant but which change according to the diode small-signal resistance, r d ( t ) . These time-constants can be parameterized by their value at time t = 0 which is o = ( 2V T I o ) C H and which is the reciprocal of the bridge 3 dB radian bandwidth during track mode:
track = 3dB =
Io 1 = o 2V T C H
(3.87)
Equation 3.86, along with the constraint on bridge resistance, r d ( t ) = 2V T [ I o ( 1 t t A ) ] , can be solved numerically for an input sinusoid of given frequency and phase,
V in ( t ) = A sin ( in t + ) , yielding an output voltage at t = which represents the held

signal corresponding to the sample at the relative phase between the input sinusoid and the sampling clock. By performing this analysis for several equally-spaced phases along the input waveform a set of output voltages representing a sampled sinusoid results. The Fourier transform of this sampled signal gives the output amplitude and phase at frequency in . Assembling these results for many values of in , the frequency response of the system is found. Figure 3.17 displays the results of such analysis compared with the simple single-pole frequency response of the bridge in track mode for several values of the normalized parameter track t A . The frequency response curves including the effects of nite aperture time follow closely the single-pole response until
f t A 1 5 ; that is, until the aperture time is one fth the period of the input signal. Beyond this
frequency the sampling gain drops rapidly exhibiting a null at f t A = 1 which appears because the input sinusoid is integrated over exactly one period ( t A = 1 f = T ). Additional nulls exist whenever f t A equals an integer value, since the input signal is then integrated over an integer number of periods thereby generating output equal to zero. Figure 3.17 shows that for reasonable
152
-20
Magnitude (dB)
-40 Track * tA = 1/32 1/16 1/8 1/4 -60
-80 .01
.1 f * tA
10
Figure 3.17. Frequency response induced by nite aperture time assuming a linear small-signal bridge model. Upper curves represent frequency response with constant bridge resistance, r d ( t ) = r d = 2V T I o . Lower curves include
the effect of bridge turn-off governed by r d ( t ) = 2V T [ I o ( 1 t t A ) ] . frequency response the following conditions must prevail:
tA <
1 10f in
(3.88)
and
track in = 2 f in
(3.89)
where f in is the desired operating frequency of the track-and-hold. track must be much larger than
2 f in , otherwise signicant attenuation occurs (even in track mode) since at track = 2 f in

signal attenuation is unacceptable (3 dB). For a desired operating frequency, f in , equal to 50 MHz, equations 3.88 and 3.89 mandate that t A 2ns and f track 50MHz 500MHz . The rst of
153
these constraints generally does not pose a difcult problem for a modern silicon bipolar process like Tektronix SHPi. The second constraint places a lower limit on the bridge bias current required for a given value of hold capacitance, C H . That is,
track =
Io 1 = f o 2V T C H in I o 2V T C H f in
(3.90)
In the preceding analysis, a simple ramp was assumed for the bridge current waveform; however, the exact form of the turn-off mechanism is not critical so that if different switching characteristics are used (e.g. exponential decay rather than linear decay of the bridge current) qualitatively similar results obtain. The nonlinear effects of nite aperture time are more deleterious than the simple bandlimiting phenomenon just described [6], [7], [15], [16]. The large-signal behavior of a diode bridge during the turn-off transient can be analyzed with the aid of equations 3.14 and 3.15 from section 3.1 which apply to gure 3.18a. These equations predict the bridge transfer characteristics during
I(t) I(t) CHdVout dt Vout(t) CH 0 I(t)

(a)
IO
Vin(t)
Aperture Time
tA
(b)
Figure 3.18. Large-signal model for simulating nite aperture effects.
track mode and are repeated here:
154
I in = I Bias tanh
V in V out 2V T
and I out = I in
(3.91)
When combined, the two lines in equation 3.91 predict the output current as a non-linear function of the input and output voltages. (By the associated reference convention both I in and I out are assumed to ow into the diode bridge in gure 3.18a.)
I out = I Bias tanh
V in V out 2V T
(3.92)
The output current is further constrained by the hold capacitor to be
I out = C H
Equations 3.92 and 3.93 combine to give
dV out dt
(3.93)
dV out(t) I Bias V in(t) V out(t) = tanh CH dt 2V T
(3.94)
Since I Bias is not constant but decreases from I o to 0 over the aperture time, t A , according to I Bias = I o ( 1 t t A ) (Fig. 3.18b), equation 3.94 becomes
dV out(t) Io V in(t) V out(t) = tanh ( 1 t tA) CH dt 2V T
(3.95)
which is the non-linear, time-varying differential equation governing bridge turn-off with nite aperture time and a linearly ramped current decay. This equation depends explicitly on the aperture time, t A , and the bridge slew-rate, I o C H ; and implicitly upon the input sinusoid amplitude, A , and frequency, f in (through the denition of V in ( t ) assumed here to be a sinusoid). Intuitively, the nonlinear nature of the bridge gives rise to distortion because in the presence of a non-zero hold capacitor, the bridge output voltage will not equal the bridge input. The bridge output current is a nonlinear function of this voltage difference and integrates on the hold capacitor resulting in a held voltage which is a nonlinear function of the input signal. This phenomenon (described in section
155
3.2.4 with reference to gure 3.14) is further exacerbated by the diminution of the bridge bias current over the aperture window. Equation 3.95 describes both of these effects and can be solved numerically for input sinusoids of various phases and frequencies (as in the case above where the band-limiting effects of nite aperture time were investigated). Fourier transforms calculate the harmonic content of the resultant sampled output waveforms from which total-harmonic-distortion (THD) can be easily ascertained. Results from such analysis agreed very closely with those obtained via SPICE circuit analysis and are plotted in gure 3.19 as functions of the circuit parameters mentioned above; t A , B slew = I o C H , A , and f in . The THD curves in gure 3.19 can be seen empirically to follow the relationship
THD = [ 40 log A + 60 log f in + 30 log t A 30 log ( I o C H ) + 30 ] dB
(3.96)
within a few decibels over all regions of interest. This expression rearranges giving a form containing normalized parameters:
THD =
40 log A + 60 log ( f in t A ) + 30 log
Io t + 30 dB CH A
(3.97)
Equations 3.96 and 3.97 can be used as guides when designing diode bridge switches and selecting circuit parameters which govern bridge operation.
3.2.6 Hold Pedestal

While the bridge diodes are conducting during track mode, they store charge on both their depletion capacitance and their diffusion capacitance. After the bridge switches to hold mode and all transients settle, the bridge diodes conduct no current with their terminal voltages determined by a mechanism dependent upon the particular implementation of the switch. Regardless of the particular diode terminal voltages in this state, reduced charge is stored on the depletion capacitance, and the diffusion storage is zero. The difference in charge stored during track mode and hold mode is therefore expelled from each diode during the turn-off transient. If the charges expelled from the two diodes connected to the hold capacitor are not equal, the net charge injected onto that capacitor imparts an output voltage perturbation called hold step or hold pedestal which,
. The diodes can still conduct a small displacement current owing to their non-zero junction capacitance. This effect is ignored here but will be discussed in section 3.2.7 which addresses bridge feedthrough in hold mode.
156
-40 -50 THD (dB) -60 -70 -80 -90 -100 .01 -40 -50 THD (dB) -60 -70 -80 -90 -100 .01 -40 -50 THD (dB) -60 -70 -80 -90 -100 .1 Amplitude (Volts)
0.01 ( I 0 C H ) t A = 0.1 ( I 0 C H ) t A = 0.1 ( I0 CH) tA = 1 1 f in t A = 0.01 0.1 A = 0.1 A = 1
A = 0.256
f in t A = 0.025
.1 Bslew * ta (Volts)
A = 0.256
1 .01
.1 Bslew * ta (Volts)
A = 1 A = 0.1
.1 fin * ta
1 .01
.1 fin * ta
f in t A = 0.025
( I0 CH) tA = 1 f in t A = 0.1
.1 Amplitude (Volts)
Figure 3.19. Simulated THD due to nite aperture time as a function of input amplitude, A , input frequency, f in , aperture time, t A , and bridge slew rate, I 0 C H . Parameters are swept in a 1, 2, 5, 10 fashion to approximate an
exponential sweep with integer values. if non-linearly dependent upon the input signal, introduces distortion into the sampled output stream. This distortion mechanism can be analyzed by determining the diode operating voltages
157
before and after the track-to-hold transition. In a typical embodiment (Fig. 3.20a), the diode bridge
Cj D1 Vin D3 D4 D2 Vout 3 CH
-Vd -Vout -Vd -Vd +Vout
1 2
Cjo 0
+Vd
(a) Figure 3.20.
(b)
Charge injection at bridge turn-off gives rise to hold pedestal distortion. (a) Typical bridge circuit showing auxiliary diodes which control bridge bias voltages in hold mode. (b) Diode small-signal capacitance-voltage characteristic.
is turned off by reversing the polarity of the bias current, thereby forcing this current to ow through two auxiliary diodes which in turn reverse bias the bridge diodes. While tracking, diodes D1 through D4 conduct nominally equal currents corresponding to the bias voltage + V d (point 1 on the diode small-signal depletion capacitance curve of gure 3.20b). During hold mode the bridge current forward biases the two auxiliary diodes which now control the upper and lower bridge node voltages. If the auxiliary diodes have twice the area as the bridge diodes, then the upper bridge node moves to V d Volts and the lower bridge node to + V d Volts. Therefore, the voltage across D4 becomes V out V d while D2 sees V d V out Volts (gure 3.20b points 2 and 3 respectively). Notice that in the implementation depicted in gure 3.20a the maximum allowable input amplitude is V d . If the input signal exceeds this value, diodes D1 and D3 will become at least slightly forward biased severely reducing the isolation provided by the bridge in the hold mode. If larger signal
. This constraint ensures that the auxiliary diodes operate at the same current density in hold mode as do the bridge diodes in track mode. Without this restriction, the auxiliary diodes forward bias potential will be lower than bridge diodes by V T ln2 Volts. This difference does not materially affect the analysis or results presented here. In fact, the auxiliary diodes are usually made larger than the bridge diodes for another reason to reduce parasitic resistance which increases feedthrough during hold mode.
158
swings are required, multiple diodes in series can replace each auxiliary diode. Since the diode capacitance-voltage characteristic is a small-signal quantity, the difference in stored charge at two operating points can be calculated by integrating the C-V function between the voltages of interest.
dQ dV dQ = C j ( V ) dV Cj ( V )
V2 Q2
Q1
dQ = Cj ( V ) dV
V1 V2
(3.98)
Q = Q 2 Q 1 =
V1
Cj ( V ) dV
Therefore, the net charge injected onto the hold capacitor which is the difference between the charges injected by diodes D1 and D4 can be expressed as
Q inj = Q D4 Q D2
V d + V out V d V out
Vd V d + V out
C j4 ( V ) dV
Vd
C j2 ( V ) dV
(3.99)
V d V out
C j ( V ) dV
where
the
C-V
curves
of
diodes
D2
and
D4
are
assumed
identical,
i.e.
C j2 ( V ) = C j4 ( V ) = C j ( V ) . The last integral in equation 3.99 represents the shaded area

under the C-V curve in gure 3.20b. The diode diffusion capacitance does not contribute to Q inj because the stored diffusion charge due to diodes D2 and D4 is nominally equal and will therefore sum to zero at the output node. Any small differences in this charge due to device mismatches result in a signal independent pedestal which disturbs every output sample and therefore appears as an offset component of the T/H circuit. In the absence of other error sources, the injected charge, Q inj ,

will prevent the held output from equalling the input according to
159
V out = V in
Q inj CH
(3.100)
so that the input signal can be expressed as a function of the output signal:
V in = V out +
Q inj CH
1 = V out + CH
C j ( V ) dV
(3.101)
Notice that V in is a purely odd function of V out regardless of the nature of C j ( V ) since
1 V in ( V out ) = V out + CH 1 = V out CH = V in ( V out )
V d V out V d + V out
C j ( V ) dV

(3.102)
C j ( V ) dV
Therefore, by inspection of the formulae for series inversion (Eq. 3.46), V out will also be an odd function of V in and only odd-order harmonics can arise from the hold pedestal phenomenon. This claim is invalid if component mismatches are encountered such that C j2 ( V ) C j4 ( V ) . Nonetheless, reasonable component matching should minimize even-order distortion products.
V in can be expressed as a polynomial function of V out by forming the Taylor series

expansion of the relationship found in equation 3.101. That is,
V in = a 1 V out + a 2 V out + a 3 V out + where 1 d V (V ) an = n! d V n in out

out n V out = 0
(3.103)
160
a 1 can be found directly from equations 3.101 and 3.103 by recalling Leibnitz Rule: if
b(x)
(x) =
a(x)
f(t, x) dt
(3.104)
then
b(x)
d (x) = dx
a(x)
f(t, x) dt + f [ b(x), x ] d b(x) f [ a(x), x ] d a(x) dx x dx
Applying Leibnitz Rule to equation 3.101 gives

dV in 1 = 1+ CH d V out + = 1+
d C(V) dV + d V out
(3.105)
1 [ C( V d + V out) ( 1 ) C( V d V out) ( 1 ) ] CH
1 [ C( V d + V out) + C( V d V out) ] CH
So that
a1 =
dV in d V out
= 1+
V out = 0
1 [ C( V d) + C( V d) ] CH
(3.106)
C( V d) = 1+2 CH

The higher order derivatives can be found in a straightforward manner.
161
d V in d V out
n
( n 1) ( n 1) 1 d d C( V d + V out) + C( V d V out) ( n 1) CH d V ( n 1) d V out out ( n 1) n1
C( V d + V out) d ( V d + V out ) 1 d = CH d ( V + V ) ( n 1) dV out d out

( n 1)
+
n1
C( V d V out) d ( V d V out ) 1 d + CH d ( V V ) ( n 1) dV out d out

( n 1) ( n 1)
(3.107)
C( V d + V out) d C( V d V out) 1 d n1 n1 = ( 1) + ( 1 ) ( n 1) ( n 1) CH d ( V + V ) d ( V d V out ) d out 0 forneven ( n 1) C( V d + V out) = 2 d fornodd CH d ( V + V ) ( n 1) d out

All even coefcients of the polynomial expansion of V in are therefore zero as noted earlier, and the odd coefcients become
an =
1 dn V (V ) n! d V n in out
out ( n 1)
V out = 0
C( V d + V out) 1 2 d = n! C H d ( V + V ) ( n 1 ) d out C(V) 1 2 d = ( n 1) n! C H dV

( n 1)
(3.108)
V out = 0
V = Vd
If the diode small-signal capacitance can be described by C j(V) where
Cj ( V) =
dQ = dV
C jo V (1 ) V BI
m
(3.109)
162
where C jo is the zero-bias capacitance, V BI is the built-in potential usually near 0.7 Volts, and m is a factor equal to about 1/2 which depends upon the junction doping prole, then the odd coefcients can be expressed as:
C(V) 1 2 d an = n! C H d ( V ) ( n 1 ) = =
( n 1)
V = Vd
1 2 C jo m ( m + 1 ) ( m + n 2 ) n1 m+n1 n! C H ( 1 + V d V BI ) V BI 1 2 C jo (m + n 1) 1 n1 m+n1 (m) n! C H V BI ( 1 + V d V BI )
(3.110)
where (x) is the Gamma or generalized factorial function. With the coefcients known for the polynomial expansion of V in in terms of V out , the series can be inverted using the formulae listed in equation 3.46 to give
V out = A 1 V in + A 2 V in + A 3 V in +
where
(3.111)
A1 =
1 = a1
1 1 = C jo C( V d) 1 1+2 1+2 CH ( 1 + V V ) m CH d BI
(3.112)
and
A3 =
2a 2 a 1 a 3 a1
5
a3 a1
(3.113)
4
1 C jo m ( m + 1 ) 1 2 m+2 3 CH V BI ( 1 + V d V BI ) C jo 1 1+2 CH ( 1 + V V ) m d BI
4
The expressions for A 1 and A 3 can be used to calculate the gain and third harmonic distortion

component due to hold pedestal. If V d V BI , simplications in the resulting equations arise.
163
AV = A1 =
1 C jo 1 1+2 CH ( 1 + V V ) m d BI 1 C jo ( 1 m ) 1+ 2 CH C jo ( 1 m ) 2 CH
(3.114)
where the last expression is based upon the binomial expansion and the assumption that
C H C jo 2
( 1 m)
which is well founded in practical circuits since m is a constant near 1/2 and C H
is usually more than an order of magnitude greater than C jo .
HD 3 =
1 A3 2 A 4 A1
1 1 C jo m ( m + 1 ) 2 m+2 3 CH V BI ( 1 + V d V BI ) 1 2 = A 3 4 C jo 1 1+2 CH ( 1 + V V ) m d BI C jo m ( m + 1 ) 1 2 m+2 C 2 V BI 1 H 2 HD 3 A 3 12 C jo ( 1 m ) 1+ 2 CH 1 12 C jo m ( m + 1 ) 1 A2 C H 2m + 2 V 2 BI
(3.115)
If m is assumed to equal 1/2, and V BI is 750mV (3/4 V) then the equations for gain and third order distortion further simplify to
AV = 1 2
C jo CH
(3.116)
164 and
HD 3 =
1 C jo 2 A 36 2 C H
(3.117)
or in decibels
C jo C jo A V = 20 log 1 2 = 20ln 1 2 ln 10dB CH CH C jo 20 2 dB ln 10 CH C jo dB CH

(3.118)
12.3
and
HD 3 = 40 log A + 20 log
1 C jo + 20 log ( ) dB CH 36 2
C jo = 40 log A + 20 log 34.1 dB CH
(3.119)
The accuracy of this analysis is demonstrated in gure 3.21 which plots gain and HD 3 as calculated analytically and as predicted by SPICE. The top plot in the gure compares SPICE results with those obtained by included many higher-order terms in the polynomial expansion and series inversion of equation 3.101, while the bottom plot uses the simpler approximations from equations 3.114 and 3.115. Note that in all cases the predicted performance is within a few decibels of the simulated result, thereby ensuring fast but accurate prediction of distortion due to the hold jump phenomenon. If excessive distortion or gain loss results from hold pedestal, a unity-gain amplier driving the bridge center tap from the output node (Fig. 3.22a) can reduce the effects to a possibly acceptable level [15], [16], [10]. Analysis of hold pedestal with feedback proceeds as in the case without feedback with the modication that the center-tap voltage is no longer grounded but is assumed to be a function of the output voltage. In this case, diodes D2 and D4 switch between the
165
T/H Harmonics Due to Hold Jump (SPICE & Analysis) 0 Av -20
-40
-60
dBc
HD3 -80
-100 HD5
-120
-140 0.1
0.15
0.2
0.25
0.3 Cjo/Ch
0.35
0.4
0.45
0.5
T/H Harmonics Due to Hold Jump (SPICE & Approximations) 0 Av -10 -20 -30 Approximation SPICE
dBc
-40 -50 -60 HD3 -70 -80 0.1 Approximation SPICE 0.15 0.2 0.25 0.3 Cjo/Ch 0.35 0.4 0.45 0.5
Figure 3.21. Comparison between distortion due to hold pedestal predicted

by analysis and simulation (upper); and between distortion predicted by simple approximations and simulation (lower). track mode with each biased at + V d , and hold mode where D2 is biased at ( V CT V d ) V out Volts and D4 at V out ( V CT + V d ) Volts. The feedback amplier is assumed for simplicity to be memoryless with a linear transfer function described by its output-referred offset, V off , and its gain,
, which is ideally unity. Therefore, V CT = V off + V out , and the diode voltages in hold mode
become V D2 = V d + V off ( 1 ) V out and V D4 = V d V off + ( 1 ) V out as shown in gure 3.22b. The equation governing the pedestal (analogous to equation 3.101) is therefore
166
Cj 1 D1 Vin D3 D4 D2
AV
Vout CH
Cjo 0
+Vd
-Vd -Vd -Vout (1-A V ) -Vd +Vout (1-A V )
(a) Figure 3.22.
(b)
A bootstrapped bridge center-tap reduces hold pedestal distortion. (a) Unity-gain buffer drives bridge center-tap from output node. (b) Diode C-V characteristic still determines residual charge injection.
V in = V out +
Q inj CH
V d V off + V out ( 1 ) V d + V off V out ( 1 )
1 = V out + CH
C j ( V ) dV
(3.120)
This equation can be slightly modied to attain the same form as equation 3.101 so that the coefcients of the Taylor series expansion, found for the case of a grounded center tap node, can be applied directly to the present case.
V d V off + V out ( 1 ) V d + V off V out ( 1 )
1 V in = V out + CH V in V out V off
C j ( V ) dV
C j ( V ) dV
(3.121)
1 = V out V out V off + CH 1 CH
V d V off + V out ( 1 ) V d + V off V out ( 1 ) V d V off + V out ( 1 ) V d + V off V out ( 1 )
V in V out V off = V out ( 1 ) V off + 1 = Vx + CH

Vd + Vx Vd Vx
C j ( V ) dV
C j ( V ) dV
167
where V x = V out ( 1 ) V off and the right hand side of the last equation in 3.121 is identical in form to equation 3.101. Since the coefcients, a n , of the Taylor series expansion of this form are known (Eqs. 3.106 and 3.108), The expansion in terms of V x can be written immediately:
V in V out V off = a 1 V x + a 2 V x + a 3 V x +
(3.122)
( n 1)
C j( V d) = 1+2 V + CH x
n=3 nodd
C j(V) 1 2 d n! C ( n 1) H dV
n Vx V = Vd
If V off is negligibly small, then V x becomes V out ( 1 ) and 3.122 can be written
V in V out
C j( V d) = 1+2 V + CH x
n=3 nodd
C j(V) 1 2 d n! C ( n 1) H dV
( n 1)
n Vx V = Vd
C j( V d) 1+2 ( 1 ) V out + CH +
n=3 nodd
C j(V) 1 2 d n! C ( n 1) H dV
( n 1)
n [ ( 1 ) V out ] V = Vd
(3.123)
C j( V d) V in = 1 + 2 ( 1 ) V + C H out +
n=3 nodd
C j(V) 1 2 ( 1 ) n d n! ( n 1) CH dV
( n 1)
n V out V = Vd
So the Taylor series coefcients for the expansion of V in as a function of V out are
a1 = 1 + 2 ( 1 ) 1 2 ( 1 ) an = n! CH
n
C j( V d) CH n3 nodd
(3.124)
( n 1)
C j(V)
V = Vd
dV
( n 1)
168
If the diode capacitance-voltage relationship, C j(V) , is described by equation 3.109, then the coefcients become
a1 = 1 + 2 ( 1 )
C jo 1 CH ( 1 + V V ) m d BI
n
( 1 ) 2 C jo (m + n 1) 1 an = n1 m+n1 n! C H (m) V BI ( 1 + V d V BI )
n3 nodd
(3.125)
With the coefcients known for the polynomial expansion of V in in terms of V out , the series can be inverted using the formulae listed in equation 3.46 to give
V out = A 1 V in + A 2 V in + A 3 V in +
where
(3.126)
A1 =
1 = a1
1 C jo 1 1 + 2 ( 1 ) CH ( 1 + V V ) m d BI
(3.127)
and
A3 =
2a 2 a 1 a 3 a1
5
a3 a1
3 4
( 1 ) 1 C jo m ( m + 1 ) 2 m+2 3 CH V BI ( 1 + V d V BI ) C jo 1 1 + 2 ( 1 ) CH ( 1 + V V ) m d BI
4
(3.128)
The expressions for A 1 and A 3 can be used to calculate the gain and third harmonic distortion

component due to hold pedestal. If V d V BI , simplications in the resulting equations arise.
169
AV = A1 =
1 C jo 1 1 + 2 ( 1 ) CH ( 1 + V V ) m d BI 1 C jo ( 1 m ) 1 + ( 1 ) 2 CH C jo ( 1 m ) 2 CH
(3.129)
1 ( 1 )
where the last expression is based upon the binomial expansion and the assumption that
C H ( 1 ) C jo 2
( 1 m)
which is well founded in practical circuits.
HD 3 =
1 A3 2 A 4 A1
3
( 1 ) 1 C jo m ( m + 1 ) 2 m+2 3 CH V BI ( 1 + V d V BI ) 1 2 = A 3 4 C jo 1 1 + 2 ( 1 ) CH ( 1 + V V ) m d BI C jo m ( m + 1 ) ( 1 ) 3 2 m+2 CH 2 V BI 1 + ( 1 ) C jo ( 1 m ) 2 CH
3
(3.130)
HD 3
1 12
3 1 C jo m ( m + 1 ) ( 1 ) 2 A 2 12 C H 2m + 2 V BI
If m is assumed to equal 1/2, and V BI is 750mV (3/4 V) then the equations for gain and third order distortion further simplify to
AV = 1 2 ( 1 )
C jo CH
(3.131)
170 and
HD 3 =
1 3 C jo 2 ( 1 ) A CH 36 2
(3.132)
or in decibels
C jo A V = 20 log 1 2 ( 1 ) CH C jo 20 2 ( 1 ) dB ln 10 CH C jo dB CH
(3.133)
12.3 ( 1 )
and
HD 3 = 40 log A + 20 log
1 C jo + 60 log ( 1 ) + 20 log ( ) dB CH 36 2
C jo = 40 log A + 20 log + 60 log ( 1 ) 34.1 dB CH
(3.134)
Notice that both gain loss (in dB) and third harmonic distortion are greatly reduced by the presence of the ( 1 ) term. Also, if = 1 , then A V = 0dB and HD 3 = dB as desired. If V off is not negligible but is very near unity then V x = V off and
V in V out V off = a 1 V x + a 2 V x + a 3 V x + = C j( V d) ( V off ) + 1+2 CH +
n=3 nodd
C j(V) 1 2 d n! C ( n 1) H dV
( n 1)
( n 1)
n ( V off ) V = Vd n V off V = Vd
(3.135)
V out
C j( V d) = V in + 2 V off + CH
n=3 nodd
C j(V) 1 2 d n! C ( n 1) H dV
171
In this case the held sample, V out , equals the input plus an offset term which is the indicated function of the auxiliary ampliers output offset voltage, V off . Therefore, hold pedestal with unity gain feedback to the bridge center tap results in an offset error at the bridge output but no gain error or distortion.
3.2.7 Feedthrough
When the sampling bridge is in hold mode, current is prevented by appropriate means from owing through the bridge diodes so that ideally the bridge impedance becomes innite, thereby isolating the hold capacitor from the input signal. Because of non-idealities in the bridge diodes, notably nite junction capacitance, the isolation is not complete. The extent to which the input signal affects the held output voltage in hold-mode is characterized by feedthrough which is the gain of the bridge, ideally zero, and which is usually expressed in decibels. In a typical diode bridge (shown with its concomitant switching circuitry in gure 3.23) all bias current is caused to ow in
Bridge
Bridge
D1 D6
D2
Vin
X1
VCT
D4
X1
Vout
D3
D5
I1
I2 Q2
Hold
Q1
Track
2I
Bridge
Figure 3.23.
Diode-bridge track-and-hold with differential pair controlling bridge current. Diodes D5 and D6 conduct during hold-mode while diodes D1 through D4 are cut-off.
the auxiliary diodes thereby forcing current in the bridge diodes to zero. In the example shown,
I 1 = 2I Bridge ,
I2 = 0 ,
I D5 = I D6 = I Bridge ,
and
I D1 = I D2 = I D3 = I D4 = 0 .
172
Therefore, the bridge diodes small-signal resistance, V T I D , becomes very large and the auxiliary diodes small-signal resistance becomes small. The bridge and auxiliary diodes now form a voltage divider severely attenuating signals as they pass from input to output. Because of the diode junction capacitance in parallel with the small-signal resistance this attenuation characteristic is frequency dependent. A small-signal model of the switch in hold mode (Fig. 3.24a) includes all of the
Cd r d
Cd
Vin
r d
r0
Av CH Cd
Vout
Cd
(a)
2Cd
Vin
r /2 d
VTop
2Cd
VFB r0
Av CH
Vout
(b)
Figure 3.24. Small-signal models of bridge in hold mode. (a) Model including all components. (b) Equivalent model simplied through symmetry.
signicant circuit elements necessary to analyze the nature of hold-mode behavior. Note that distortion in this mode is unimportant since any signal at the bridge output is unwanted; and since the bridge output is greatly attenuated leading to signals which are largely distortion free. Therefore, small-signal models adequate describe circuit behavior in hold mode. The bridge model (Fig. 3.24a) includes C d , the diode small-signal junction capacitance, for those diodes which are nonconducting, and r d , the diode small-signal resistance, for those diodes which are conducting during hold mode. Also included in the model is an amplier with A V gain and r o output resistance feeding its signal from the bridge output to the bridge center tap. These parameters can be set to zero if the bridge center tap is grounded directly rather than driven by an amplier. Bridge feedthrough
173
analysis proceeds by noting that this model includes identical elements mirrored above and below a horizontal line of symmetry. By combining in parallel those elements which by symmetry are seen to exhibit identical node voltages, the simplied network of 3.24b results which can be solved most easily by nodal analysis. The 3 equations which govern circuit operation are:
( V in V Top ) s2C d + ( V out V Top ) s2C d + ( V FB V Top ) r b = 0 ( V Top V out ) s2C d V out sC H = 0 V FB = A V V out
where r b = r d 2 + r o . The second constraint above can be solved for V out in terms of V Top and the third constraint gives V FB in terms of V out . (3.136)
V out = V FB =
2C d V C H + 2C d Top C H + 2C d 2A V C d V Top
(3.137)
These two relations allow V in to be expressed solely as a function of V Top :
V in =
V Top 1 s4C d ( C H + C d ) + ( C H + 2C d ( 1 A V ) ) rb s2C d ( C H + 2C d )
(3.138)
When the above equation is combined with the rst expression in 3.137 the hold mode gain results.
V out Cd = V in CH + Cd
s 2 ( 1 AV ) Cd + CH s+ 4r b C d ( C H + C d ) rb = rd + ro 2
(3.139)
where
This equation indicates that the input-output transfer function exhibits a zero at DC and a pole at a frequency dependent upon the circuit parameters. The expression for this pole frequency can be
174
simplied if C H 2C d in which case
2 ( 1 AV ) Cd + CH 1 1 = ft 4r b C d 4r b C d ( C H + C d ) ft 4r b C d
Therefore, the input-output characteristic simplies to
(3.140)
V out Cd s = V in C H + C d s + 1 ft
The magnitude of this transfer function is
(3.141)
V out V in
=
s = j
Cd CH + Cd
2 + 1 2 ft 1 1 + 1 ( ft ) 2
(3.142)
Cd = CH + Cd
which is plotted in gure 3.25. Since, r b is a few tens of ohms and C d is a few tens of femtofarads,
20 log H ( j ) Cd Cd + CH
Cd C d + C H ft
20 dB/decade 1 1 = ft 4r b C d
V out V in
s = j
Figure 3.25. Small-signal frequency response of diode bridge in hold mode.
175
the pole frequency, 1 ft , is many tens of Gigahertz; therefore, at all frequencies of interest
ft 1 and the expression for feedthrough can be simplied: V out V in =

s = j
Cd 1 C H + C d 1 + 1 ( ) 2 ft Cd ( ft ) 2 CH + Cd Cd C H + C d ft Cd 4r C CH + Cd b d
2
= =
(3.143)
Cd = 4r b CH
where C H C d was assumed in the last simplication. The frequency-dependent feedthrough in hold mode is simply:
Cd Feedthrough ( in) = 4r b C H in
(3.144)
Notice that hold capacitance, C H , is the only parameter which can be freely varied since r b cannot reasonably be made smaller than about 10; C d is a xed device constant dependent upon the process being used; and in is a parameter of the performance goals for the circuit. Feedthrough can be made arbitrarily low by increasing the value of C H which will also decrease distortion due to hold pedestal, but at the expense of increased track mode distortion in both the preamplier and the diode bridge itself. If a satisfactory trade-off cannot be made with this approach and a differential implementation is used, capacitively coupling signals from the complementary bridge can partially cancel the residual signal at the hold capacitor affording an added degree of signal attenuation [10]. An embodiment of this concept (Fig. 3.26) entails coupling capacitors from the top and bottom nodes of each bridge to the output node of the complementary bridge. Cancellation of the output signal occurs during hold mode if the value of the coupling capacitance equals the value of the corresponding diode junction capacitance. If this condition holds, capacitor C2B couples a signal from the top of bridge B onto hold capacitor C HA equal in magnitude to the signal coupled through diode D2A onto C HA ; however, since bridge B receives an input signal complementary to
176
C2A
C2B
D1A VA
D2A
D2B VB CHA CHB D4B
D1B
D3A
D4A
D3B
C4A Bridge A
+Vout
C4B Bridge B
Figure 3.26.
Cross-coupled capacitors between complementary bridges reduce feedthrough and hold pedestal error.
bridge A, the signal coupled through C2B is complementary to that coupled through D2A. Therefore, the net coupling onto the hold capacitor is zero. Similarly, C2A cancels the coupling through D2B; C4A cancels D4B; and C4B cancels D4A. These cancellations also operate during track mode but since the bridge impedance is then very low, the effect is negligible. The bridge diode bias voltages vary from track mode to hold mode and also depend upon the signal at the bridge center taps, labelled V A and V B in gure 3.26. Diode and cross-coupling bias voltages are tabulated for reference in table 3.1. If the bridge center taps are grounded (or more generally set to the input
Element
D2A D4A D2B D4B C2A C4A
Track Mode Potential Vd Vd Vd Vd ( V in + V d ) ( V in ) ( V in V d ) ( V in )
Hold Mode Potential ( V A V d ) ( V in ) ( V in ) ( V A + V d ) ( V B V d ) ( V in ) ( V in ) ( V B + V d ) ( V A V d ) ( V in ) ( V A + V d ) ( V in )
V= V Hold V Track V A 2V d V in V A 2V d + V in V B 2V d + V in V B 2V d V in V A 2V d V in V A + 2V d V in
Table 3.1. Bias voltages across bridge elements in track mode and hold mode.
177
Element
C2B C4B
Track Mode Potential ( V in + V d ) ( V in ) ( V in V d ) ( V in )
Hold Mode Potential ( V B V d ) ( V in ) ( V B + V d ) ( V in )
V= V Hold V Track V B 2V d + V in V B + 2V d + V in
Table 3.1. Bias voltages across bridge elements in track mode and hold mode.
common-mode voltage) then the diode bias potential in hold mode is that listed in table 3.1 evaluated with V A = V B = 0 and each pair of diodes, (D2A, D4A) and (D2B, D4B), couples from the bridge top and bottom nodes to the bridge outputs with capacitances C j( V d + V in) and C j( V d V in) . The sum of these capacitances (representing the net capacitance coupled from the bridge top and bottom to the bridge output) will equal to a rst order approximation C j( V d) . Therefore, if C2A, C4A, C2B, and C4B are equal in capacitance to C j( V d) signicant cancellation in bridge feedthrough results. If the bridge center taps are driven with unit-gain ampliers from their respective bridge outputs ( V A = V in and V B = V in ), the resultant hold mode bias voltage on each of diodes D2A, D4A, D2B, and D4B is V d . Therefore, these diodes junction capacitances are each C j( V d) and perfect feedthrough cancellation occurs if the crosscoupling capacitors take on this same value. Mismatches in the cross-coupling capacitors from their ideal values, C j( V d) , will be relatively large because the added capacitors will most likely be implemented with metal-insulator-metal (MIM) or metal-insulator-semiconductor (MIS) structures which do not track diode capacitance well. Simulations which predict bridge feedthrough as a function of cross-coupling capacitance (Fig. 3.27) indicate high sensitivity to mismatches. For example gure 3.27 indicates that a nearly 40 dB increase in feedthrough arises when the crosscoupling capacitance deviates from the ideal value by 25%. Better matching can be obtained by constructing the cross-coupling capacitors from diodes similar to those comprising the bridge. Simple diodes are inappropriate because they will become forward biased interfering with normal bridge operation so structures involving multiple diodes connected to prevent current ow are necessary (Fig. 3.28). Such realizations incur parasitic substrate capacitances which inevitably detract from the achievable signal cancellation, but better matching can indeed be achieved (Fig. 3.29) The simulation leading to the data plotted in gure 3.29 replaced each coupling capacitor with
capacitances are signicantly reduced if a fully oxide-isolated process is used or if a semi-insulating substrate such as in Gallium-Arsenide (GaAs) is used.
. Substrate
178
-70
-80
Feedthrough (dB)
-90
-100
-110
-120
.5
.75 1 1.25 Cross Coupling Capacitance (normalized to optimum)
1.5
Figure 3.27. Feedthrough versus cross-coupling capacitance normalized to

optimum value.
Figure 3.28. Cross-coupling scheme for reduced feedthrough with series connected diodes as coupling elements.
two diodes connected in series but with opposite polarity. The gure indicates that such an arrangement can achieve feedthrough near 100 dB even with diode area deviations of a few percent, matching which is easily attained in most modern semiconductor processes. The hold pedestal phenomenon described in section 3.2.6 can also be mitigated somewhat
179
-70
-80
Feedthrough (dB)
-90
-100
-110
-120 0.85
0.90 0.95 1.00 1.05 1.10 Cross Coupling Diode Area (normalized to optimum)
Figure 3.29.
Feedthrough versus area of cross-coupled diode structure normalized to the optimum area.
with this cross-coupling arrangement. In this case, the charge which is cancelled is that expelled from the bridge diodes when switched from the conducting to the non-conducting state. Figure 3.30 indicates how the cross-coupling capacitances can partially cancel the charges expelled by the bridge diodes during bridge turn-off. For this cancellation to be complete however, the crosscoupling elements must exhibit the same non-linear C-V characteristics as the bridge diodes and must also experience the same voltage transitions during the turn-off transient (see for example gure 3.20). The initial and nal voltages across the diode and cross-coupling elements at the trackto-hold transition compiled in table 3.1 are again helpful in studying such operation. The last column of this table indicates that with V A = V B = 0 , the bridge diodes experience the same voltage transitions as do the pertinent cross-coupling elements; however neither xed capacitors nor series coupled diodes provide the appropriate C-V characteristic to achieve exact charge injection cancellation. Therefore, only rst-order cancellation is possible with this method, improving gain loss due to hold pedestal but leaving distortion unaffected. If the bridge center taps are driven by ampliers from the respective bridge outputs such that V A = V out and V B = V out , then hold pedestal is negligible anyway (recall the analysis from section 3.2.6) so this cross-cancelling
180
Figure 3.30.
Cross-coupling can partially cancel hold pedestal error by cancelling charge expelled by bridge diodes during bridge turn-off. Note that charge injection from a bridge diode connected to the top node of one bridge is cancelled by the cross-coupled element connected to the bottom node of the complementary bridge. Likewise, injection from a diode connected to the bottom of one bridge is cancelled by the cross-coupled element connected to the top of the complementary bridge.
approach is unnecessary. Although the cross-coupling scheme described here can reduce feedthrough and gain loss from hold pedestal, its several drawbacks including sensitivity to device mismatches, added parasitic capacitances loading the bridge, and increased layout complexity call into question the utility of the technique; therefore, this approach was not utilized in the present design.
3.2.8 Noise
Electronic noise generated by the elements within the track-and-hold contaminates the input signal before digitization. Therefore, this noise must be negligible compared to quantization noise to prevent the T/H from limiting the achievable SNR of the A/D converter. Moreover, several noise sources affect T/H operation in ways that are unique from more general purpose circuits. Such sources which comprise T/H noise include: Sample clock jitter as exacerbated by noisy clock buffer electronics within the T/H itself

Electronic noise seen at the hold capacitor during track mode Electronic noise which adds to the held voltage during hold mode
181
Shot noise from the postamplier bias current which is integrated on the hold capacitor during the hold period
These sources are summarized in gure 3.31 and will be described separately below. Since the noise
+Vin
Clock Buffer
2
Preamp and Bridge
kT noise C CH IB Vout
Clock
-Vin
Preamp and Bridge
CH
Noise sources affecting track-and-hold operation. represents the total jitter noise power on the drive signals to the diode bridge including the jitter on the incoming clock and that added by the clock buffer circuitry. kT C represents the mean-square noise voltage at the hold capacitors. This is an approximation assuming that the dominant component is thermal noise and exists during both track mode and hold mode. I B causes base shot noise which is integrated on the hold capacitor during hold mode giving rise to voltage noise.
Figure 3.31.
sources listed are uncorrelated, the total noise power emanating from the T/H is the sum of all of these components. Total noise from an A/D converter includes this electronic noise from the T/H plus quantization noise so that SNR can be expressed as
SNR =
2 Signal 2 + 2 + 2 + 2 + 2 Q Jitter Track Hold Shot

2
(3.145)
where Track is the noise power added to the signal during track mode, Hold is the noise power
2
182

2
added to the held signal during hold mode, and Shot is the shot noise integrated on the hold capacitor during hold mode. The components of noise power found in the denominator of equation 3.145 are now discussed with the exception of the quantization noise power, Q , which was described in detail in section 1.3.2.
2
The effect of clock jitter on SNR was treated in section 3.2.1 from a theoretical standpoint. Here the deleterious effects of electronic noise in the clock buffer on the incoming clock signal are discussed. The function of the clock buffer circuitry is to provide gain and level shifting so that a standard logic-level signal can switch the diode bridge. In so doing, noise within the buffer will exacerbate the jitter of the sampling signal seen at the top and bottom nodes of the diode bridge. The resultant clock noise at the bridge drive nodes (which was the subject of section 3.2.1) derives from the slew rate of the incoming clock signal and the input-referred noise voltage of the clock buffer according to
Bridge
in
dV clock dt
(3.146)
where is the standard deviation of the clock jitter at the bridge drive nodes (this entity was Bridge called in section 3.2.1), and V is the standard deviation of the input-referred clock buffer
in
noise voltage. Notice that this component of clock jitter power adds to the jitter power already existing on the incoming clock signal. dV clock dt , the input clock signals slew rate, is difcult to predict in practice so a pessimistic approximation can be made by assuming that the incoming clock signal is a sinusoid at the clock frequency with appropriate amplitude and offset to alternate between the expected logic levels. dV clock dt can then be determined analytically. Under these conditions, equation 3.146 places an upper limit on the input-referred clock buffer noise since
V
in
Bridge
dV clock dt
(3.147)
and dV clock dt is known from the assumption given above, and can be selected based on Bridge its effect on A/D SNR as detailed in section 3.2.1. V , the standard deviation of the input referred
in
noise voltage, can be calculated using standard methods of circuit analysis and should include all noise sources including thermal noise, shot noise, 1 f noise, etc. In the present design, thermal noise from transistor intrinsic base resistance dominates the input-referred noise but does not present a limit to A/D converter operation at 10 bits of resolution and 100 Msps. The clock buffer

circuitry will be discussed in more detail in section 3.3.3.
183
Noise power produced by the track-and-hold electronics during track mode (called above) can be calculated in ordinary fashion and referred to any convenient node in 2 Track the circuit for purposes of later analysis. This noise represents perturbations which are added to the desired signal and which are sampled and then held when the S/H switches into hold mode. Once in hold mode, electronic noise further perturbs the held signal so that three components contribute to the signal which is eventually quantized: the desired signal itself, additive noise from the circuit in track mode, and additive noise from the circuit in hold mode. Because the bias levels for many T/H circuit elements are different in track mode than in hold mode, the noise contributions during these two states are not necessarily equal. Further, since 2 contributes at the time of the track-to-hold transition while Track 2 contributes at the quantization instant, the two sources are independent (assuming Hold for simplicity white noise). Therefore, the noise power from the two sources simply adds to the desired signal to give 2 = 2 + 2 + 2 Total Signal Track Hold
(3.148)
If the track-mode noise and the hold-mode noise are nearly equal, the total noise power added to the signal is twice that encountered in a continuous-time circuit. Therefore, low noise design of the T/H electronics is particularly important mandating use of extreme care to ensure optimum performance. Although standard techniques of noise analysis pertain to calculation of the noise power at any circuit node, and computer simulation enables rapid and accurate analysis of very complicated circuits; determination of the noise in a very simple network serves as a crude but illustrative example enlightening analysis of the T/H circuit discussed here. Such a simple network is now investigated.
In a simple single-pole system consisting of a resistor driving a shunt capacitor (Fig. 3.32), the noise power spectral density output from the circuit is the low-pass ltered white, thermal noise power spectral density from the resistor whose mean square is v n = 4kTR df . The frequency response of the system is
2
184
R V out v n = 4kTR f
2
Figure 3.32. Single-pole RC low pass lter for analysis of kT/C noise. V out(s) 1 = 1 + sRC V in(s)
so that the output power spectral density becomes
2
(3.149)
2 V out
V in 1+ R C
2 2 2
4kTR df 1 + 2 R C
2 2
(3.150)
and the mean-square noise voltage at the capacitor can be found by integration:
2 V oT 2 V out
df = 2 2 1 + 2 R C
4kTR
4kTR 1 + ( 2fRC )
2
df
(3.151)
where the subscript oT implies total output noise power as distinct from output noise power spectral density. By substituting x = 2fRC , this integration simplies to
2 V oT
( 2kT ) ( C ) 1+x
2
2kT dx = C
1 1+x
2
dx
(3.152)
which is easily solved to give
2 V oT
2kT = C
1 1+x
2
dx =
2kT kT = C 2 C
(3.153)
185
This equation implies that the integrated mean-square noise voltage arising from any single-pole RC network is kT C regardless of the resistor value and bandwidth of the system. Or stated more simply, the RMS noise voltage is kT C . By generalizing the results of the above analysis, it can be shown that in any passive circuit where noise arises exclusively from thermal sources, the mean-square integrated noise voltage at any node with shunt capacitance to ground can be conservatively approximated by kT C where
C is the shunt capacitance. Although this concept does not extend in any rigorous way to active
circuits, most practical circuits exhibit noise voltages on the order of this amount. By simulation, the T/H circuits investigated here demonstrated mean-square noise voltages at the hold capacitor within a factor of about 3 of kT C H for a wide range of circuit parameters. This empirical result allows rapid approximations of circuit noise performance during preliminary design studies. Since similar noise power levels exist at the hold capacitor in both track and hold modes, and since these components arise from independent noise sources, the resultant contribution to the total noise from
2 and Hold is twice the value quoted above; therefore, mean-square noise voltage referred 2 Track
to the hold node can be approximated as Track + Hold 5 kT C . The differential aspect of the
2 2
T/H designed here affects the noise analysis. Since two identical half-circuits comprise the T/H,
kT C noise as just describes exists at each hold capacitor. These noise sources are independent so
+ Vin -
Preamp & Bridge
V nT =
CH
kT CH
+
VH
Preamp & Bridge
CH
+ Postamp
V nT =
kT CH
Figure 3.33.
kT/C noise at the hold capacitors. In the differential implementation the two independent sources contribute to the total noise power perturbing the held voltage, V H resulting in doubled noise power compared to a single-ended version. Signal amplitude is also doubled, thus quadrupling signal power and increasing SNR by 3 dB over the single-ended case.
186
their powers add when affecting the differential held voltage, V H . Therefore, the mean-square differential noise component of the held voltage is V HT = 2kT C (where the HT subscript refers to the total integrated mean-square noise voltage at the hold node as distinct form the noise power spectral density). In spite of this increase in noise power, the differential implementation exhibits superior SNR compared to a single-ended version because while the noise power doubles as shown, the signal power quadruples (since the signal amplitude doubles and the power is proportional to
2
A ). Therefore, a differential T/H circuit is capable of increased SNR by 3 decibels over a singleended version. During hold mode, base shot noise from the postamplier integrates on the hold capacitor,
C H , giving rise to a noise voltage which adds to the held signal further degrading achievable SNR.
+ V Held
_ V Held Ib Ib
CH
CH
I bias
I bias
Figure 3.34.
Base shot noise integrates on the hold capacitors during the hold interval adding a noise component to the held voltage.
The mean square of the shot noise is i n = 2qI B df where q is the electron charge and I B is
the base current owing to the input transistor of the postamplier. When integrated over the
hold period, T S = 1 f S (where f S is the sample rate of the converter), the resultant mean-square noise voltage on the hold capacitor, C H , is
2 = Shot
qI B CH fS
2
(3.154)
. My thanks to Aaron Buchwald for deriving this result.
187
Since the shot noise source is independent from the others previously described, this noise power adds to the total signal power which is eventually quantized. Notice that increased hold capacitance,
C H , decreases the shot noise contribution as does decreased postamplier input bias current, I B .
The integrated shot noise component decreases with increasing sample rate, f S , since the noise current spends less time integrating on the hold capacitor forming a noise voltage. Only C H and I B are parameters under designer control which affect the integrated shot noise. Therefore, these factors must be chosen judiciously to keep Shot acceptably small.
2
3.2.9 Droop
Input bias current owing to the postamplier during hold mode depletes the hold capacitor of charge resulting in a change in the held voltage called droop (Fig 3.35a). The held voltage varies
V Held
CH
V Held Slope= I b / CH Ib 0 Ibias

(a) (b)
time
Figure 3.35. Postamplier input bias current causes droop on hold capacitor.
with the postamplier input current according to:
dV Held(t) Ib = CH dt
(3.155)
where I b is the postamplier input current. If I b is constant, the held voltage changes at a xed slew rate (Fig. 3.35b), and in a T/H circuit operating at sample rate f S = 1 T S the voltage deviation
188
during the hold period becomes
V Held =
Ib TS Ib t = CH CH 2
(3.156)
If the input bias current, I b , is truly constant, then V Held will not vary from sample to sample, and therefore will not affect operation of the T/H except by adding an offset to the stream of held samples. This offset must be kept reasonably small to prevent bias problems in succeeding circuitry but does not hinder performance in any other way. If, however, the postamplier input bias current depends upon the held signal then equation 3.155 modies to
dV Held(t) I b(V Held(t)) = dt CH
(3.157)
where I b(V Held) indicates the functional dependence of I b on V Held(t) . For a known function, I b(V Held) , equation 3.157 can be solved for V Held(T S 2) , the held voltage at the end of the hold mode. If I b is a linear function of V Held(t) , say
I b = V Held(t)
then V Held(T S 2) can be solved for analytically using equation 3.157:
(3.158)
dV Held(t) V Held(t) = dt CH dV Held(t) = dt CH V Held(t)

V Held(T S 2)
Vo
dV Held(t) = CH V Held(t)
TS 2
dt
(3.159)
ln (
V Held(T S 2) TS )= CH 2 Vo
TS CH 2
V Held(T S 2) = V o e
189
The last line of equation 3.159 indicates that the held voltage at the end of hold mode,
V Held(T S 2) , equals the initial held voltage, V o , multiplied by a constant factor, exp ( T S 2C H) . Therefore, when I b is a linear function of V Held , the effect of droop is to
attenuate the stream of sampled signals from the T/H without introducing any distortion. In general, however, dependency of I b on V Held causes distortion at the T/H output because signals of different amplitudes experience different deviations during hold mode. This potential error source can be mitigated by ensuring that I b is small enough and C H is large enough that any distortion resulting from droop is acceptably small. Mandating low postamplier input bias current, I b , and large hold capacitance, C H , as just suggested reduces droop-induced distortion but possibly at the expense of increased settling time of the postamplier due to its low bias current, and at the expense of increased track-mode distortion because of the increased dynamic load on the preamplier. Alternatively, the natural common-mode rejection of a differential implementation can be used advantageously to eliminate most effects of the droop phenomenon. In a differential realization of the T/H, both held voltages will experience nominally equal droop so that the resulting differential signal is largely (if not totally) independent of postamplier input bias current (Fig. 3.36). Since each side of the differential circuit still
+ V Held CH I b1 I b2
V Held CH
Ibias Ibias
(a)
+ V Held
Voltage
slope= I b1/ CH slope= I b2 / CH ~ slope= 0 _ + V Held _ V Held Time
_ V Held
(b)
Figure 3.36. A differential T/H implementation largely cancels droop effects.
190
experiences a voltage drop during the hold mode equal to approximately I b T S 2C H care must be taken to ensure that bias levels of succeeding circuitry remain suitable. Cancellation of droop effects relies upon I b1 = I b2 in gure 3.36. Otherwise, a residual differential droop signal will perturb the held signal according to
V Held = V Held V Held =
( I b1 I b2 ) T S 2 CH
(3.160)
If the current difference I b1 I b2 is constant, then (as in the single-ended case with constant I b ) V Held will not vary from sample to sample but will merely add a xed offset to each sample of the output data stream. Likewise, if I b1 I b2 varies linearly with V Held , then attenuation of the sampled data stream results. Again, as in the single-ended case, distortion arises when I b1 I b2 is a nonlinear function of V Held . The chief advantage of the differential implementation regarding droop behavior is that I b1 I b2 is usually quite small so that the slew rate of the differential output from the postamplier is near zero. In contrast, the postamplier can traverse many A/D LSBs during the hold mode if a single-ended circuit T/H is used.
3.2.10 Thermal Distortion

Power dissipated in an integrated circuit induces temperature gradients across the surface of the silicon chip. These gradients in turn affect device operation because the underlying semiconductor physics follow either Fermi-Dirac or Maxwell-Boltzmann distributions both of which depend exponentially on temperature. Such temperature dependence is exhibited by, among other things, I S , the saturation current of a pn junction, and V T , the thermal voltage equal to kT q . These two dependencies combine to determine the temperature coefcient of the pn junction potential under constant current conditions, TC V , which is well known to be approximately BE 2 mV/C. This extreme sensitivity of the bipolar transistors operating characteristic frequently degrades circuit operation by causing unwanted perturbations in base-emitter potentials when temperature gradients exist. For example, thermal effects can induce offsets in comparators when one transistor of the input differential pair operates at a different temperature than the complementary transistor. This temperature difference can be caused by power dissipation within the comparator itself which, in turn, depends upon the input signal to the circuit. Since dynamic thermal behavior in silicon exhibits natural frequencies in the audio range, signal-dependent

thermal gradients result in unwanted comparator hysteresis [34], [35].
191
To quantify the magnitude of electro-thermal interaction, the thermal resistance from a devices junction to the substrate, js , must be known. js can be calculated by solving the steadystate thermal diffusion equation for a device of given geometry and power dissipation [36],[37]. When performed for a minimum-size SHPi transistor with a 2 m X 8 m emitter area not located near any adiabatic edges and dissipating 1 mW in a 250 m thick substrate, such analysis yields a temperature contour exhibiting a 2 C temperature rise from the substrate to the emitter center (Fig. 3.37). Therefore, for a minimum-size SHPi device, js = 2 C mW . The contour
2 Temperature Rise (C)
1.5
0.5
0 20 0 -20 y axis (microns) -20 x axis (microns) 20 0
Figure 3.37. Thermal contour of minimum-size SHPi device (2 m X 8 m emitter area) dissipating 1 mW on a 250 m thick substrate.
of gure 3.37 also indicates that temperature perturbations of the substrate are localized to an area a few times larger than the emitter itself, indicating that modest power dissipated in one device will only marginally increase the temperature of adjacent devices. For comparison, a large device with a 75 m X 75 m emitter area dissipating 200 mW also in a 250 m thick substrate shows an increase in emitter temperature of approximately 20 C although the power density is only about
192
half of that in the previous case (Fig. 3.38). js for this device is therefore 0.1 C/mW. Again,
20
Temperature Rise (C)
15
10
0 0.4 0.2 0 -0.2 y axis (mm) -0.4 -0.4 -0.2 x axis (mm) 0.2 0 0.4
Figure 3.38. Thermal contour of large device (75 m X 75 m emitter area) dissipating 200 mW.
signicant temperature changes are limited to an area a few times larger than the emitter region. Note that although the area of the larger device is 350 times that of the minimum device, its thermal resistance to the substrate, js , is only 20 times lower. Nonetheless, when high power dissipation is required, larger devices are necessary for their lower thermal resistance. Electro-thermal interaction gives rise to distortion when an electrical input signal modulates device power. The power modulation induces temperature uctuations within the device resulting in electrical perturbations which distort the original signal. This phenomenon, called thermal distortion, is particularly troublesome in precision circuits where even small deviations from ideal performance are unacceptable. The T/H circuit under consideration represents such a precision circuit, and even a simple emitter follower buffer comprising the preamplier and/or postamplier is susceptible to excessive thermal distortion. Emitter follower device power is determined exclusively by the input voltage since the bias current is ideally constant (Fig. 3.39). Power dissipation in a transistor can be expressed by
193
V CC V in P D = I c V ce + I b V be V out I Bias
Figure 3.39. Emitter follower buffer. P D = I c V ce + I b V be I c V ce

(3.161)
where the approximation assumes I c I b . In an emitter follower such as depicted in gure 3.39 the power dissipation becomes
P D = I Bias ( V CC V out ) = I Bias [ V CC ( V in V be ) ]
(3.162)
If the input voltage, V in , changes to a new value, V in + V in , then the power dissipation will change correspondingly to
P D + P D = I Bias { V CC [ ( V in + V in ) V be ] }
(3.163)
where any changes in V be are assumed to be negligible. Subtracting equation 3.162 from equation 3.163 gives the change in power, P D , as a function of the change in input voltage, V in :
P D = I Bias V in
(3.164)
This change in the emitter follower power dissipation will cause a change in the base-emitter junction temperature which will in turn cause a change in V be . The change in V be can be determined from the device thermal resistance, js , and the temperature coefcient of the pn junction potential, TC V . BE
V be = TC V js P D
BE
(3.165)
By substituting the expression in equation 3.164 for P D the incremental base-emitter voltage as
194
a function of the incremental input voltage results:
V be = TC V js I Bias V in
BE
V be = TC V js I Bias BE V in
(3.166)
Since V be is an error term caused when V in is applied to the T/H, and since this error term must be small compared to a quantization step, Q , of the following quantizer, the ratio V be V in must smaller than 2
N
. This places an upper bound on the emitter follower bias current before thermal
distortion leads to errors larger than one quantization step.
V be N <2 V in TC V
BE
js I Bias < 2 2 TC V
N N
BE
I Bias < I Bias <
(3.167)
js
1 2 TC VBE js
The last line of equation 3.167 represents a severe limitation on bias current for emitter followers in high-resolution circuits. For example, in the T/H under consideration with N = 10 ,
TC V
BE
= 2mV C , and js = 2 C mW , bias current is limited to I Bias < 1 2 TC VBE js

N
1 250 A 2 C 2mV 10 (2 ) ( )( ) mW C
(3.168)
This low value of bias current can be problematic when driving capacitive loads because both bandwidth and dynamic linearity degrade with reduced bias (as explained in section 3.2.3). Therefore, simply selecting low bias levels is not a viable method for reducing thermal distortion to acceptable levels. Rather, techniques must be employed to enable operation at higher bias levels without thermal distortion effects. Circuits based on negative feedback can achieve insensitivity to thermal gradients, but this method is rejected for the present application because open-loop
3.3 Track-and-Hold Design
195
implementations offer potentially higher-speed operation. Instead, approaches are utilized which maintain constant power dissipation in pertinent devices independent of signal level, or which constrain signal-dependent power to be matched between complementary devices in differential implementations [38]. Both of these techniques have been used in the T/H circuit and will be described in detail.

Sections 3.1 and 3.2 discussed operation and limitations of diode-bridge track-and-hold circuits from a general perspective. This section describes in detail the specic circuits implemented during this project to realize a 10-bit 100 Msps A/D converter with on-chip T/H. Two such circuits are required in the feedforward architecture used: the rst, the input T/H, tracks the 50 MHz input signal with adequate dynamic linearity to assure 10-bit operation at 100 Msps while the second, the interstage T/H, is required for pipelined operation of the A/D converter and requires only linearity consistent with 7-bit quantization but must also operate at 100 Msps.
3.3.1 Preamplier and Sampling Bridge

The input T/H circuit is based upon a diode-bridge with a differential pair current switch and resistive loads. Both the preamplier and postamplier are based upon emitter followers to achieve a simple design with high-speed performance and good linearity (Fig. 3.40). This circuit suffers from several drawbacks which were discussed in section 3.2 and which can be at least partially alleviated by resorting to a differential implementation. Additional circuit modications are required to overcome other shortcomings. The important error sources aficting the T/H of gure 3.40 include: Track mode distortion due to dynamic load current owing through the input emitter follower and diode-bridge and into load capacitor C L (these effects are analyzed in sections 3.2.3 and 3.2.4) Track mode distortion caused by nite load impedances, R L , as described in section 3.2.4 Thermal distortion resulting from signal-dependent power modulation in the preamplier and postamplier (section 3.2.10)
196
RL
RL
Vin
Vout C H
Hold
Track
Figure 3.40. A single-ended T/H circuit based on a diode-bridge with emitter

follower preamplier, differential pair current switch with resistive loads, and emitter follower postamplier. Excessive droop caused by postamplier bias current discharging the hold capacitor (section 3.2.9) Exacerbated hold pedestal error which arises because the bridge center-tap node is not centered at the same voltage as the input signal. The input source is assumed to be ground-centered with 50 impedance. (See section 3.2.6.) The differential circuit implemented to mitigate these errors (Fig. 3.41) includes two identical diode-bridge switches driven by a common clock buffer, two hold capacitors connected to ground, a differential postamplier, and a compensation network between the complementary input emitter followers to decrease both static and dynamic track-mode linearity. The differential nature of the circuit naturally cancels even-order error terms including even-order distortion components and droop. Additionally, the SNR of this approach is improved over the single-ended version because while the noise power is doubled, so is the signal amplitude resulting in quadrupled signal power. Aside from these advantages which accrue for all differential circuits, the available complementary
197
Input Buffer
Vin
X1
Diode Bridge Switch
Compensation Network
Track Hold
Clock Buffer
+ -
Vout
Differential Postamplifier
Vin
X1 Input Buffer
Diode Bridge Switch
Figure 3.41. A differential track-and-hold implementation with linearity compensation.

signals can be used judiciously to cancel some mechanisms of distortion. The technique used here (Fig. 3.42) reduces track mode distortion by injecting a compensation current at the emitters of the two main emitter followers. This compensation current is generated by a transconductance cell comprising a degenerated differential pair whose inputs are developed by an auxiliary pair of emitter followers. The output of each auxiliary emitter follower drives the complementary input of the transconductance cell so that the effective polarity of transconductance is inverted. The magnitude of the transconductance is determined by the cells degeneration resistance, R E , which is set equal to the diode-bridge load resistors, R L . By selecting this polarity and value of transconductance, signal current is injected into the input node of the bridge exactly equal to that required to ow through the parallel combination of the two bridge load resistors, R L , in response to the input signal. This arrangement therefore cancels the static signal current owing from the main emitter follower eliminating its signal-dependent V be modulation and hence its static distortion. Dynamic distortion caused by signal current owing from the main emitter followers into the hold capacitors is also reduced with this mechanism by connecting a shunt capacitor around the transconductances degeneration resistor. The value of this capacitance should nominally equal one half the hold capacitance, but the actual value, determined empirically via simulation, is
198
RL
RL
RL
RL
Vin+
A=4
To Postamplifier Vout+ Vout-
A=4
Vin-
Hold
Track 2.5 mA
Track 2.5 mA
Hold
RE
200 uA
800 uA
800 uA
200 uA
Figure 3.42. Differential preamplier and bridge with compensation.

somewhat different to optimally cancel not only dynamic distortion from the main emitter follower, but from other dynamic effects within the bridge as well. Because the bias and signal currents owing through the bridges are unaffected by this scheme, distortion arising from current modulation in the bridge diodes (both static and dynamic) is not eliminated. These distortion sources are analyzed in section 3.2.4, and along with nite aperture time remain as the dominant error sources in the T/H. In addition to generating the input signals for the compensating transconductance cell, the auxiliary emitter followers feed a level-shifted signal to the base of a bootstrap device which maintains a constant V ce across the main emitter followers independent of the input signal level. This method eliminates thermal distortion in the input devices. To reduce thermal noise which is dominated by intrinsic base resistance in the main emitter followers, these devices are selected to be 4 times the minimum device size, thus reducing the contribution of these noise sources by a like factor. The center-tap nodes of the complementary bridges are biased at one diode drop below ground potential. This voltage drop matches that of the input emitter followers so that the centertap nodes are biased at the common-mode voltage of the differential input signal. The preampliers consisting of main and auxiliary emitter followers, the complementary diode-bridges, the transconductance cell, and the two hold capacitors are laid out in symmetric fashion occupying an area of approximately 600 m 500 m (Fig. 3.43).
199
## # pppp # p # #p p p#p p# # p # ## ppp pp p p #p # # p# p p ## p ppp p p# p# # p#pp # # ## pp # # # # # # #pp # p p pppp # p # # p # # #p # p p# p p # pp p p # ## #p p# p# # #p p ## # p p p #p# #p # p p pp# p #p #p #p p p# p #p# #pp p pp#p p p ## p p p pp## ## # pp pp # # p pp pp # # ppp p #p pp #p # #p #p p p p ppp # ##p pp #p # pp p # # # p p # ppp ## ### pp #### # p # ppp ppp pppppp
xsamp1 Size: 592 x 480 microns
Layout of differential preamplier and diode bridge with feedforward compensation.
Figure 3.43.
3.3.2 Postamplier Design

The purpose of the postamplier is to provide high input impedance with low bias current to prevent leakage of charge from the hold capacitor during hold mode. In addition, an ideal postamplier should exhibit low output impedance for driving capacitive loads with low distortion and short settling time. Of course, low power dissipation, and low-noise operation are desirable as for any analog component. In some instances, the postamplier also provides voltage gain, but the rst T/H in the present A/D converter does not require gain greater than unity (the voltage gain of the postamplier in the second T/H from this design is 2 however). A prototype postamplier fullling all of the above characteristics derives from an ideal operational amplier (op-amp) congured as a voltage follower (Fig. 3.44a). This circuit provides innite input impedance, unity gain, and zero output impedance, but is unrealizable in practice. A simple but crude approximation to this ideal relies on a resistively loaded differential pair to form a basic one-stage op-amp (Fig.
200
Vcc RL Vin Vout Vin Ibias Vout
(a) Auxiliary Amplifier
(b)
X1
RL Vin Ibias
Level Shift Vout Vout-
RL Vin+ RE
RL Vin-
Vout+
(c)
(d)
Postamplier implementations. (a) An operational amplier connected as a voltage follower. (b) A differential pair congured as a voltage follower. (c) A differential pair-based follower with enhanced performance. (d) An open-loop unity-gain postamplier with linearity compensation. 3.44b). The chief limitation of this approach is the relatively low gain achievable with resistive loading which is expressed by
Figure 3.44.
AV = gm RL =
VR IC L RL = VT VT
(3.169)
where V R is the bias voltage across load resistor R L . Since a 5 Volt power supply is used, V R is L L limited to about 2.5 Volts so that the maximum gain is
AV =
VR
VT
2.5V = 100 25mV
(3.170)
201
With open-loop gain of 100, the followers closed-loop gain is only approximately 0.99, and the improvements from feedback in input and output impedance are modest. The effective resistance,
R L , can be increased, and the amplier gain improved proportionately, if the top node of the load
resistor is driven by a level-shifted replica of the output voltage rather than connected to the positive power supply (Fig. 3.44c). In this arrangement, a constant bias equal to the level-shift voltage is maintained across R L thus presenting an innite impedance to the differential pair. Higher openloop gain and improved closed-loop performance result. If the gain of the auxiliary amplier in gure 3.44c is 1 rather than 1, the effective impedance looking into the load resistor is R L and the open-loop gain becomes
AV = gm
VR RL V LS IC RL L = = = VT V T V T
(3.171)
where V LS is the value of the level-shifting voltage. Therefore, even with a non-ideal bootstrap amplier signicant improvements in gain can be achieved. A suitable circuit for providing the level-shifting and near-unity gain necessary in gure 3.44c is shown in gure 3.44d. This buffer amplier relies on a degenerated differential pair with resistive loads to attain voltage gain near unity, and employs diode-connected transistors in its loads to enhance linearity. The load diodes improve linearity by eliminating the dependence of amplier gain upon transistor g m . The transconductance of the degenerated differential pair is
Gm =
gm 1 = 1 + gm ( RE 2) ( RE 2 ) + 1 gm
(3.172)
where R E 2 appears instead of R E because differential half-circuit is used for calculating the gain. The load impedance seen in gure 3.44d is
ZL = RL + 1 gm
so that the amplier gain becomes
(3.173)
AV = Gm ZL =
RL + 1 gm ( RE 2 ) + 1 gm
(3.174)
202
If R L = R E 2 then the gain expression simplies to
AV =
( RE 2 ) + 1 gm = 1 ( RE 2 ) + 1 gm
(3.175)
Since the voltage gain, A V , is independent of g m , distortion-free operation results. Finite transistor reduces the actual gain of this amplier to slightly less than unity for two reasons. First, losses reduce the G m given above by the factor ( + 1 ) , and second, g m of the load diodes is lower than that of the differential pair transistors by the same factor, ( + 1 ) , since the collector current of the differential pair devices equals the emitter current of the diode-connected load transistors. Equation 3.175 indicates that the buffer amplier voltage gain is negative, however, since the realization is fully differential, either inverting or non-inverting operation is easily obtainable. This differential auxiliary buffer is combined with two complementary followers from gure 3.44c to form the T/H postamplier (Fig. 3.45). In this implementation, each of the transistors
Vcc
Vin+
A=4 A=4 A=4 A=4
Vin-
+ Vout Figure 3.45. Differential postamplier implementation.
comprising the op-amp followers is increased in area to reduce thermal noise from intrinsic base resistance. Additionally, the high gain achieved with the bootstrapping technique will increase the
203
input impedance and decrease the output impedance signicantly. Each transistor in the op-amp differential pairs experiences constant V ce so thermal distortion is eliminated (any residual thermal effects are further reduced because of the closed-loop nature of the amplier). The postamplier layout is symmetrical; is pitch aligned with the preamplier and bridge circuits; and occupies an area of 300 m 500 m (Fig. 3.46).
Figure 3.46. Layout of differential postamplier with feedback bootstrapping.
# # # ## ## ## # # # # # ppp p # # # # p #ppp# # ppp#p # p# # # ppp# p pp ## p pp# pp p # #p p# p p # # ## # p #ppp # p pp # # # # p ## # # p # pppp #p ## # # p# # # # # p# ppppp # pp # # p # p p # # p # # # ppp p p pp p p# # # p # p # ppp # # ## # ## # # # # #
3.3.3 Clock Buffer

The clock buffer circuit provides suitable gain and level-shifting to accept a standard
204
emitter-coupled-logic (ECL) input signal and drive the differential pair switches which control the complementary diode-bridge. The buffer must perform this function while adding minimal noise to the incoming clock signal (as discussed in sections 3.2.1 and 3.2.8) and while dissipating minimal power. The implementation used for this project (Fig. 3.47) incorporates input emitter followers to
+
Vin -2V
+
Vout
Vref
Figure 3.47. Clock buffer schematic diagram.
provide high input impedance and level-shifting, a resistively loaded differential pair to provide gain and common-mode rejection, and emitter follower output buffers to provide low output impedance. Two series connected diodes ensure the correct common-mode bias voltage at the output of the differential pair where on-chip capacitors lter broadband noise and prevent ringing of the output emitter followers when driving capacitive loads. The input emitter followers are 4 times larger than minimum devices to reduce their base resistance associated thermal noise which proves to be the dominant noise source in this amplier. The clock buffer is pitch-aligned with the

rest of the T/H circuitry and occupies an area of 220 m 425 m (Fig. 3.48).
205
# #### #p# p# # # ## # # # # # ## # ## # #p #p# #p#p ## p ## p ppp ## # # pp ### ## pp ppp # p # #p p# p pp #p # p# #p ## p p pp # p #p # # # p p p # # #
ckbuf Size: 220 x 424 microns
Figure 3.48. Layout of rst track-and-hold clock buffer circuit.
3.3.4 Design Summary

The differential preamplier, complementary bridges, and differential postamplier combine to form the T/H circuit used for this A/D converter (Fig. 3.49) which operates from +5 V and 5 V supplies dissipating approximately 100 mW. (The clock buffer and bias generation circuitry are not included in gure 3.49 for simplicity but are included in the 100 mW power gure.) The two hold capacitors are 2 pF metal-oxide-semiconductor (MOS) structures which occupy around 10% of the T/H area which is 1200 m 500 m (Fig. 3.50). The full-scale input signal
206
V in
V in
+ V out Figure 3.49.

Complete track-and-hold circuit (with postamplier shaded). The clock buffer has not been drawn for simplicity.
# # # p ## p p ## p p # p# p ### ## p # pp # # # # pp p #p # p p # # # p # # # # pp # p p #p ## # ## # # pp p p p # #p # p # ## p# p # # # # # #p # # #p # # pp p # # # p # # p p ## # p # # # p ## # pp p p pp # # p p # p # p # # ## # p p p # #p p ##p ## p# ## pp# pp # p # # #p # # p p p # # ### # pppp p # p p # # ## # p# pppp # # # #p #p p # p # # # p # p
th1 Size: 1232 x 480 microns
Figure 3.50. Layout of rst track-and-hold circuit.

to the T/H is designed to have 512 mV differential amplitude. Alternatively, the full-scale range can be specied as 1.024 V differential. Simulations indicate that for a full-scale sinusoidal input at a frequency near 50 MHz and sampled at 100 Msps, the spectrum of the output sample stream contains harmonics which are over 80 dB below the fundamental frequency (Fig. 3.51). The prominent odd-order harmonic is the 3rd, located at 85.7 dBc, while the odd-order total harmonic distortion (THD) is 84.4 dB. These gures approach the ideal distortion level of a 10-bit quantizer which is 9N = 90dBc . Because the differential architecture of the T/H rejects all even-order distortion products, only odd components appear in the differential output spectrum. Anticipating imperfect cancellation of even-order components due to mismatches in the T/H components, the single-ended output spectrum was also investigated. The worst-case even-order harmonic in the
3.4 Interstage TrackandHold Design
207
0 -10 -20 Relative Amplitude (dBc) -30 -40 -50 -60 -70 -80 -90 -100
4 Harmonic
Figure 3.51. Simulated T/H output spectrum. Fs=100 Msps, Fin=43.75 MHz.
single-ended spectrum is the 2nd at 67 dBc. This distortion product, along with all other evenorder components, will be attenuated signicantly by the common-mode rejection of the succeeding circuits within the A/D so that the overall distortion performance of the T/H is acceptable for application in a 10-bit converter.

The second (or interstage) track-and-hold circuit receives a signal from the residue amplier in the A/D converter which must be quantized with 7-bit resolution. As in the rst T/H, operation at 100 Msps is required, but the input to the second T/H is not a dynamically changing signal. Rather, the input here is a signal which steps rapidly at the hold-to-track transition (as the reconstruction DAC switches to its new state) and then settles slowly during track mode. Therefore, good dynamic linearity in track mode is unnecessary and only static linearity consistent with 7-bit quantization (implying SFDR = 9N = 63dBc ) is required. Unlike the input T/H, gain accuracy is critical in the interstage T/H and its design is modied accordingly. The interstage T/H is modelled after the input T/H with slight modication as indicated in gure 3.52. This block diagram indicates that the interstage T/H is identical to the input T/H with the addition of two feedback ampliers from the two output nodes to the bridge center-tap nodes.
208
Feedback Amplifier X1 Input Buffer
Vin
X1
Diode Bridge Switch
Compensation Network
Track Hold
Clock Buffer
+ -
Vout
Differential Postamplifier
Vin
X1 Input Buffer
Diode Bridge Switch
X1 Feedback Amplifier
Figure 3.52. Second stage track-and-hold block diagram with feedback to bridge center-tap nodes to reduce gain-loss due to hold pedestal error.
These ampliers reduce hold pedestal error which would otherwise cause unacceptable gain loss (see section 3.2.6). The feedback ampliers are simple, one-stage op-amps congured as voltage followers like that depicted in gure 3.44b. When connected between bridge output and center-tap node (Fig 3.53), these buffers signicantly reduce the deleterious effects of hold pedestal. The layout of the interstage T/H is symmetrical and occupies an area equal to 1200 m 500 m (Fig. 3.54). The postamplier of the interstage T/H must present a high impedance to the hold capacitors to prevent excessive droop, and must provide voltage gain of 2 in order for the amplitude of the residue signal to correctly align with the full-scale voltage of the ne quantizer. This gain
xsamp2
Size: 226 x 556 microns
Vin
Hold Track
Figure 3.54. Layout of second T/H.
C H
Figure 3.53. Second track-and-hold with bootstrapped center-tap.
Vout
209
must be accurate to within about 1% to prevent missing codes in the A/D transfer function. The
# # # # # # # ## pp ### #pp # # p # # p # ## # p # #p # ## p# # p#pp # pp # ##p # ## # p p p pp p #p ## # # ppppp p ### p# p ## ## # # p p# p # #pp # p # ## ## # p# pp p # # # #ppp # #pp # # pp # # # p # ## # # ##pp # p # ppp p # # p# ## p # p # #pp p # p # ppppp # # # pp pp # # # # # pp # # pp# pp
210
circuit implemented here resembles that described in section 3.3.2 and shown in gure 3.44d with the exception that the load impedances are doubled to achieve the increased gain necessary (Fig. 3.55). In this circuit, the output common-mode voltage is set by a diode reference string (D1-D3)
Vcc
D3 Qpull-up
D2 D1
Ql1A
Ql1B
Ql2A
Ql2B
Rl
Rl
+Vout-
Vin+ Ree
Vin-
Figure 3.55.
Interstage postamplier schematic which provides high input impedance and voltage gain of 2. Output emitter followers are not shown for simplicity.
which supplies the bias voltage for the base of an emitter follower pull-up device (Qpull-up). Using this method, the output common-mode voltage becomes
V cm = V D1 + V D2 + V D3 V Qpull up V Ql1A V Ql2A I Bias R L = I Bias R L
(3.176)
211
where the last line of equation 3.176 assumes all V BE drops are equal. Since this bias voltage is independent of V BE , it is also independent of the concomitant reliance on temperature. The gain of the second postamplier is
1 1 1 ( AV = Gm ZL = + + RL) R ee g mQl1A g mQl2A 1 g + 2 m 1 2 ( + RL ) = R ee g m 1 g + 2 m

If R ee = R L , then this expression reduces to
(3.177)
1 2 ( + RL ) AV = R ee g m 1 g + 2 m 1 2 ( + RL ) = 2 = RL g m 1 g + 2 m
(3.178)
Since the gain is independent of g m and hence transistor operating point, the amplier should be distortion-free. Mismatches in components will degrade performance from this ideal, but operation with linearity appropriate for 7-bit quantization ( SFDR = 9N = 9 7 = 63dB ) is achievable. The interstage postamplier layout is symmetrical and occupies an area equal to
225 m 300 m (Fig. 3.56).

A replica of the interstage T/H circuit facilitates matching the A/D converter residue fullscale amplitude to the ne quantizer full-scale amplitude. This replica circuit is identical to the interstage T/H but scaled down to reduce power dissipation. Also, the replica circuit is locked in track mode, so the bridge switch circuitry is eliminated. The entire interstage T/H along with its replica, the clock buffer, and the bias circuitry occupy an area equal to 750 m 1000 m (Fig. 3.57).
[1]
212
References
[3]
[2]
Figure 3.56. Second T/H postamplier.

sh2pst Size: 224 x 285 microns
pp p p ## #p p#p## ##p # ### p## #p # # # p# p# p p #p # p # ## p pppp# #p # p# # # #### ppp p p # #ppp # pp #p pp pp ### p ### p #p# p # p pp## p p # p ## # # # # p p# # # # p p ## ## # # # # #### p# # #pp # p# #p ###p p #p# # #ppp# # ## # # #p # # ## pp ## # p p # pp# p p # ppp p # # # p pp # # p p p p p
B. Gilbert, Translinear circuits: A proposed classification, Electronics Letters, vol. 11, pp. 1416, Jan. 1975.
B. Gilbert, A new wide-band amplifier technique, IEEE Journal of Solid State Circuits,
B. Gilbert, A precise four-quadrant multiplier with subnanosecond response, IEEE Journal of Solid State Circuits, vol. SC-3, pp. 365373, Dec. 1968.
[5] [4]
[7] [6]
[9]
[8]
[11]
th2 Size: 741 x 981 microns
[10] vol. SC-3, pp. 353365, Dec. 1968.
Figure 3.57. Second T/H with replica.
E. Seevinck, Analysis and Synthesis of Translinear Integrated Circuits. Elsevier, 1988.
E. Seevinck, Synthesis of nonlinear circuits based on the translinear principle, in International Symposium on Circuits and Systems, pp. 370373, IEEE, 1983.
A. J. Metz, Sampling bridge. U.S. Patent Number 4,659,945, Apr. 1987.

213
J. R. Gray and S. C. Kitsopoulos, A precision sample and hold circuit with subnanosecond switching, IEEE Transactions on Circuit Theory, vol. CT-11, pp. 389396, Sept. 1964.
I. Dostis, Evaluation of the nonlinear distortion caused by the finite turn-off time of a Sample-and-Hold-Circuit for high-speed PCM, IEEE Transactions on Circuit Theory, vol. CT-13, pp. 9497, Mar. 1966.
K. Tanaka, F. Ishikawa, K. Abe, and K. Koma, A 40MS/s monolithic S/H IC, in Interna-
B. Astegher, A. Lechner, and H. Jessner, A novel All-NPN sample and hold circuit, in 15th European Solid-State Circuits Conference Digest of Technical Papers, pp. 8891, IEEE, 1989.
G. Erdi and P. R. Henneuse, A precision FET-Less Sample-and-Hold with high Chargeto-Droop current ratio, IEEE Journal of Solid State Circuits, vol. SC-13, pp. 864873, Dec. 1978.
##### ## ##### # # #p## ## ### # #### pp p# #p # p## p# #p pp #p ##### ##p## p # ppp# ## pp# # p p## # p ## ## p## ### ppp p # # p # pp ## # # p p ## # # ## ppp p# # # #pp # p p # ## ##p# # # #p ##p # # # pp # p pp p ## p # #p p# p pp # p # # # # #p #p p # p # p # # # # # p # p p pp # # p# # # p # # ## # p # p # #### # p pp # ##p # # # #p # #p #pp ppp pp pp # ### #p # # #p pp# # ppp # # # ##p # # #pp p#p #p p p pp p # # # # #p## # p # ##p p p p# #p p p ## p p# # # ## #p # #p ##p # p # p p ## p # # #p #p ## # # ### # p p p p p # p# p # ## ## p p ## p pppp p p p ## #p p# ### # # # # p p ppp # # p # # # ppp#p # # # # ppp # #
214

tional Solid State Circuits Conference, pp. 190191, IEEE, Feb. 1983.
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M. J. Chambers and L. F. Linder, A precision monolithic Sample-And-Hold for video Analog-to-Digital converters, in International Solid State Circuits Conference, pp. 168169, IEEE, Feb. 1991. G. M. Gorman, J. B. Camou, A. K. Oki, B. K. Oyama, and M. E. Kim, High performance sample-and-hold implemented with GaAs/AlGaAs heterojunction bipolar transistor technology, in International Electron Device Meeting, pp. 623626, IEEE, Dec. 1987. K. Poulton, J. S. Kang, J. J. Corcoran, K.-C. Wang, P. M. Asbeck, M.-C. F. Chang, and G. Sullivan, A 2 Gs/s HBT sample and hold, in GaAs IC Symposium, pp. 199202, IEEE, 1988. J. Corcoran, K. Poulton, and T. Hornak, A 1GHz 6b ADC system, in International Solid State Circuits Conference, pp. 102103, IEEE, Feb. 1987. K. Poulton, J. J. Corcoran, and T. Hornak, A 1-GHz 6-bit ADC system, IEEE Journal of Solid State Circuits, vol. SC-22, pp. 962970, Dec. 1987. B. Wong and K. Fawcett, A precision dual bridge GaAs sample and hold, in GaAs IC Symposium, pp. 8790, IEEE, 1987. F. Thomas, F. Debrie, M. Gloanec, M. L. Paih, P. Martin, T. Nguyen, S. Ruggeri, and J.M. Uro, 1-GHz GaAs ADC building blocks, IEEE Journal of Solid State Circuits, vol. SC-24, pp. 223228, Apr. 1989. K. R. Stafford, P. R. Gray, and R. A. Blanchard, A complete monolithic Sample/Hold amplifier, IEEE Journal of Solid State Circuits, vol. SC-9, pp. 381387, Dec. 1974. P. J. Lim and B. A. Wooley, A high-speed sample-and-hold technique using a miller hold capacitance, IEEE Journal of Solid State Circuits, vol. SC-26, pp. 643651, Apr. 1991. M. Nayebi, A 10-bit video BiCMOS track-and-hold amplifier, IEEE Journal of Solid State Circuits, vol. SC-24, pp. 15071516, Dec. 1989. P. Real and D. Mercer, A 14b linear, 250ns sample-and-hold subsystem with self- correction, in International Solid State Circuits Conference, pp. 164165, IEEE, Feb. 1991. P. Real, D. H. Robertson, C. W. Mangelsdorf, and T. L. Tewksbury, A wide-band 10-b 20-Ms/s pipelined ADC using current-mode signals, IEEE Journal of Solid State Circuits, vol. SC-26, pp. 11031109, Aug. 1991. F. Moraveji, A 14b, 150ns sample-and-hold amplifier with low hold step, in International Solid State Circuits Conference, pp. 166167, IEEE, Feb. 1991. F. Moraveji, A high-speed current-multiplexed sample-and-hold amplifier with low hold step, IEEE Journal of Solid State Circuits, vol. SC-26, pp. 18001808, Dec. 1991. R. J. van de Plassche and H. J. Schouwennars, A monolithic S/H amplifier for digital audio, in International Solid State Circuits Conference, pp. 180181, IEEE, Feb. 1983. R. J. van de Plassche and H. J. Schouwennars, A monolithic high-speed sample-and-hold amplifier for digital audio, IEEE Journal of Solid State Circuits, vol. SC-18, pp. 716722, Dec. 1983. R. Petschacher, B. Zojer, B. Astegher, H. Jessner, and A. Lechner, A 10-b 75-MSPS subranging A/D converter with integrated sample and hold, IEEE Journal of Solid State Cir-
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[28]

cuits, vol. SC-25, pp. 13391346, Dec. 1990. [29] [30] [31]
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P. H. Saul, A GaAs MESFET sample and hold switch, IEEE Journal of Solid State Circuits, vol. SC-15, pp. 282285, June 1980. R. Bayruns, N. Scheinberg, and R. Goyal, An 8ns monolithic GaAs sample and hold amplifier, in International Solid State Circuits Conference, pp. 4243, IEEE, Feb. 1987. D. R. Martin and D. J. Secor, High speed analogtodigital converters in communication systems: Terminology, architecture, theory, and performance, tech. rep., TRW Electronic Systems Group, Redondo Beach, CA, Nov. 1981. T. Wakimoto, Y. Akazawa, and S. Konaka, Si bipolar 2-GHz 6 bit flash A/D conversion LSI, IEEE Journal of Solid State Circuits, vol. SC-23, pp. 13451350, Dec. 1988. M. Shinagawa, Y. Akazawa, and T. Wakimoto, Jitter analysis of high-speed sampling systems, IEEE Journal of Solid State Circuits, vol. SC-25, pp. 220224, Feb. 1990. K.-C. Wang, P. M. Asbeck, M.-C. F. Chang, D. L. Miller, G. J. Sullivan, J. J. Corcoran, and T. Hornak, Heating effects on the accuracy of HBT voltage comparators, IEEE Transactions on Electron Devices, vol. ED-34, pp. 17291735, Aug. 1987. K. Poulton, K. L. Knudsen, J. J. Corcoran, K.-C. Wang, R. L. Pierson, R. B. Nubling, and M.-C. F. Chang, Thermal design and simulation of bipolar integrated circuits, IEEE Journal of Solid State Circuits, vol. SC-27, pp. 13791387, Oct. 1992. R. C. Joy and E. S. Schlig, Thermal properties of very fast transistors, IEEE Transactions on Electron Devices, vol. ED-17, pp. 586594, Aug. 1970. R. D. Lindsted and R. J. Surtry, Steadystate junction temperatures of semiconductor chips, IEEE Transactions on Electron Devices, vol. ED-19, pp. 4144, Jan. 1972. T. C. Hill, III, Differential amplifier with dynamic thermal balancing. U.S. Patent Number 4,528,516, July 1985.
[32] [33] [34]
[35]
[36] [37] [38]
216
Chapter 4
Coarse Quantizer
4.1 4-Bit Flash Quantizer

The topology of the coarse quantizer is based upon a ash converter (Fig. 4.1) with several modications to improve performance and reduce power dissipation. The basic ash A/D converter architecture is well-suited for low resolution applications such as the 4-bit coarse quantizer envisioned here, but does exhibit some characteristics which hinder performance of the 10-bit A/D converter including: high input capacitance, threshold perturbations due to comparator input current owing through the resistive reference ladder, and high power dissipation. These drawbacks are alleviated through two techniques, use of a differential reference ladder implementation and interpolation between comparator pre-ampliers. These methods are detailed in the next two subsections.
4.1.1 Differential Reference Ladder

In a typical ash A/D converter such as that depicted in gure 4.1 input bias current ows into each comparator of the array. This current ows through the resistive ladder thereby causing voltage uctuations which perturb the nominally equally-spaced reference voltages from their ideal positions [1]. This well-known effect is called reference bowing because the reference voltages vary from their ideal positions according to a parabolic or bowed pattern. A reference generation
218
Chapter 4 Coarse Quantizer
+Vref
Vin
Encoding Logic
-Vref
2 -1 Thermometer Comparators Code
Figure 4.1. Flash or parallel A/D converter topology.

scheme which simultaneously eliminates the reference bowing problem and provides buffering to reduce the capacitive loading presented by the comparator array relies on a differential signal being applied to differential emitter followers with resistive loads (Fig. 4.2) [23]. Here, the emitter followers provide buffering, however, the nodes at the bottom of the resistive ladders must be charged through the full ladder resistance. The distributed nature of this loading places a practical upper limit on the number of comparators which can be driven in this manner; however for the low resolution coarse quantizer, this settling time is adequate. Temporarily ignoring comparator bias currents, the kth comparator threshold occurs when its differential input is zero which implies that
Vk = VN k
(4.1)
219
V in
Q1
VN V0 R Tap V1 R Tap V2 VN 2 VN 1
I Ladder
C0
+
C1
+
C2
V2 CN 2
VN 2 R Tap VN 1 R Tap VN I Ladder V0 V1
+
CN 1
+
CN
Q2
V in
Figure 4.2. Differential reference ladder with comparators.

The node voltages V k and V N k can be dened in terms of the input voltage and the voltage drops across the resistive ladder:
V in V BE1 kV Tap = V in V BE2 ( N k ) V Tap
(4.2)
where V Tap is dened by V Tap = I Ladder R . If V BE1 = V BE2 , then equation 4.2 simplies to
2V in kV Tap = ( N k ) V Tap 2V in = ( 2k N ) V Tap V in = ( k N 2 ) V Tap

(4.3)
220
The last line of equation 4.3 indicates that the value of V in at which the input to the kth comparator equals zero is linearly proportional to k as desired. To take into account the effects of comparator input currents, consider the case if the comparator input is a differential pair. Then bias current ows only into the comparator terminal with the higher applied potential except when both terminals are at nearly the same voltage in which case the input bias current divides equally between the two terminals. This situation is depicted in gure 4.3 where the kth comparators inputs are assumed
V in V0 V1 V2 Vk 1 Vk Vk + 1 VN 2 VN 1 VN
Q1
Ib Ib Ib Ib Ib 2 Ib Ib Ib Ib Ib 2
Q2
V0 V1 V2 Vk 1 Vk Vk + 1 VN 2
V in
R Tap R Tap
R Tap VN 1 R Tap VN
I Ladder
I Ladder
Figure 4.3.
currents.
Differential reference ladder showing comparator input bias
to be balanced, and the base currents are labelled accordingly. The effective threshold voltage for
221
the kth comparator can be determined by again writing the equation which denes that threshold:
Vk = VN k
(4.4)
which can be expanded in terms of the ladder variables and the comparator input bias current to give
k
V in V BE1 kV Tap
p=1
RTap Ib ( k p + 1 2 )
Nk p=1
=
(4.5)
= V in V BE2 ( N k ) V Tap
RTap Ib ( N k p + 1 2 )
If V BE1 is again assumed to equal V BE2 , then equation 4.5 becomes
2V in = ( 2k N ) V Tap + R Tap I b V in = ( k
k2 ( N k ) 2 2
R Tap I b 2 N 2 2 ( k N + 2Nk k ) ) V Tap + 4 2 NR Tap I b N N = ( k ) V Tap + (k ) 2 2 2 NR Tap I b N ) = ( k ) ( V Tap + 2 2
(4.6)
The last line of this equation implies that the input voltage which denes the kth threshold increases linearly with k . The only difference between this result and that found for the simplied case with no comparator currents (Eq. 4.3) is that the proportionality constant changed from V Tap to V Tap + NR Tap I b 2 . This fact implies that in the differential ladder scheme presented, comparator input currents do not affect threshold linearity but merely increase the uniform spacing between thresholds by the quantity NR Tap I b 2 . The symmetry of the differential scheme can be better appreciated as depicted in gure 4.4 where the comparators tap diametrically opposed points along the two ladders drawn along the perimeter of a circle.
4.1.2 Interpolation
The conventional ash architecture was modied for use with the coarse quantizer by
222
Figure 4.4. Three dimensional depiction of differential reference ladder with

comparator connections. employing interpolation between adjacent comparator pre-ampliers to reduce power dissipation and capacitive loading. The interpolation utilized combines outputs from adjacent differential comparator pre-ampliers (Fig. 4.5) to create a virtual threshold for a comparator where no pre-
Preamps
V0 Vn VA VA
Comparators
C0 C1
VA VA
VB Vin VB
"1" C0 C1 C2 "0" Actual Thresholds Interpolated Threshold
V2 Vn-2
VB C2 VB
2Rtap I lad
Figure 4.5.
Interpolation between preampliers reduces loading on differential reference ladder and reduces power by halving the number of comparator pre-ampliers.
223
amplier differential input voltage equals zero [3], [4], [5]. This operation relies on the fact that the preamplier output transition from one polarity to the other occurs over some reasonable range of input voltage. Otherwise, the interpolation would be ineffective. By using this interpolation technique, the number of pre-ampliers used in the coarse quantizer was reduced from 15 to 8. This reduction minimizes power dissipation and reduces capacitive loading on the differential reference ladder signicantly. The differential ladder with interpolation can be visualized abstractly with the aid of gure 4.6 where pre-amplier connections to the reference ladder are drawn in black, and
+Vin
V0 V0 V2
-Vin
V2
Vn-2 Vn Vn
Vn-2
Figure 4.6. Differential reference ladder drawn to emphasize circular symmetry, and including reference to interpolated thresholds in grey.
virtual connections which are generated with interpolation are drawn in grey.
224
4.1.3 Layout and DAC Interface

The eight differential-pair pre-ampliers are laid out in a linear array with the differential ladder to their left (as oriented in gure 4.7). This array is most easily connected to the comparator array by abutment, so the 15 comparators must pitch-align with the 8 preampliers, implying that a high aspect-ratio is necessary for the comparator layout (Fig. 4.8). Each comparator cell also includes a differential pair serving as a current switch of the segmented reconstruction DAC. Locating the DAC current switches within the comparator cells greatly reduces wiring capacitance, and the direct connection between the ash comparators and the current segment switches provides for maximum switching speed by eliminating all intervening logic [6]. The complete coarse quantizer with differential ladder, interpolating pre-ampliers, and comparators with internal DAC switches is shown in gure 4.9.
References
[1] [2]
A. G. F. Dingwall, Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter, IEEE Journal of Solid State Circuits, vol. SC-14, pp. 926932, Dec. 1979. R. Petschacher, B. Zojer, B. Astegher, H. Jessner, and A. Lechner, A 10-b 75-MSPS subranging A/D converter with integrated sample and hold, IEEE Journal of Solid State Circuits, vol. SC-25, pp. 13391346, Dec. 1990. C. Lane, A 10-Bit 60 MSPS flash ADC, in Bipolar Circuits and Technology Meeting, pp. 4447, IEEE, Sept. 1989. C. W. Mangelsdorf, Parallel analog-to-digital converter. U.S. Patent Number 4,924,227, May 1990. D. A. Mercer, A 12-b 750-ns subranging A/D converter with self-correcting S/H, IEEE Journal of Solid State Circuits, vol. SC-26, pp. 17901799, Dec. 1991. T. Kamoto, Y. Akazawa, and M. Shinagawa, An 8-Bit 2-ns monolithic DAC, IEEE Jour-
[3] [4] [5] [6]
xcqprear
# ### #p ### p # p p p p # # # p # # ## p # p # p p # # # # p # # p p p # # # p ## ## # p # # # p pp # p # p # # p p # # # p # p p # # # # # # # p p p p # p # p p p # # #p# ## # # p p # # # p p pp ## ## # # # p pp## p p # p p p # # p # p pp# # # # # p p p p p p pp # # # ### # # # p # # # # # # p # # # # # ### p p pp# p # # # # # # p #p ## ## pp # # p p p# p # # p # # # p # ## # # # pp # p # # p # # p p pp # # # p # # p # # pp # # # # # p p # p p # # # p # p # # p # p # # # # p# # #p pp # p # # # # p # p # # # # # p # p p pppp p # # p# ppp p # # # # # p# p p # p # # p # pp # # # p p p # # # p p p pp p # p# # # # p # p # # # # p ppp p # pp # p p # pp #p p # # p#p # # # p# # # # # p p # p# p# # p # # p p # # # # p p # # p# p # # ## ## p pp p #p p p # # # # p# pp p # # p # ppp # ## # # # # # # p #p #pp ppp # # p# ## p pp # # pp p # pp p # # # # # p # # p p p # ## p# # p p # # pp ppp # # p p # # # #p # p p # # p p # # # # # # # p p # p # p# # p #p# p p # p p p # # ## # # p p #p p p # p# # # p p p # p p p p # p p # # # # # p # p # p# # # # p ppp p # # ## p ## # # p # # p# # ## p p p p # p# p pp## # ## p # # p p # p # p p # p pp# # # #p # p# p # p pp p # p pp # # # # # p # # p # # # # p pp pp # # # # # # p # #pp ppp # # # p # # # p ## # # # pp p p pp # p # p# pp # # # # # p# # p p # # # # p # p p # # pp # # # # p p p #pp p# # # # # p # # # # # # p p p p pp p # pp # p # # # # p # # # ## # # pp # p pp # # p p # # # p## p # p p # p # p# p# # pp pp # # p # # # # # p# p pp p p # ## # p# # p # # # # p # p # # # p # p # # p p# # # p # # # p ## ### p p # p# # # # p## # # p p# ## p
reference ladder.
nal of Solid State Circuits, vol. SC-23, pp. 142146, Feb. 1988.
Figure 4.7.
Coarse quantizer preamplier array driven by differential
225
226
cqltchvo
Figure 4.8. Coarse quantizer comparator with internal DAC current switch.
## pp ## p # # # p p p # # p p p # # p p # # # p p p # # # p # p p # p p # # # pp # #p # p p # p # p p pp p # # # p p # p # # # p p # pp # #
Coarse quantizer latch array with current segment inputs and differential DAC output.
ltchar
# #### # # # p ### # p p # # # p p # p p p p# p # p # # p p p p p p # # # # # ## pp# p# # # # ### # p# # p pp # #p #p #p # # p # p # p # p p# p ## p# # p ## # pp p p pp # # p ##pp# #p# p # p# ## p# pp # # p p # p # p p p #p p #p # # ## # p # # # # p p ppp #p## pp# ## p# # p# p # ## p ppp p# #p # p p pp pp ppppp ### # # # p ## ## p# # # # p p#pp # p # pp pp # p# # p # ## # p# # # # # # p## #p p# p##p p p p ## p p # p p p #p# ## # p# p# # # # p p ## #p pp ppp # # pp p# # p### pp pp# p p p### p #p#p pp # p # #p # p p p p# #p #p # ## p# pp# p# pp pp# p#p ### # # # # # # # #p ppp# ppp# p p pp # p p p # ## # #p p ## ## ## p pp# ## # # # # # # # # # p #pp# ## # p# pppp ### ## pp # p # p # # # # # # # ## p # p p #p # # # p p p p #p pp#p # # ## ## pp# p ppp # p p # p # # p # # p# # pp p p pp# #p p ## ## # # # # # # # pppp #pp ppp# # p # p pp # #p p#p p #p p### # pp # # # # # p pp## # # # p p#### # p p p# # p # p# p p p p pp # pp pp #p # p # # # ## # p# ppp ## p pp###p #p p # ## pp# ## ## # p # # # ## pp# # #p# # pp pp # p p ## p# p p# # p pp # # p # # # #p# # # ## # p p# # # p p p# p p #p## ## p p # # # ppp p#p # # # ###p# p# p# # p pp pppp# ppppp# pp pppp ## # p p pp # # p ## pp ## p # # # # # # # ## # #ppp p# pp # pp ## pppp pppp #p # ### # p # # #pp p p p p pp # ## p # p p # # # p p # #p p p# pp p# # p p# # ## ## # # p# pp# ##p ### ## # p #p #pp p# # # ## # # ppp #pp# ppp# ##p p#p # # # ## # p p# pp p p#p # # # p# # # # ## p # # #p # p # # p#p# # # # p pp pp p # #p p # p# pp # p p #p # p#p p# # p#p pp ## ## # p # ## #p p # pp# ##p #p ## # p# # ## ## # # p# # p #p ppp pp p # ## ## p p p# p ppp # # p #p# # # p # # p #p# # p p# pp# ## p# #p# # p p # # p # pp p pp p# pp## # p p # p# p#p # ## # p# #p # # p pp # pp # #p p# # p## #p # #p p # # # # p ## # pp pp pp# ##p pp## p# pp # # p ## #p # # p# # ## # # p p # # p# p ## p # p # # #p p p ## # p p# # p #p p p p p p # p p ### p# p ppp # p #p ## p # p # p # # # # p #p p # p p # ## ### # # ##p# p # #p ppp pppp # p#p p p p p # #p pp # p # # p p ## pp # p p p# # # # #p# p # pp pp# p# pp p ## ### ###p #p p # # p p pp # ## # p p p p # # p # p#p ## p p # # ### ### ## p p p # p # p ## # p pp p p # p# p#p p p# #p p ## p p# # ## ## # # pp# ppp# p # #p ## p # p pp pp # # ## #p ## p#p # # p p ### p p # # pp p#p ##p# p p p pp # #p p # #p ## p# ## # # # p # pp# pp #p # # p # # p# p # p# p# #pp # p #p # # p # p #ppp # p# pp# # # # #p ppp ## # p# # p# # p p p # ## pp #p p # pp # #p # p pp p p # # p p pp p# pp# pp# # # # # p p p # p pp p # ## ## ## # pp #p p## # # # p pp # pp p # ### # p# p# # # # # # p p # pp p # pp p p # p # # p ppp p## #p# ## ## # # # p ppp # ## #p p # p# #p pp ## #p # pp pp ## p p # p pp p# # p #p## # #p#p ## p# #p # p # ## # p # # p# # #p # #p p pp p pp# p#p# p#p p# ## # p p ppp p#p # # # # pp p# ## ## ## # p# p p# #p ## pp pp p p# # #p p ppp pp p ## ##p# # # p# #p # ## # p #p pp #p p#p ## # ## # #p# ##p pp# p# # # p# p#p p#p p p p p# ## p p p# p#p p pp ##p p p p pp #p ##p p# pp p # pp #pp #p# ## # p# pp p #p p # p # ## p # #p p#p # p# pp # p p #p # # # # p p # ## p# p# # p p #p #p p# p # # p #p ##p # p# # # p p# # p p# p ppp pp pp pp p
Figure 4.9.
227
228
Chapter 5
DigitaltoAnalog Converter and Residue Amplier
The digital-to-analog converter within the 10-bit ADC produces an analog signal proportional to the digital output from the coarse quantizer suitable for subtraction from the ADC input signal. Because a coarse replica of the input signal is reconstructed at the DAC output, the internal D/A converter is frequently termed a reconstruction DAC. The subtraction of the reconstructed signal from the input occurs within the residue amplier generating a result which is then processed by the ne quantizer to complete the digitization. To ensure adequate linearity of the ADC, both the D/A converter and the residue amplier must perform their respective functions with linearity errors below one 10-bit LSB. Since errors in these two components form only a fraction of the total error affecting A/D operation, actual DAC and residue amplier errors must be well below this level. In addition to these accuracy requirements, both components must operate very rapidly while dissipating low power. The architecture and circuit implementations of the D/A converter and residue amplier are discussed in detail next.
5.1 Segmented Approach

The most important requirement for the reconstruction DAC is that its linearity be commensurate with 10-bit operation. Additionally, the DAC delay-time, as measured from a change
230
Chapter 5 DigitaltoAnalog Converter and Residue Amplifier
in its digital input until its analog output has settled adequately, must be minimized; especially since in the unconventional timing arrangement employed (Figs. 2.15 and 2.16) the DAC must track dynamically changing digital inputs. Since the coarse quantizer comparator bank generates a thermometer code output, a DAC architecture which directly interfaces with this format is desirable. Several architectures were investigated for suitability as reconstruction DACs given the aforementioned considerations. The R-2-R ladder DAC [1], [2], perhaps the most commonly implemented D/A converter architecture, provides a very efcient solution since only one current source is required per bit. However, the R-2-R topology exhibits high sensitivity to resistor mismatch and is therefore unsuitable for the present application. D/A converters employing dynamic element matching techniques offer excellent linearity and intolerance to device mismatches [3], [4], [5], [6], [7] but generally require high power supply voltages and large off-chip decoupling elements. Neither of these special requirements can be supported in the present design so dynamic matching methods were abandoned. Current copier techniques offer high accuracy and potentially low power dissipation [8], [9], but require CMOS devices which are unavailable in the semiconductor process used here. A fully-segmented DAC architecture provides very low sensitivity to device mismatches [10], [11] along with the simplest possible interface to the thermometer code output from the coarse quantizer and was therefore selected as the architecture for the reconstruction DAC. The segmented implementation of the reconstruction D/A converter exhibits 4-bit resolution and so consists of 15 equally weighted current segments which are switched under control of the thermometer code output from the coarse quantizer (Fig. 5.1). Each 250 A segment current is set by a reference voltage driving the base of a twice minimum-size transistor stabilized by a 400 mV degeneration voltage. The ballast resistance necessary to establish this degeneration is 1600 implemented by an 800 m 25 m NiCr thin-lm resistor with
50
sheet resistance. These resistors were designed to be very large to minimize
mismatches along the segment array [12]. The anticipated mismatch of such a resistor, R R , in Tektronix SHPi process is approximately 0.1%, typical of many modern semiconductor processes [13], [11], [10].
5.2 Effects of Mismatches
231
IOut
IOut
1 Wiring Matrix 10 A=2 Thin Film (NiCr) Resistors 800 m
2 3 4 5 6 7 8 9 10 11 12 13 14 15 3 14 7 5 12 1 8 15 4 11 9 2 13 6 VRef R = .1% R 25 m + 400mV 1600
250 A
Figure 5.1. Fully-segmented current-output reconstruction DAC.

Current segment mismatches arise from both random and deterministic phenomena. Deterministic errors are caused largely by asymmetrical layout of the current segments. For example, if thermal gradients exist across the segment array the equivalence between the segment currents will be destroyed. Likewise, if the current segments see unequal wiring resistance to ground, individual currents will be perturbed. These types of errors must be addressed during layout but are not considered further here. Three sources of random error degrade segment matching: mismatches in transistor saturation current (which also manifest themselves as V BE mismatches when devices carry equal currents), mismatches in transistor current gain, , and mismatches in current source degeneration resistance. Straightforward analysis [14] indicates that for degeneration voltages a few times larger than the thermal voltage, V T , or more, the mismatch in degeneration resistance dominates the other error sources. Since this condition holds in the DAC designed here, where the degeneration voltage is 400 mV, the relative current source mismatch is approximated by
232
the relative degeneration resistor mismatch. That is I I R R , where I represents the segment current and R the degeneration resistance. The effect of current source mismatch errors on reconstruction DAC and A/D performance can be assessed via Monte Carlo simulation wherein current segment values are selected from an assumed random distribution, and the resultant DAC output levels or A/D thresholds are calculated. Simulation of DAC linearity using this technique led to gure 5.2 which plots DAC yield (assuming
100 90 80 70 60 Yield (%) 50 40 30 20 10 0 0.0
Resolution = 4 bits Peak INL = 1/2 10-bit LSB Number of Samples = 200
0.1
0.2
0.3 0.4 0.5 0.6 0.7 Current Segment Mismatch (%)
0.8
0.9
1.0
Figure 5.2. 10-bit yield for a fully-segmented DAC with 4 bit resolution versus current segment mismatch assuming maximum INL is 1/2 LSB.
peak INL must be below 1/2 of a 10-bit LSB) versus the DAC current segment mismatch, I I . This gure indicates that yield is virtually 100% for I I < 0.2% , and signicant degradation occurs for I I 0.3% . A more pertinent measure of the impact of current segment mismatch is its effect on A/D converter SNR shown in gure 5.3 along with ADC yield (assuming minimally acceptable SNR is 59 dB). This gure indicates that SNR degradation is minimal when
I I < 0.1% and approaches 1 dB when I I = 0.2 % . Therefore, the above simulations
233
100 90 80 ADC Yield at 59 dB (%) 70 60 50 40 30 20 10 0 62 61 60 Mean SNR (dB) 59 58 57 56 55 54 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 DAC Current Source Matching (%) 0.9 1.0
n1=5 n2=6 n1=4 n2=7
n1=5 n2=6 n1=4 n2=7
segmented DAC current source mismatch for both 4-7 and 5-6 partitioning. indicate that DAC current source mismatches should not degrade A/D converter SNR signicantly since the resistor matching expected from the Tektronix process is quite good,
I I R R = 0.1% . However, the preceding simulations assume erroneously that segment

errors are uncorrelated with each other. In reality, a strong spatial correlation exists among resistors, implying that if one resistor deviates from the norm, neighboring resistors tend to do so in the same fashion [11]. Such spatial correlation degrades DAC INL from predicted levels. To counteract this
234
phenomenon, a wiring matrix added between the DAC current sources and the current switches (Fig. 5.1) randomizes the apparent location of current segments by ensuring that physically proximate segments are not connected to current switches which are located near to each other. An optimum ordering for this scrambling procedure was developed by Conroy [11]. Others have devised scrambling sequences to cancel the effects of current source errors where the mismatches are assumed to follow a linear or quadratic function of distance from the array center [15], [16], [17], [18], [19], [20], but the technique proposed by Conroy gives superior results and was used here. When the current segments are thus scrambled, the Monte Carlo analysis described earlier accurately predicts DAC and A/D converter performance degradation due to current segment errors. Therefore, random errors aficting current source values such that I I = 0.1 % should not signicantly degrade the SNR of the 10-bit A/D converter.
5.3 Layout Considerations

To combat the potential deleterious effects of unforeseen deterministic errors such as thermal gradients, three versions of the DAC array were implemented (and consequently three versions of the A/D converter). The rst layout of the DAC current segments (Fig. 5.4) corresponds to the arrangement just described. The connections from the DAC switch array located in the coarse quantizer enter the layout at the top left in sequential order, and as can be seen are connected to the individual current segments in an apparent haphazard ordering. This ordering is actually the optimum arrangement for removing spatial correlations alluded to earlier. The lines at the top left of the layout connect seamlessly to those in the layout of the coarse quantizer (Fig. 4.9 at top right). The second DAC current segment layout is intended to cancel linear thermal gradients across the array. Therefore, two identical current source arrays (each with one half the required current) are connected in parallel and physically arranged so that the centroid of each pair of sources connected in parallel is located at the center of the array. Therefore, if the current segments are numbered sequentially from 1 to 15, and the two sub-arrays are designated A and B such that sources 1A and 1B are electrically connected in parallel, then moving from one end of the joint array to the other, the sources encountered are 1A,15B,2A,14B,
,14A,2B,15A,1B
. In the
layout of this current source array (Fig. 5.5), the wiring matrix also enters at the top left and scrambles the effective locations of the sources to minimize the effects of spatial correlation. The third DAC current source array is identical electrically to the rst, but the degeneration
# # # # ####### # # # # # # ##### # # ##### # # # # # # # # # # pp#p # # #p #pp ppp# pp#p##p pp#p#p # # ## ppp ppp# pp#p## p#p p##p# #p#pp p#p## pppp ppp #p#p ## #p#p #pppp ppppp ppppp #pp# ## #p # ## ## # # # # ###### # ## # # ## # # # #
snorcim 2911 x 866 :eziS yarracad
paid to enable laser trimming of resistors [21], [22], [23]. of the array (Fig. 5.6) is signicantly larger than the nominal array and indicates the area penalty resistors are larger and include special tabs to facilitate laser trimming if necessary. The overall size
Figure 5.4.
matrix at top.
Segmented DAC current source array with scrambled wiring
5.3 Layout Considerations
235
## # # # ### # ## ## # # #### # ## # # # # # # # #### # ###### ## # # # # # # # # ppppppppp # # ## #### #### ##### ###### ##### ### #### ######## ###### # # # # # # # # # # # # # ## # # ## # # ## ## # # # ### ## ## ### #### ## # # ppp# pppppp ppppppp pppppppp# pppppppppp pppppppppp pppppppp ppppp ### ###### ###### ##### ### # ## # # #p ppp pppppp ppppppp pppppppp ppppppp ###pp ppppp ppp#pp #ppp #####pp ###### ### ### #pp##p#p #pp##p# pp### #### ## # ### # # # # # ## # ## ## ###### # # ## # ## # # ## # # # # ########## ## #
236
5.4 Residue Amplier

snorcim 2511 x 619 :eziS
layout.
The purpose of the residue amplier is to subtract the analog output of the reconstruction
Figure 5.5.
Segmented DAC current source array with common centroid
23racad
# # # ## ### # ##### # ##### ## #### # # # # # # # # # # p# p ppp ppppppppppp ppppppppppp ppppppp ppppppp ## ## #### # # p pppp pppp ppppppppp# pppppppppp pppppppppp# ppppppppp# ppppppp### pppppp ## # ### #### pp pp pp # ppppppppp ## # ####pp##p# #### #p#### # #### ## # # # # ## # ## # ####
Figure 5.6. Segmented DAC current source array with trimmable layout.
snorcim 6531 x 6321 :eziS mirtcad
signals. In this method, the transconductance operation must exhibit linearity commensurate with linear transconductance operation followed by straightforward subtraction of the two current performing the required transconductance and current-mode subtraction (Fig. 5.7a) relies upon a to convert the T/H output signal from a voltage to a current before subtraction. A typical circuit for DAC generates a current output, and since current-mode subtraction is inherently fast, it is desirable performed with an open-loop circuit which achieves the requisite linearity. Since the reconstruction DAC from the held signal out of the input T/H. To ensure very fast settling, this operation must be
5.4 Residue Amplifier
237
238
+Vout+Vin +Vin DAC -Vin
+Vout-Vin
DAC
(a)
Vout
Residue Waveform
(b)
Vin
Coarse quantizer Thresholds
(c) Figure 5.7. Residue amplier implementations. (a) Typical approach using transconductance cell and subtracting currents at output. (b) Improved approach subtracting currents at transconductor emitter.
10-bit operation. An improved technique (Fig. 5.7b) subtracts the signal currents at the emitters of the transconductance amplier taking advantage of the reduced dynamic range of the signal at this location. Because the current subtraction takes place in the degeneration resistor of the transconductance stage, the signal current modulating the V BE of the input transistors is reduced by a factor of 16 compared to the previous case. This reduction occurs because the DAC output current is a close approximation to the transconductance current resulting in a current waveform similar to that shown in gure 5.7c. The reduction in dynamic range reduces distortion signicantly since according to equations 3.52 and 3.53, HD 2 is proportional to the signal amplitude, and HD 3 is proportional to the square of the signal amplitude. Therefore, the improved residue amplier reduces HD 2 compared to the conventional case by 20 log 16 = 24dB , and the HD 3 by a dramatic 20 log 16 = 48dB . In addition to the improved linearity offered by the new approach,
2
[2]
[1]
resampar Size: 542 x 382 microns
References
Figure 5.8. Residue amplier and its replicas.

239
D. J. Dooley, A complete monolithic 10-b D/A converter, IEEE Journal of Solid State Circuits, vol. SC-8, pp. 404408, Dec. 1973.
subtraction operation. The physical implementation of the residue amplier is shown in gure 5.8.
the power dissipation is reduced compared to the conventional topology since the bias current of
the DAC is also used by the transconductance stage. By selecting the load resistors of the residue
amplier to be twice the value of the degeneration resistor a gain of 4 is achieved along with the
B. E. Amazeen, P. R. Holloway, and D. A. Mercer, A complete single-supply microprocessor-compatible 8-bit DAC, IEEE Journal of Solid State Circuits, vol. SC-15, pp. 1059
# p # #p# # # # # # # # # # # p # # p # ## # #p p ## # # # p # # p# # # # ## # # # # p p # # # # # p p # p p # # # # # # # p # p # # # p # p# # # # ##p# # #p# # # # p # # p p ### # p # # p # #p # # p # # p p# # # # # p ## # #p # # pp pp #p # ##p #p# # p # # ### # p # p # ### # p# # ## # # pp # # p ## # p #p # # # # p # # p # ## p # ## # p p #
240

1070, Dec. 1980.
[3] [4] [5] [6]
R. J. van de Plassche, Dynamic element matching for high-accuracy monolithic D/A converters, IEEE Journal of Solid State Circuits, vol. SC-11, pp. 795800, Dec. 1976. R. J. van de Plassche and D. Goedhart, A monolithic 14 bit D/A converter, IEEE Journal of Solid State Circuits, vol. SC-14, pp. 552556, June 1979. R. J. van de Plassche and H. J. Schouwennars, A monolithic 14 bit A/D converter, IEEE Journal of Solid State Circuits, vol. SC-17, pp. 11121117, Dec. 1982. E. C. Kwong, G. L. Baldwin, and T. Hornak, A frequency-ratio-based 12-bit MOS precision binary current source, IEEE Journal of Solid State Circuits, vol. SC-19, pp. 1029 1037, Dec. 1984. H. J. Schouwenaars, E. C. Dijkmans, B. M. J. Kup, and E. J. M. van Tuijl, A monolithic dual 16-bit D/A converter, IEEE Journal of Solid State Circuits, vol. SC-21, pp. 424429, June 1986. H. J. Schouwenaars, D. W. J. Groeneveld, and H. A. H. Termeer, A low-power stereo 16bit CMOS D/A converter for digital audio, IEEE Journal of Solid State Circuits, vol. SC23, pp. 12901297, Dec. 1988. D. W. J. Groeneveld, H. J. Schouwenaars, H. A. H. Termeer, and C. A. A. Bastiaansen, A self-calibration technique for monolithic high-resolution D/A converters, IEEE Journal of Solid State Circuits, vol. SC-24, pp. 15171522, Dec. 1989. J. A. Schoeff, An inherently monotonic 12 bit DAC, IEEE Journal of Solid State Circuits, vol. SC-14, pp. 904911, Dec. 1979. C. S. G. Conroy, W. A. Lane, and M. A. Moran, Statistical design techniques for D/A converters, IEEE Journal of Solid State Circuits, vol. SC-24, pp. 11181128, Aug. 1989. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, Matching properties of MOS transistors, IEEE Journal of Solid State Circuits, vol. SC-24, pp. 14531440, Oct. 1989. G. Kelson, H. H. Stellrecht, and D. S. Perloff, A monolithic 10-b digital-to-analog converter using ion implantation, IEEE Journal of Solid State Circuits, vol. SC-8, pp. 396 403, Dec. 1973. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. John Wiley and Sons, second ed., 1984. P. H. Saul and J. S. Urquhart, Techniques and technology for high-speed D-A conversion, IEEE Journal of Solid State Circuits, vol. SC-19, pp. 6268, Feb. 1984. T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, An 80MHz 8b CMOS D/A converter, in International Solid State Circuits Conference, pp. 132133, IEEE, Feb. 1986. T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, An 80-MHz 8bit CMOS D/A converter, IEEE Journal of Solid State Circuits, vol. SC-21, pp. 983988, Dec. 1986. Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, A 10-b 70-MS/s CMOS D/A converter, in 1990 Symposium on VLSI Circuits Digest of Technical Papers, pp. 57 58, IEEE, 1990.
[7]
[8]
[9]
[10] [11] [12] [13]
[14] [15] [16]
[17]
[18]

[19] [20] [21] [22]
241
Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, A 10-b 70-MS/s CMOS D/A converter, IEEE Journal of Solid State Circuits, vol. SC-26, pp. 637642, Apr. 1991. F. G. Weiss, A 1 Gs/s GaAS DAC with on-chip current sources, in GaAs IC Symposium, pp. 217220, IEEE, 1986. J. J. Price, A passive laser-trimming technique to improve linearity of a 10-bit D/A converter, IEEE Journal of Solid State Circuits, vol. SC-11, pp. 789794, Dec. 1976. K. Kato, T. Ono, and Y. Amemiya, A monolithic 14 bit D/A converter fabricated with a new trimming technique (DOT), IEEE Journal of Solid State Circuits, vol. SC-19, pp. 802807, Oct. 1988. J. Shier, A finite-mesh technique for laser trimming of thin-film resistors, IEEE Journal of Solid State Circuits, vol. SC-23, pp. 10051009, Aug. 1988.
[23]
242
Chapter 6
Folding Fine Quantizer
6.1 Concept of Folding

As described in chapter 2, a feedforward multi-stage A/D converter gains efciency by partitioning an N-bit quantization into a number of lower-resolution quantizations. In such a converter (Fig. 6.1a) an n1-bit coarse quantizer digitizes the input signal with low resolution, and applies the resultant codeword to a reconstruction DAC. The analog output of the DAC is then subtracted from the original input to form a residue signal (Fig. 6.1b) which is quantized by an
n2-bit ne quantizer. The advantage of this approach arises because the combined complexity of
the n1-bit coarse quantizer and the n2-bit ne quantizer can be far less than the complexity of a single N-bit quantizer. The object of a folding quantizer is to form the residue signal with simple analog circuits thereby obviating the need for the coarse quantizer, DAC, and subtracter components of gure 6.1a. In such an implementation (Fig. 6.2), the low dynamic-range residue signal generated by the analog folding circuit directly drives the ne quantizer. Because of the periodic nature of the residue signal; however, the digitized output from the ne quantizer is ambiguous, and a coarse quantizer is still necessary to ascertain in which period of the folding circuits transfer characteristic the quantizer input signal lies. The input-output characteristic of the analog folding circuit can be parameterized by the number of piece-wise linear segments, or folds, which it contains. This parameter, abbreviated F , determines the resolution of both the coarse and
244
Chapter 6 Folding Fine Quantizer
Vin
Residue
ADC
N2 Fine Bits
ADC N1 Coarse Bits Residue
DAC
(a)
Vin 2 Coarse Quantizer Thresholds

N1
(b) Figure 6.1. Architecture of feedforward quantizer.
Vout
Vin
Vin
LSBs MSBs Coarse Quantizer (F Thresholds) Digital Encoder N-bit Output
Figure 6.2. Folding A/D converter architecture. Analog folding with F folds
reduces ne quantizer resolution to 2 F . ne quantizers required in a folding A/D converter (Fig. 6.3). Since the coarse quantizer requires F
N
Fine Quantizer (2 /F Thresholds)
Analog Folding Circuit with F Folds
Vout
2 Fine Thresholds
N2
6.1 Concept of Folding
245
VFS
VFS
2N Thresholds Comparator Array Input Signal Flash Converter
2N Thresholds Flash Converter
Folding Converter
Folding Converter
VFS/F 2 /F Thresholds 0 0 Fold 1 Fold 2 Fold F-1 Fold F VFS

N
VFS/F 2 /F Thresholds 0 0 Fold 1 Fold 2 Fold F-1 Fold F VFS

N
A/D Input Signal
A/D Input Signal
(a)
(b)
Figure 6.3.
Reduction in dynamic range seen be comparator array for (a) sawtooth and (b) triangle folding characteristics.
N
thresholds, its resolution is n1 = log 2 F while the ne quantizer requires 2 F thresholds so its resolution is n2 = log 2 ( 2 F ) = N n1 .
N
6.1.1 Linear Folding Circuits

Folding A/D converters based on the architecture of gure 6.2 would be possible if simple analog circuits could easily realize the piece-wise linear input-output characteristics indicated. However, because of the discontinuities in the folding transfer function, these types of characteristics are inherently difcult to realize. Several implementations have been developed which approximate the triangle wave folding characteristic of gure 6.3, but each has signicant drawbacks. For example, the circuit of gure 6.4 [1], [2] based on the translinear principle, offers a near ideal approximation to a triangle wave folding characteristic. However, the differential input voltage varies by 2 diode drops for each fold within the transfer function. So if eight folds are desired, the differential input voltage range is 16 V D 16 0.7 = 11.2V . This voltage swing is unacceptably large for the low-power, high-frequency application considered here. A second folding circuit which approximates the ideal triangle wave depicted in gure 6.3 is shown in gure 6.5 [3]. This topology also approximates the triangle waveform quite well, but also suffers from the
246
(4-)I
Iout Iout
Iout Iout I
1 2
3 4
-I
Figure 6.4. Translinear-based current-mode folding circuit.

large input swing requirement which plagued the rst circuit. In addition, this implementation exhibits a large common mode output current upon which the differential output current is superimposed. In practical applications with limited power supply voltages, this common-mode component could prove problematic. Generally, circuits with discontinuous input-output characteristics are difcult to realize and are not amenable to high-speed applications. Therefore, folding converters which do not rely upon piece-wise linear folding functions prevail.
6.2 Sinusoidal Folding
247
I out
I out
4I
4I
(4- )
I out - I out
1 2
3 4
-I
Figure 6.5. Current-mode folding circuit using cascodes.

A folding A/D converter based upon a periodic, but not piece-wise linear folding function can be developed if the non-linear function is well behaved which in this context means that the characteristic is periodic and does not saturate [4], [5]. A sinusoidal folding function (Fig. 6.6) serves as an apt example. In this case, the folding characteristic resembles the triangle-wave depicted in gure 6.3b; however, the output signal from the folding circuit is not a linear function of the input. Therefore, the ne quantizer must contain thresholds which are not uniformly spaced, but which are located according to an inverse-sine law. This threshold placement would be very difcult to achieve in practice, but a simple alternative lies in generating many sinusoids, uniformly shifted in phase with respect to each other (Fig 6.7). In this arrangement, the ne quantizer consists of an array of comparators, each with its reference input grounded so that the quantizer thresholds correspond to the zero-crossings of the sinusoids. Since the sinusoids are equally-spaced in phase, their zero-crossings are equally-spaced along the analog input range, and the quantizer thresholds are located correctly. Generating the phase-shifted waveforms with an array of sinusoidal folding
248
Vout
Vin
Vin
Digital Encoder Coarse Quantizer

Figure 6.6.
A folding function which is not piece-wise linear. The transfer function shown is sinusoidal for convenience but could be any non-saturating, periodic function.
In-Phase
=0 Digital Encoder
Vin
= 90/
Quadrature = 90
Figure 6.7. An array of phase-shifted, non-linear folding blocks with comparators detecting zero-crossings can circumvent the need for an inversesine quantizer.
circuits would be very inefcient, but a simplication of the scheme depicted in gure 6.7 obviates the need for this type of redundancy. Instead, only two quadrature sinusoids are generated, and the remaining signals are obtained by linear superposition between the rst two. A simple technique for
Inverse-Sine Fine Quantizer
Sinusoidal Folding Circuit
Vout
249
achieving the superposition utilizes resistive interpolation (Fig. 6.8). By appropriately selecting the
In-Phase
=0 Interpolation
=0 90/ Digital Encoder
Vin
Q I Quadrature = 90
= 90
Figure 6.8.
Linear superposition implements non-uniform interpolation to generate multiple sinusoids equally-spaced in phase from two quadrature sinusoids.
interpolation resistors, any desirable phase angle, , can be generated. The folding quantizer architecture presented in gure 6.8 is simple and potentially very efcient; however, practical circuits must be available to generate the two quadrature sinusoids, and the interpolation scheme must be easily implemented and robust. These two issues are discussed in the following sections.
6.2.2 Sinusoidal Folding Circuits

Several circuits with sinusoidal transfer functions were investigated for suitability in folding quantizers. The rst such circuit considered (Fig. 6.9) [1], is based on the translinear principle and offers the advantages of simplicity and low common-mode output current for a given differential output. However, as in the case with the previous translinear-based folding circuits, the voltage drive required to obtain an input-output characteristics with 8 folds (or equivalently 4 periods) is on the order of 5 V. This voltage swing is not compatible with the quantizer being designed here. Therefore, the circuit of gure 6.9 was rejected. A modication of this folding circuit requires a differential current drive rather than a differential voltage drive (Fig. 6.10) [2], but still demands a very large voltage swing at its input to generate several folds. A different approach which does not require large voltage drive (because it is not a translinear circuit) is depicted in gure 6.11
250
Vin+
Vin-
I out I out
IE
I out - I out IE Increasing IR

2 -8 -6 -4 -2 4 6 8
Vin+ - VinIR
-IE
Figure 6.9. Translinear sinusoidal folding circuit with voltage drive.

[6], [7]. This circuit relies on the hyperbolic tangent transfer function of a voltage driven bipolar differential pair to approximate a sinusoid. By selecting the voltage separation between the references V 1 , V 2 , V 3 , and V 4 appropriately, a good approximation to a sinusoid may be made over a few periods. An appropriate voltage separation is a few times the thermal voltage, V T , so the total input voltage swing is on the order of 1 V for an 8-fold circuit, an acceptable value. The circuit of gure 6.11 suffers some important drawbacks. The input is single-ended so, as in the case of the ash coarse quantizer from chapter 4, bias currents owing into the folding circuits differential pairs will perturb the apparent reference voltages thereby distorting the desired shape of the sinusoid. Additionally, the output current from the folding circuit consists of a large common-mode component with only a small differential component. Therefore, operation under limited power supply voltage ranges poses biasing problems. Lastly, if many folds are desired, mandating many differential pairs in the folding circuit, then the capacitive loading on the output node becomes large adversely affecting settling time. Some of these drawbacks are overcome by the circuit of gure 6.12 [24], [9], [10], [12], [12], [13] which uses a wired-OR conguration at the differential pair
251
2R 0.7R
2.4R R
3.4R R
2.4R 0.7R
2R
(1- )I
I out I out
IE
I out - I out IE Increasing IR
1/4
1/2
3/4
-I E
Figure 6.10. Translinear sinusoidal folding circuit with current drive.

outputs to reduce the common-mode output signal and to provide buffering. This circuit still suffers from the threshold perturbing effects of a single-ended reference scheme. To eliminate this error source, the sinusoidal folding circuit of gure 6.13 was developed. This circuit incorporates a differential reference ladder identical to that described in chapter 4 [14], [23], [13], [16]. Therefore, errors due to input bias current owing through the resistive reference ladder and into the differential pairs comprising the folding circuit are eliminated. Cascode devices are employed to reduce the impedance at the common collector node loaded by signicant device capacitance, and de-bias resistors connected from the cascode emitters to the positive supply absorb most of the bias current drawn by the differential pairs in the folding circuit. Owing to the low input impedance of the cascode devices, only a small amount of signal current ows into the de-bias resistors. Therefore, the output signal has a large differential-mode component and a small common-mode component as desired. Two extra differential pairs are added to the folding circuit at the extremes to ensure that each of the 9 remaining pairs in the circuit experience symmetric effects from nearestneighbor differential pairs. This technique maintains the delity of the sinusoid at the extremes of
252
RL
RL
+ Vout V1 V2 V V3 V V4 V
Vin I I I I
Vout
IRL
V1
V2
V3
V4
Vin
-IR L
Figure 6.11. Folding circuit based upon hyperbolic tangent transfer function
of voltage driven differential pairs. the input range. Notice that the phase of the resulting waveform can be controlled by shifting the positions along the reference ladder to which the folding circuit connects. In this way, a second folding circuit whose output is in quadrature with the rst can easily be constructed. A signicant drawback of this folding circuit is its dependence on temperature. Since the gain of the differential pairs within the circuit vary with temperature, and since the output waveform is not an exact sinusoid but an approximation to one, the shape of the output waveform will change slightly with temperature. This changing shape introduces errors into the resulting quantizer transfer function which will be discussed in detail in the next sub-section.
6.3 Non-uniform Interpolation
253
RL
RL
RL
RL
RL
+ Vout V1 Vin I Vout I I I V2 V V3 V V4 V
IRL
V1
V2
V3
V4
Vin
-IR L
Figure 6.12. Folding circuit based on wired-OR interconnection.
Rl +Vout-
Rl
Ip Vin+
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Ip
Ip Im
Rt
Rt
Rt
Rt
Rt
Rt
Rt
Rt
Rt
Rt
Im
Rt
Rt
Rt
Rt
Rt Vout IpRl
Rt
Rt
Rt
Rt
Rt
Vin-
-7
-6
-5
-4
-3
-2
-1 -IpRl
Vin+ - VinIm Rt
Figure 6.13. Fully-differential sinusoidal folding circuit with differential reference ladder, overow compensation, and common-mode de-bias circuitry.
254

The interpolation scheme depicted in gure 6.8 is conceptually straightforward and can be
implemented with a simple resistive ladder as depicted in gure 6.14. Here differential emitter
V5 V6
V4
R2 R1 R1
Q
V3
R2 R2 R1
I
R1 R2
R2 R1
V2 V1
R2
R1 R1 R2 R2
Figure 6.14.
Differential non-uniform interpolation ladder generates sinusoids equally spaced in phase from quadrature inputs. Distortion is minimized due to symmetry of circuit enabling use of simple, low-power emitter follower buffers.
followers buffer the quadrature signals output by the two folding circuits discussed above. The quadrature waveforms are termed the In-phase signal and the Quadrature signal and are therefore labelled I and Q in the schematic. The interpolation ladder is redrawn along with a phasor diagram and plots of interpolated waveforms in gure 6.15 to emphasize the analogous representations. Note the similarity, both physical and conceptual, between the electrical representation and the phasor representation. Comparator differential inputs connect to points diametrically opposed on the resistive ring. Also, the symmetry of this conguration reduces the effects of distortion in the emitter follower buffers. When I = I , Q = Q so that signal current ows from the Q node, through the interpolation ring and into the Q node, but the voltages at I and I remain unperturbed so that no
255
V5 V6
V4
R2 R1 R1
Q
V3
R2 R2 R1
I
R1 R2
R2 R1
V2 V1 V5 V6
V4
Q
V3 V2
V1
R2
R1 R1 R2 R2
(a)
VOut 0 -VFS
(b)
VIn VFS
(c) Figure 6.15. (a) Differential non-uniform interpolation ladder. (b) Phasor representation of quadrature and interpolated signals. (c) Corresponding voltage waveforms.
threshold variation results. Similarly, when I = Q , then I = Q so that signal current owing from the I node equals that owing from the Q node, and signal current owing to the I node equals that owing to the Q node. Therefore, resultant V BE modulation in the emitter follower buffers cancels and, again, no threshold perturbation results. The resistor values required to obtain interpolated sinusoids equally-spaced in phase from two quadrature waveforms can be found by simple trigonometric identities. The resistor spread necessary is about 2:1, and sensitivity of ADC threshold placement to resistor errors is quite low. When temperature is varied, the shape of the incoming quadrature signals changes leading to threshold error. Simulations of this effect shown in gure 6.16 indicate that threshold errors are nearly non-existent at room temperature as desired, but increase for both temperature extremes. Maximum threshold error occurs when temperature is -55 C reaching a magnitude of
approximately 6% of an 8-bit LSB.
256
8 6 4 DNL (% of 8-Bit LSB) 2 0 -2 -4 -6 -8

T=125 T=100 T=75 T=50 T=25 T=0 T=-25 T=-55
16 Interpolation Position
32
Figure 6.16. Threshold error at interpolated thresholds.
6.4 Folding and Interpolating A/D Converter

The components required to implement the folding quantizer block diagram depicted in gure 6.8 have been demonstrated; however, several additional functions must be added to form a useful circuit. Figure 6.17 includes all necessary circuitry for a 7-bit folding quantizer. The input signal (assumed differential) drives a differential reference ladder attached to two folding circuits which generate quadrature differential sinusoidal outputs called I and Q. These signals are applied via emitter follower buffers across a differential non-uniform interpolation ladder to generate an array of equally phase-shifted sinusoids. The array of sinusoids must be digitized and encoded. Additionally, a coarse quantizer must determine within which fold of the sinusoidal transfer characteristic the input signal lies. The coarse quantizer is sometimes called a cycle-pointer because it identies which cycle of the folding characteristic the input signal occupies. In the block diagram of gure 6.17, as in all folding A/D converters, the number of
257
2
Sinewave Generators Differential Reference Ladder (16 taps)
8
Folds per Sinewave
Times Interpolation
= =
128 7 2
Digital Encoding & Error Correction Digital Output (7 Bits)
Vin
I Q
Nonuniform Differential 8X Interpolation Ladder
Analog Encoding and Comparators (5 Bits)
Cycle-Pointing Coarse Quantizer (3 Bits)
Figure 6.17. Folding, interpolating, and analog encoding ne quantizer using quadrature folded waveforms.
N
thresholds, 2 , is determined by
2 = AFI
(6.1)
where A is the number of folding circuits, F is the number of folds in each folded waveform, and
I is the interpolation factor. In the present design, A = 2 since only the I and Q folding circuits
are used, F = 8 which is a practical limit for low voltage-swing converters, and I = 8 which is required so that AFI = 128 = 2 .
7
6.4.1 Encoding
The novel encoding technique used for this converter greatly reduces the complexity of the necessary encoding circuitry (Fig. 6.18). Rather than drive comparators directly, the outputs from the interpolation ladder are encoded in the analog domain before digitization. This encoding most naturally maps to Gray code, wherein each decreasingly signicant bit transitions at twice the rate of its predecessor (Fig. 6.18, right side). In the present encoding scheme, this relationship is produced by multiplying two quadrature signals which transition at the rate of the predecessor bit (recall that the product of 2 quadrature sinusoids is a third sinusoid at twice the frequency). The result is a simple encoding tree composed of multiplier elements: analog multiplier encoders and digital Exclusive-OR gates. In fact, the analog encoders are very simple multiplier circuits identical to Exclusive-OR gates. The latching comparators dene the transition boundary across which encoded analog signals become digital logic levels.
258
I BIT 1
R1
R1 R1
R1 BIT 2
R2
R2 R2
R2
BIT 3
R3
R3 R3
R3
BIT 4
R4
R4 R4 Nonuniform Interpolation Ladder
R4 Analog Multiplier Encoders
BIT 5
Comparators
Digital Encoding
Gray Coded Output Waveforms
Figure 6.18.
Improved encoding scheme signicantly reduces hardware complexity. All circuits are differential but are shown single-ended for simplicity.
6.4.2 Cycle Pointer (Coarse Quantizer)

The coarse quantizer output is in Gray code, for compatibility with the Gray-coded ne quantizer, and also to minimize encoding errors caused by comparator metastability. Analog encoders, simplied versions of folding ampliers [17], [18], [19], [20], [21], [22], [23], produce this Gray code (Fig. 6.19) by comparing the analog input with appropriate reference voltages. Outputs from these analog processing blocks are digitized generating Gray code directly with no other intervening logic.
6.4.3 Layout
The layout of the analog portion of the folding 7-bit quantizer (Fig. 6.20) includes the differential reference ladder, the folding ampliers, interpolation ladder, and analog multipliers from the encoding block. This portion of the chip is approximately 1100m 1100 m .
259
1
V VB VC A
out MSB VD VE VF In
1
Vin
+ Vout -
2
V VB VC A
out MSB-1 VD VE VF In
Input
2 3
V VB VC A VD VE VF In out Vin MSB-2 VB VE
+ _ Vout
3
VA
+ _ Vout VC VD VF
4
V VB VC A
out Vin MSB-3 VD VE VF In
Gray Code Digital Output
Figure 6.19.
Cycle pointer incorporating analog encoding. Actual circuit is differential but is shown single-ended for simplicity.
References
[1] [2]
B. Gilbert, Monolithic analog READ-ONLY memory for character generation, IEEE Journal of Solid State Circuits, vol. SC-6, pp. 4555, Feb. 1971. B. Gilbert, A monolithic microsystem for analog synthesis of trigonometric functions and their inverses, IEEE Journal of Solid State Circuits, vol. SC-17, pp. 11791191, Dec. 1982. R. J. van de Plassche and R. E. J. van der Grift, A high-speed 7 bit A/D converter, IEEE Journal of Solid State Circuits, vol. SC-14, pp. 938943, Dec. 1979. W. Wolz, Videoumsetzer mit mehrfachfaltung, Elektronik, pp. 7376, July 1983. J. V. Woods and R. N. Zobel, Fast synthesized cyclic-parallel analogue-digital convertor, IEE Proceedings, vol. 127, pp. 4551, Apr. 1980. A. Arbel and R. Kurz, Fast ADC, IEEE Transactions on Nuclear Science, vol. NS-22, pp. 446451, Feb. 1975. R. E. J. van de Grift and R. J. van de Plassche, A monolithic 8-bit video A/D converter,
[3] [4] [5] [6] [7]
[8]
[9]
260
[11]
xfqfend Size: 1132 x 1113 microns
[10]
Figure 6.20.
IEEE Journal of Solid State Circuits, vol. SC-19, pp. 374378, June 1984. Layout of ne quantizer analog circuitry including differential reference ladder, folding ampliers, interpolation ladder, and analog multipliers from the encoding block.
R. E. J. van de Grift, I. W. J. M. Rutten, and M. van der Veen, An 8 bit video ADC incorporating folding and interpolation techniques, IEEE Journal of Solid State Circuits, vol. SC-22, pp. 944953, Dec. 1987.
R. J. van de Plassche and P. Baltus, An 8b 100-MHz folding ADC, in International Solid State Circuits Conference, pp. 222223, IEEE, Feb. 1988.
R. J. van de Plassche and P. Baltus, An 8-bit 100-MHz full Nyquist analog-to-digital con-
R. E. J. van de Grift and M. van der Veen, An 8b 50MHz video ADC with folding and interpolation techniques, in International Solid State Circuits Conference, pp. 9495, IEEE, Feb. 1987.
# # # ## # # ### p p # # # ## p## # ####p# # ppp# # #### p# p # ### p# ##p # ## #p # p #pp # # p # #p ### p # # #p # ## p# #p# #p# pp # ### # p p p # p p p # ## # # p p # ## ##p ## #pp p# #p ### # ## # p # # ##pp p #pp p# pp # p ## ### # # # #p p p # # # # p # p p## # ## # # ### # p# p # # # p # ## # p pp ## p #p # ## # p# # # # p pp # ## p# p# # p# ## p# # # # # # # # # p# #p#p # p# p p # # # # #p # # p #p # p p# p## ## p p ## ## # p# # p# # ## # p p # # pp #p # # p # # ## # # p p #p ## ##pp# ## # # ## # #p p p #p ## # p p # ## # # # p## # # #p # p # # ## p # # p p ## p # # # #p pp#p # # # # p # ## # ## pp p# # p # # # p # # p p # # # p # # # #p # ### pp # p p# # p # p p # # ## ## p # # p # # # p p #p p # # # p # p ### ## p# ##p# # #pp ## # # pppp ### p #p p # # pp #p #p ## p#pp ## #pp # #ppp p# # #p p# # # # ## #### # # # # # ####

verter, IEEE Journal of Solid State Circuits, vol. SC-23, pp. 13341344, Dec. 1988. [12] [13] [14] [15]
261
J. van Valburg and R. van de Plassche, An 8b 650MHz folding ADC, in International Solid State Circuits Conference, pp. 3031, IEEE, Feb. 1992. P. Vorenkamp and J. P. M. Verdaasdonk, A 10b 50Ms/s pipelined ADC, in International Solid State Circuits Conference, pp. 3233, IEEE, Feb. 1992. L. M. Devito, High-speed voltage-to-frequency converter. U.S. Patent Number 4,839,653, June 1989. R. Petschacher, B. Zojer, B. Astegher, H. Jessner, and A. Lechner, A 10-b 75-MSPS subranging A/D converter with integrated sample and hold, IEEE Journal of Solid State Circuits, vol. SC-25, pp. 13391346, Dec. 1990. A. G. F. Dingwall, Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter, IEEE Journal of Solid State Circuits, vol. SC-14, pp. 926932, Dec. 1979. J. J. Corcoran, K. L. Knudsen, D. R. Hiller, and P. W. Clark, A 400MHz 6b ADC, in International Solid State Circuits Conference, pp. 294295, IEEE, Feb. 1984. A. P. Brokaw, Parallel analog-to-digital converter. U.S. Patent Number 4,270,118, May 1981. T. W. Henry and M. P. Morgenthaler, Direct flash analog-to-digital converter and method. U.S. Patent Number 4,386,339, May 1983. C. W. Mangelsdorf, Parallel analog-to-digital converter. U.S. Patent Number 4,924,227, May 1990. C. W. Mangelsdorf and A. P. Brokaw, Integrated circuit analog-to-digital converter. U.S. Patent Number 4,596,976, June 1986. P. A. Reiling, Translating circuits. U.S. Patent Number 2,922,151, Jan. 1960. P. A. Reiling, Analog-to-digital converter. U.S. Patent Number 3,573,798, Apr. 1971.
[16] [17] [18] [19] [20] [21] [22] [23]
262
Chapter 7
Gain Stabilization
7.1 Gain Matching Requirements

Gain mismatch among the 10-bit ADC components leads to threshold errors in the A/D converter transfer function [1], [21], [3], [4], [5]. These errors are most easily quantied by their effect on SNR according to equation 1.109. However, component gain errors also give rise to distortion, since the threshold disturbances they cause are not random, but deterministic functions of analog input voltage. As mentioned in section 10.2, a useful area of inquiry lies in determining analytic expressions for ADC distortion in terms of pertinent gain mismatch factors. Three component gain errors are considered: coarse quantizer gain error, DAC gain error, and ne quantizer gain error. All other gain errors can be expressed as equivalent values of these three. Variations in coarse quantizer gain from the ideal value cause equivalent variations in the ADC gain, but do not degrade linearity. DAC gain errors cause the residue waveform to exceed the input range of the ne quantizer for extreme values of input voltage (Fig. 7.1a). Such errors in the residue waveform manifest themselves as SNR degradation. This effect, described in chapter 2 and repeated here for convenience (Fig. 7.2), becomes excessive for DAC gain errors greater than about 1% in magnitude for the 4,7 partitioning used here. Fine quantizer gain errors cause periodic disturbances of the A/D converter thresholds (Fig. 7.1b) which degrade linearity. Therefore, ne quantizer gain error must also be limited to about 1% before SNR diminishes signicantly (Fig.
264
Chapter 7 Gain Stabilization
-V Residue = V DAC in Nominal Input Range to 2nd Quantizer
DAC gain too low
DAC gain too high Correct DAC Gain
Vfs/4
Vfs/2
3Vfs/4
Vfs
0 V1 Opamp ensures V1=V2 Segment 10
Vin V2 Segment 15
(b)
Reconstruced A/D Output Ideal Waveform
Vfs
3Vfs/4
Vfs/2
Vfs/4
A/D Output with Incorrect 2nd Quantizer Full-Scale Range 0

Vfs/4 Vfs/2 3Vfs/4 Vfs
Vin
(a) Figure 7.1. Effects of component gain errors on A/D transfer function. (a) Effect of ne quantizer gain error. (b) Effect of DAC gain error.
7.3).
7.2 Gain Control
265
62 60 58 56 SNR (dB) 54 52 50 48 46 44 10
n1=5 n2=6
n1=4 n2=7
n1=4 n2=7
ADC Gain Error (%) 5
n1=5 n2=6
-5
-10 -10
-8
-6
-4
-2 0 2 DAC Gain Error (%)
10
Figure 7.2. 10 bit A/D converter SNR (upper) and gain error (lower) versus
DAC gain error for both 4-7 and 5-6 partitioning.
7.2 Gain Control

To avoid the errors described above, the full-scale range of the reconstruction DAC must match the full-scale range of the input signal; and the residue, after amplication, must align with the full-scale range of the ne quantizer. These gains are matched to one another using on-chip replica circuits (Fig. 7.4) [20], [7], [23], [9]. An externally supplied reference voltage equal to the
266
62 60 58 56 SNR (dB) 54 52 50 48 46 44 0.05 0.04 0.03 ADC Gain Error (%) 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 -0.05 -10 -8 -6 -4 -2 0 2 4 Fine Quantizer Gain Error (%) 6 8 10
n1=5 n2=6
n1=4 n2=7
n1=4 n2=7
n1=5 n2=6
Figure 7.3. 10 bit A/D converter SNR (upper) and gain error (lower) versus
ne quantizer gain error for both 4-7 and 5-6 partitioning. full-scale range of the input drives a scaled replica of the coarse quantizer differential reference ladder, and an op-amp forces the DC voltage across both the replica and the main ladders to match this reference. Similarly, the full-scale reference voltage and an attenuated version drive two scaled replicas of the residue amplier biased by two scaled DAC replicas set the specic thermometer codes 111 and 011. (The scaling factor used here is 1:5 so the replica DAC settings correspond to all 15 segments on and 10-of-15 segments on respectively.) A second op-amp controls the segment currents in the replica and main DAC to align two peaks along the sawtooth residue characteristic
7.2 Gain Control
267
+Vfs 4 -Vfs Scaled S/H 2 Replica
First Quantizer Ladder
Hardwired DAC Switch "1 1 1"
Hardwired DAC Switch "0 1 1"
DAC Segment Currents
Second Quantizer Ladder
Coarse Quantizer Gain Loop
Reconstruction DAC Gain Loop
Fine Quantizer Gain Loop
Figure 7.4. Gain-matching replica circuits and feedback loops which adjust
component gains. (voltages V1 and V2 in gure 7.1a). Thus, the DAC full-scale range aligns with the rst quantizer full-scale range. The output of one replica residue amplier also supplies the reference level to a replica of the second quantizer ladder. The second quantizer gain is controlled by a third op-amp loop identical to that controlling the rst quantizer gain. All three op-amps, which operate at DC in the replica circuits, are off-chip.
References
[1] [2]
S. H. Lewis and P. R. Gray, A pipelined 5MHz 9b ADC, in International Solid State Circuits Conference, pp. 210211, IEEE, Feb. 1987. S. H. Lewis and P. R. Gray, A pipelined 5-Msample/s 9-bit analog-to-digital converter,
268

IEEE Journal of Solid State Circuits, vol. SC-22, pp. 954961, Dec. 1987.
[3] [4] [5]
S. Sutarja and P. R. Gray, A 250ks/s 13b pipelined A/D converter, in International Solid State Circuits Conference, pp. 228229, IEEE, Feb. 1988. S. Sutarja and P. R. Gray, A pipelined 13-bit, 250-ks/s, 5-V analog-to-digital converter, IEEE Journal of Solid State Circuits, vol. SC-23, pp. 13161323, Dec. 1988. M. Ishikawa and T. Tsukahara, An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wide-band S/H, IEEE Journal of Solid State Circuits, vol. SC-24, pp. 1485 1491, Dec. 1989. T. Shimizu, M. Hotta, K. Maio, and S. Ueda, A 10-bit 20-MHz two-step parallel A/D converter with internal S/H, IEEE Journal of Solid State Circuits, vol. SC-24, pp. 1320, Feb. 1989. T. Shimizu, M. Hotta, K. Maio, and S. Ueda, A 10b 20MHz two-step parallel ADC with internal S/H, in International Solid State Circuits Conference, pp. 224225, IEEE, Feb. 1988. R. Petschacher, B. Zojer, B. Astegher, H. Jessner, and A. Lechner, A 10-b 75-MSPS subranging A/D converter with integrated sample and hold, IEEE Journal of Solid State Circuits, vol. SC-25, pp. 13391346, Dec. 1990. P. Vorenkamp and J. P. M. Verdaasdonk, A 10b 50Ms/s pipelined ADC, in International Solid State Circuits Conference, pp. 3233, IEEE, Feb. 1992.
[6]
[7]
[8]
[9]
Chapter 8
Performance
Three versions of the 10-bit A/D converter differing exclusively in the layout of the reconstruction DAC were fabricated in the Tektronix SHPi process. Each chip occupies the same area and uses identical pad locations to facilitate testing. The performance of these chips is discussed next. A separate 8-bit A/D converter based upon the 7-bit ne quantizer of chapter 6 was also fabricated. Performance of the 8-bit device is discussed in chapter 9.
8.1 Circuit Layout

Because low complexity quantizers comprise the A/D converter, each chip incorporates less than 2500 transistors and even fewer resistors so that the silicon area occupied is approximately 4mm 4mm , or equivalently 160mil 160mil (Fig 8.1). The 4-bit coarse quantizer, DAC
current switches, and encoding logic (including the Coarse Ladder, Coarse Latches & DAC Switches, Delay Stage, Correction MUX, and Coarse ROM as labelled in gure 8.1) occupy about the same area as the 7-bit ne quantizer and its encoding logic (Folding Amps, Cycle Pointer, Fine Encoding, and Error Correction in gure 8.1), thus conrming the original premise by which conversion was partitioned between the two stages (see section 2.3.2 and gure 2.17). The input and interstage T/H circuits are located at the top of the chip along with the residue amplier. These are the most sensitive analog components in the A/D converter and are therefore intentionally located as far away as possible from digital components and from the output buffers. The coarse quantizer
270
Chapter 8 Performance
T/H 1
Res Amp T/H 2
4064m
Coarse Ladder DAC Coarse Latches & DAC Switches Folding Amps
Delay Stage
Cycle Pointer
Fine Encoding
Correction MUX Coarse ROM
Error Correction
Output Buffers 4288mm
10-bit A/D converter with constituent components highlighted. Die size is approximately 4 mm X 4 mm (160 mil X 160 mil). Analog input is at top, left of chip. Digital outputs are at bottom. is on the left side of the chip with the ne quantizer on the right. The reconstruction DAC occupies the center of the die in all 3 implementations, and the output buffers ll the bottom of the layout. The 10-bit output word from the converter is Gray coded and includes one extra bit to indicate an overow or underow condition. Each output latch switches a differential pair which drives complementary open-emitter transistors. These output devices can be terminated off-chip by differential ECL receivers. Thus, the on-chip output drivers are compatible with standard ECL logic levels as are the sample-clock inputs. The analog input circuitry provides 50 termination resistors from both complementary input nodes to ground and accepts ground-centered signals.
Figure 8.1.
8.1 Circuit Layout
271
The version of the A/D converter utilizing the nominal DAC layout (Fig. 8.2) includes
Figure 8.2. Die photograph of 10-bit A/D converter with nominal DAC layout.
Unused area surrounding DAC degeneration resistors is reserved for use in other ADC versions.
signicant unused silicon surrounding the DAC degeneration resistors (as shown in gure 8.1, the DAC occupies the center portion of the circuit). This area is reserved to accommodate the larger DAC layouts from other versions of the ADC chip. In the version of the converter using a commoncentroid reconstruction DAC (Fig. 8.3) this area is nearly lled, and in the version incorporating a trimmable DAC (Fig. 8.4) the area is completely utilized. In fact, the excessively large size of trimmable resistors is a signicant impediment to their widespread use. Since the die-size and pad
272
Figure 8.3.
Die photograph of 10-bit A/D converter with common centroid reconstruction DAC layout.
locations are identical for all versions of the converter chip, packaging and testing techniques were also consistent among the different versions. Each chip has 100 pads, but many are used solely to monitor internal bias voltages during testing with custom wafer probes. Therefore, the chips were bonded in standard ceramic 68-pin leaded chip-carrier (LCC) packages. The three versions of the 10-bit converter shared a common reticle along with the 8-bit converter so that only one mask set was required to fabricate all four circuits. No JFETs or PNP bipolar devices are included on any of the four chips ensuring that the circuit design and layout are applicable to generally available silicon bipolar processes.
8.2 Test Methodology
273
Figure 8.4. Die photograph of 10-bit A/D converter with trimmable reconstruction DAC layout.

The A/D converter chips were tested by supplying sinusoidal input signals and ECL compatible clocks to the device under test (DUT) and capturing the resultant digital output data in high-speed memory for later evaluation by computer. The test set-up used for this purpose (Fig. 8.5) supplies low-noise, sinusoidal analog input signals which are appropriately ltered to reduce harmonics and which are phase-locked to low-noise, fast rise-time sample clocks. Passive phasesplitters generate differential analog input signals in response to the single-ended versions emanating from the frequency synthesizers. Digital data is captured in high-speed memory and later downloaded to a laboratory computer for analysis. Additionally, a high-speed, 10-bit DAC
274
Power Supplies HP 8662 Freq. Synth.

10 MHz Reference
Analog Input
HP 8662 Freq. Synth.
BPF
DUT
10-Bit DAC Oscilloscope 10
Clock
HP 8662 Freq. Synth.
Colby PG5000 Pulse Gen.
Workstation
GPIB Control
Spectrum Analyzer Tek 9503 Fast Data Cache
Figure 8.5.
A/D converter test setup. All synthesizers are phase-locked to one master synthesizer. Pulse generator supplies ECL clock signal to DUT upon trigger from low phase-noise synthesized source. Four pulse generators are used to supply clocks to DUT, but only one is shown for simplicity. Off-chip reconstruction DAC is helpful for real-time debugging of system. Digitized data is captured in fast, deep memory and analyzed on workstation off-line.
reconstructs the digitized signal for analysis with an oscilloscope and spectrum analyzer. The test set-up, a photograph of which appears in gure 8.6, also includes computer-controlled power supplies and voltmeters to monitor bias voltages and power dissipation. Both probed wafers and packaged parts were tested using this set-up. To facilitate testing of many devices, a xture with a low insertion-force socket was used when evaluating parts housed in the 68-pin ceramic packages described above. Several well-known analysis techniques enable characterization of A/D converter dynamic performance from collections of digital output data taken from the DUT in response to known input signals. In particular, performing the Fast Fourier Transform (FFT) on digitized waveforms generates the ADCs digital output spectrum from which SNR, SFDR, and THD can be ascertained [1], [2], [3], [4]. Additionally, calculating histograms from large sets of output data generated in response to input signals with known probability density functions enables determination of the ADCs dynamic integral and differential linearity error (INL and DNL) [1], [2]. Alternatively, INL
275
Figure 8.6.
A/D converter test setup. Synthesizers, pulse generators, spectrum analyzer, and lter bank are housed in rack on left. High-speed memory and workstation are on right. Power supplies, oscilloscopes, and test xtures are on bench in rear.
and DNL can be calculated from measurements of the actual ADC threshold levels. Such measurements are best performed with the aid of a hardware tracking loop which encloses the A/D converter within a feedback loop to perform an integrated (and hence low-noise) measurement of the particular threshold level in question [1], [5]. These analysis techniques allow calculation of ADC dynamic performance without the intervention of a potentially error-prone reconstruction DAC and were utilized to characterize the ADCs described here. The reconstruction DAC in the test set-up above generates qualitative information for debugging and trouble-shooting, and does not affect the accuracy of the performance data tabulated below.
276
8.3 Test Results

Approximately 70 die sites were probed and 15 packaged parts tested for each of the three ADC versions. The probed die sites were all located on one wafer, and the packaged parts were taken from a second wafer. No signicant difference in performance was noted between the three versions so distinctions among the three circuits will no longer be made. About 70% of the circuits tested exhibit the nominal performance described here. The ADC dissipates 800 mW from +5 V and 5 V power supplies, excluding off-chip ECL supplies which bias the output devices. The +5 V power supply is required only for the two T/H circuits. Although the converters performed reasonably well at or beyond 100 Msps, reliable data could only be obtained at 75 Msps, and all of the data reported below pertains to that sample-rate. Spectral analysis of digitized sinewaves using 8192 point FFTs and Hamming window ltering indicates dynamic performance consistent with 10-bit operation (Figs. 8.9 through 8.7). For
0 -10 Relative Amplitude (dBc) -20 -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 Frequency (MHz) 30 35 40 n = 5.87 MHz fs = 75 Msps FFT block size = 8192 S/(N+D) = 59 dB SFDR = -77 dBc
Figure 8.7. Digital output spectrum from A/D converter when sampling a 5.87 MHz sinusoidal input at 75 Msps.
8.3 Test Results
277
0 -10 Relative Amplitude (dBc) -20 -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 Frequency (MHz) 30 35 40 2n 3n n = 5.87 MHz fs = 75 Msps FFT block size = 8192 S/(N+D) = 59 dB SFDR = -76 dBc
a 5.87 MHz differential, full-scale input sinusoid converted at 75 Msps, the ratio of signal power to all other power in the output spectrum, the so-called signal-to-noise-plus-distortion or S/(N+D), is 59 dB. Also, the spurious-free dynamic range (SFDR), specied by the highest spurious signal level relative to the fundamental, is nearly 80dBc . The spectra from gures 8.9 through 8.7 correspond to three different ADCs operating at the frequencies specied above. All three devices give similar S/(N+D), approximately 59 dB, which closely approaches the theoretical limit for a 10-bit ADC, 62 dB. The SFDR is about 77dBc in all three cases. This gure falls short of the ideal for a 10bit converter, 9N = 90dB , but compares very favorably to the distortion performance reported for other 10-bit converters extant. When the analog input frequency is increased toward the target Nyquist rate of 50 MHz, distortion increases as expected (Fig. 8.10). For a 49.6 MHz full-scale input and a 75 Msps conversion rate, the S/(N+D) degrades only slightly to 56 dB while the SFDR, dominated by the 3rd harmonic, degrades to 62dBc . The rst several harmonics, although rearranged in position
278
0 -10 Relative Amplitude (dBc) -20 -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 Frequency (MHz) 30 35 40 2n 3n n = 5.87 MHz fs = 75 Msps FFT block size = 8192 S/(N+D) = 59 dB SFDR = -75 dBc
due to the effects of aliasing, are clearly visible above the noise oor in the spectrum plotted in gure 8.10. The 3rd harmonic is dominant as mentioned, followed by the 2nd harmonic located at 69dBc . Other low-order harmonics are discernible but are near 80dBc . The degraded S/(N+D), 56 dB, is still greater than 9 effective bits and at 50 MHz surpasses the performance of any known monolithic 10-bit ADC regardless of power dissipation. Likewise, the decreased SFDR at 50 MHz nonetheless represents a signicant improvement in achievable performance over any 10-bit A/D converter reported to date. Integral linearity error (ILE) and differential linearity error (DLE), also known as integral non-linearity (INL) and differential non-linearity (DNL) respectively can be calculated from histograms of ADC output data in response to signals with know probability density functions [1], [2]. By using this histogram method on data collected from the ADC when digitizing a 5.87 MHz sinusoid at 75 Msps the DNL and INL plotted in gures 8.11 and 8.12 respectively result. Peak DNL is less than 1/2 LSB and is for most thresholds below 0.2 LSB. The root-mean-square (rms)
8.3 Test Results
279
0 -10 Relative Amplitude (dBc) -20 -30 -40 -50 -60 -70 -80 -90 -100 0 5 10 15 20 25 Frequency (MHz) 30 35 40 6f 3f 9f n = 49.6 MHz fs = 75 Msps FFT block size = 8192 S/(N+D) = 56 dB SFDR = -62 dBc
2f 8f 5f 4f 7f
DNL is approximately 0.1 LSB. Both of these gures are consistent with 10-bit linearity and indicate that the nonuniform interpolation scheme used to eliminate threshold errors in the ne quantizer works effectively as does the interstage gain-matching approach. Peak INL is below 3/4 LSB and for most thresholds is less than 1/2 LSB. Again, this uniformity of threshold placement conrms the validity of the design techniques invoked to attain 10-bit operation with very low complexity and power dissipation. When the input frequency is increased from 5.87 MHz to 49.6 MHz, the threshold uniformity degrades slightly. Plots of the DNL and INL calculated from the histogram technique at this frequency are shown in gures 8.13 and 8.14 respectively. Peak DNL is still well below 1/2 LSB, and rms DNL is virtually unchanged from the 5.87 MHz case. INL no longer remains below 3/4 LSB, extending to 0.8 LSB for a very few codes. This phenomenon is probably caused by T/H distortion since the location of the ADC thresholds is independent of the analog input frequency.
280
.5 .4 .3 Threshold Error (LSB's) .2 .1 0 -.1 -.2 -.3 -.4 -.5 0 .1 .2 .3 .4 .5 .6 .7 .8 Threshold Number (X1000) .9 1 1.1
Figure 8.11. Differential linearity as measured by a histogram test with fin = 6MHz and fs = 75Msps.
A stringent test on A/D converter operation, called a beat-frequency test, entails driving the T/H with an analog input frequency close to 1/2 the sample rate. Under these conditions, the input signal traverses across the maximum number of thresholds between successive samples. Therefore, signal slew-rates within the circuit are maximized resulting in greater distortion than in other modes of operation. By applying the digital output from the A/D converter to a reconstruction DAC, the resultant signal can be displayed on an oscilloscope exposing any signs of faulty operation such as missing codes. A beat frequency test performed on this ADC operating at 75 Msps and with the analog input set to 37.501 MHz results in the oscilloscope waveform depicted in gure 8.15. To obtain this image, the output data stream from the ADC was decimated by 2 before being applied to the reconstruction DAC. This operation is necessary because otherwise an envelope signal will be displayed. Such an envelope results under near-Nyquist conditions because the A/D converter will sample a sinusoid peak of one polarity, followed on the successive sample by a sinusoid peak of the opposite polarity. For this reason, a test like that described here is sometimes called an envelope test. When decimating by 2, every other sample is removed from the data stream so that
8.3 Test Results
281
1 .8 .6 Threshold Error (LSB's) .4 .2 0 -.2 -.4 -.6 -.8 -1 0 .1 .2 .3 .4 .5 .6 .7 .8 Threshold Number (X1000) .9 1 1.1
Figure 8.12. Integral linearity as measured by a histogram test with fin = 5.87MHz and fs = 75Msps.
successive samples produce adjacent voltages. Note that the frequency difference from Nyquist, that is f in f S 2 , gives the frequency of the resultant waveform. The waveform shown in gure 8.15 shows no signs of distortion or missing codes even under the stressful conditions selected. The delity of the beat frequency waveform implies that the T/H circuit can adequately track highfrequency inputs without distortion due to slewing effects, and that the quantizer can adequately track a voltage transition equal to its full-scale-range in one sample period.
282
.5 .4 .3 Threshold Error (LSB's) .2 .1 0 -.1 -.2 -.3 -.4 -.5 0 .1 .2 .3 .4 .5 .6 .7 .8 Threshold Number (X1000) .9 1 1.1
Figure 8.13. Differential linearity as measured by a histogram test with fin = 49.6 MHz and fs = 75 Msps.
8.3 Test Results
283
1 .8 .6 Threshold Error (LSB's) .4 .2 0 -.2 -.4 -.6 -.8 -1 0 .1 .2 .3 .4 .5 .6 .7 .8 Threshold Number (X1000) .9 1 1.1
Figure 8.14. Integral linearity as measured by a histogram test with fin = 5.87 MHz and fs = 75 Msps.
284
Figure 8.15.
Beat frequency test. fS = 75 Msps, fin = 37.501 MHz. ADC output is decimated by 2 then applied to reconstruction DAC and displayed on oscilloscope.
References
[1] [2] [3] [4] [5]
Hewlett Packard, Dynamic Performance Testing of AtoD Converters. Product Note 5180A2. J. Doernberg, H. Lee, and D. A. Hodges, Full-speed testing of A/D converters, IEEE Journal of Solid State Circuits, vol. SC-19, pp. 820827, Dec. 1984. G. Pretzl, Dynamic testing of high-speed A/D converters, IEEE Journal of Solid State Circuits, vol. SC-13, pp. 368371, June 1978. T. E. Linnenbrink, Effective bits: Is that all there is?, IEEE Transactions on Instrumentation and Measurement, vol. IM-33, pp. 184187, Mar. 1984. J. J. Corcoran, T. Hornak, and P. B. Skov, A high-resolution error plotter for analog-todigital converters, IEEE Transactions on Instrumentation and Measurement, vol. IM-24, pp. 370374, Dec. 1975.
Chapter 9
8Bit A/D Converter
The ne quantizer from the 10-bit ADC incorporates folding, interpolation, and analog encoding to achieve efcient, high-speed operation. This building-block, suitably modied, forms the quantizer of the 8-bit A/D converter described here. The input T/H from the 10-bit ADC precedes this quantizer to ensure accurate digitization of dynamic signals. A brief description detailing the architecture of this composite A/D appears next, followed by discussion of the converters measured performance.
9.1 Architecture
Since the 8-bit ADC (Fig. 9.1) derives from its 7-bit predecessor (Fig. 6.17), the two architectures share most features, differing in only two aspects. First, the 8-bit ADC features a T/H to capture dynamic signals, and second, its interpolation factor is doubled (as is the complexity of succeeding stages), thereby increasing the converters resolution by one bit. The resolution, N , of the converter derives from
2 = AFI
(9.1)
where A is the number of folding ampliers used, F is the number of folds per sinewave, and I is the interpolation factor. For the 8-bit quantizer implemented, A = 2 , F = 8 , and I = 16 ;
286
Chapter 9 8Bit A/D Converter
2
Sinewave Generators Differential Reference Ladder (16 taps)
8
Folds per Sinewave
16
Times Interpolation
= 256 8 = 2
Digital Encoding & Error Correction Digital Output (8 Bits)
Vin T/H
I Q
Nonuniform Differential 16X Interpolation Ladder
Analog Encoding and Comparators (6 Bits)
Cycle-Pointing Coarse Quantizer (3 Bits)
Figure 9.1. 8-bit A/D converter architecture. T/H derives from input T/H in 10-bit ADC. Quantizer is based upon 7-bit ne quantizer, also from 10-bit converter.
therefore,
A F I = 2 8 16 = 256 = 2
(9.2)
as expected. The increased interpolation factor, I , compared to the 7-bit case roughly doubles the number of comparators necessary along with the complexity of the succeeding logic. Whereas the differential reference ladder and folding ampliers are identical among the two quantizers (owing to the fact that A and F are equal), the die photograph (Fig. 9.2) indicates that the analog and digital encoding banks are twice the size of those in the 7-bit quantizer (see gures 6.20 for comparison). Even with this increase in complexity, the A/D chip still requires only 21 comparators: 17 to digitize the interpolated sinusoids and 4 to form the cycle pointer. These components are visible when the overlaid text is removed from the die photograph (Fig. 9.3). The entire converter utilizes only approximately 1000 transistors and the fabricated die occupies about 3mm 3mm ( 120mils 120mils ).
9.2 Performance
287
T/H
Differential Ladder & Folding Ampliers Interpolation Ring 3056mm
Coarse Quantizer
Analog Encoding Digital Encoding
Error Correction Output Buffers 3152mm

8-bit A/D converter with overlays to indicate location of constituent components.
Figure 9.2.
9.2 Performance
The 8-bit converter chips were tested using the same set-up and algorithms as the 10-bit A/D. Different wafer probe cards and test xtures were necessary to accommodate the smaller die size and number of pads required for the 8-bit chip. Again, approximately 70 die sites were probed and 15 packaged parts tested. The ADC dissipates 550 mW from +5 V and 5 V supplies, but only the input T/H circuit requires the positive supply voltage. As in the 10-bit converter, digital inputs and outputs are compatible with ECL logic levels, while the analog input provides 50 terminations for a ground-centered differential signal.
288
Figure 9.3. Die photograph of 8-bit A/D converter.

FFT analysis of digital output data provides the corresponding spectrum generated by the A/D converter. This output spectrum can be evaluated to ascertain SNR and harmonic distortion. When performed over an array of input and sample frequencies, such analysis completely characterizes ADC performance. FFT analysis on digitized data from the 8-bit converter generated the plots of SNR and harmonic distortion shown in gures 9.4 through 9.11 below. This data covers sample rates from 25 Msps to 200 Msps along with input frequencies from 1.5 MHz to the Nyquist rate. Each plot includes measurements for nominal power supply voltages and for power supply variations of +7% and 7%. The data contained in these curves should be compared to ideal performance for an 8-bit quantizer which includes:
9.2 Performance
289
SNR = 6.02N + 1.76dB = 6.02 8 + 1.76dB = 50 dB

and
(9.3)
SFDR = 9NdBc = 9 8dBc = 72dBc
(9.4)
At 25 Msps (Fig. 9.4) SNR is near 48 dB for the nominal and high power supply voltages at input
50
-35
45 FS=25Msps 40 SNR (dB) Nominal Power Supplies +7% Power Supplies -7% Power Supplies
-40 Harmonic Distortion (dBc)
-45
35
-50
30
-55
25
-60
20
10 Input Frequency (MHz)
-65 100
Figure 9.4. Measured SNR and harmonic distortion versus input frequency
at 25 Msps.
frequencies below 20 MHz. Above this frequency, SNR degrades to 45 dB at 40 MHz. For the same power supply values, harmonic distortion as specied by SFDR, varies between 58 dBc and
290
62 dBc. This measured SNR and SFDR compares favorably with the ideal values specied in equations 9.3 and 9.4 respectively. At power supply values 7% below nominal, both the measured SNR and the measured SFDR are degraded signicantly. This phenomenon is probably caused by droop effects which are more pronounced at the 25 MHz sample rate than at the higher frequencies for which the T/H was optimized. Improved performance at 50 Msps (Fig. 9.5) supports this
50
-35
45 FS=50Msps
40 SNR (dB) Nominal Power Supplies +7% Power Supplies -7% Power Supplies
-45
35
-50
30
-55
25
-60
20
-65 100
at 50 Msps.
assertion. At this higher sample rate, performance is virtually independent of power supply showing a gradual roll-off in SNR above 20 MHz input frequency to 40 dB at 80 MHz. Over this input frequency range, SFDR increases from 60 dBc to 50dBc. These performance gures for low input frequencies are excellent, indicating that the quantizer architecture operates with adequate linearity. The degradation in SNR and SFDR at modest input frequencies implies, however, that the T/H circuit cannot deliver adequate dynamic linearity to sustain the delity achievable by the quantizer. Increasing the sample rate to 100 Msps reveals sensitivity to power supply voltage (Fig. 9.6). At this sample rate, SNR and SFDR are almost identical to those recorded at 50 Msps with the
9.2 Performance
291
50
-35
-45
35
-50
30
-55
25
-60
20
-65 100
at 100 Msps. exception of data corresponding to 7% supply voltages which degrades very rapidly at 20 MHz input frequency. Because this performance change is dependent upon input frequency, its cause probably lies within the T/H circuit. SNR and SFDR continually degrade as sample rate is increased. Figures 9.7 through 9.10 show SNR and SFDR for the sample rates 125 Msps, 150 Msps, 175 Msps, and 200 Msps respectively. This data indicates that dynamic linearity continues to degrade with increasing sample rate at input frequencies above 10 MHz for all power supply values. Linearity at low input frequencies remains unaffected until 175 Msps at which point SNR drops by about 1 dB compared to lower sample-rate data. SNR is 46 dB (45 dB for 7% power supply values) at 200 Msps, but dynamic linearity drops off severely. The effect of substrate temperature on linearity can be seen in gures 9.11 and 9.12 which plot SNR and SFDR versus input frequency for 200 Msps operation at 40 C and 125 C respectively. SNR corresponding to 200 Msps and 40 C at low input frequency is about 45 dB, but drops rapidly with increasing frequency. SNR taken at 200 Msps and 125 C is 38 dB at low input frequency and also declines rapidly with input frequency. Clearly these extremes of temperature and sample rate stress the converter beyond its limits for delivering linearity near that
292
50
-35
-45
35
-50
30
-55
25
-60
20
-65 100
at 125 Msps. attainable with an ideal quantizer. Operation at low input frequencies and at sample rates below 175 Msps does, however, deliver adequate performance for most applications. A summary of dynamic performance for sample rates from 100 Msps to 200 Msps is depicted in gure 9.13 which plots SNR versus analog input frequency. All plots in this gure correspond to room temperature operation with nominal power supply values. The data follows the trend alluded to above: excellent SNR at low input frequencies rolling off quite steeply when input frequency increases above about 10 MHz. This behavior is largely independent of sample rate with 200 Msps operation delivering performance only slightly worse than that at 100 Msps. These symptoms are consistent with the hypothesis that the input T/H circuitry limits high-speed performance. Performance at low input frequencies was further quantied by measuring the threshold voltages of the converter using a comparator feedback loop like that described in section 8.2. This accurate, DC measurement led to the plots of peak and rms integral linearity error (or INL) included
9.2 Performance
293
50
-35
-45
35
-50
30
-55
25
-60
20
-65 100
at 150 Msps. in gure 9.14 which correspond to varying conditions of temperature and power supply voltage. From room temperature to 40 C rms threshold errors remain below 25% of an LSB independent of power supply voltages (within 7 % of nominal) and peak threshold errors are below about 60% LSB. Wen temperature increases to 125 C, rms INL increases to about 38% LSB, and peak INL rises to 95% LSB. The DC values of INL for room temperature and below are adequate for many applications and demonstrate the feasibility of achieving 8-bit A/D converter operation using the folding architecture investigated here. Excessive threshold errors at high temperature represent a deviation from simulated behavior worthy of further investigation.
294
50
-35
-45
35
-50
30
-55
25
-60
20
-65 100
at 175 Msps.
9.2 Performance
295
50
-35
-45
35
-50
30
-55
25
-60
20
-65 100
at 200 Msps.
296
50
-35
45
40 FS=200Msps SNR (dB) T=-40C 35
-45
-50
30 Nominal Power Supplies +7% Power Supplies -2% Power Supplies
-55
25
-60
20
-65 100
Figure 9.11. Measured SNR and harmonic distortion versus input frequency at 200 Msps with T = -40 C.
9.2 Performance
297
45 Nominal Power Supplies +7% Power Supplies -7% Power Supplies 40
-35
-40
Harmonic Distortion (dBc)
SNR (dB)
35
-45
30 FS=200Msps T = 125C 25
-50
-55 100
at 25 Msps.
298
50
45
40 FS=100Msps FS=125Msps FS=150Msps FS=175Msps FS=200Msps SNR (dB)
35
30
25
20
100
Figure 9.13. Measured SNR versus input frequency at several sample rates.
9.2 Performance
299
100
80 Linearity Error (% of LSB)
T = 125 C T = 25 C T = -40 C
Peak Error
60
40
RMS Error
20
0 -10
-8
-6
-4
-2 0 2 4 Power Supply Variation (%)
10
Figure 9.14. Measured integral linearity error versus power supply variation
at several temperatures with fS = 100 Msps. Upper curves plot peak INL. Lower curves plot RMS INL.
300
Chapter 10
Conclusions and Suggested Further Research
10.1Conclusions
A 10-bit, untrimmed, silicon bipolar analog-to-digital converter was developed which is capable of operation at over 75 Msps. When digitizing a 6 MHz sinusoid at this sample rate, the resultant SNR is 59 dB and the SFDR is 77 dBc. For a 50 MHz input the SNR drops to 56 dB and the SFDR decreases to 63 dBc. The measured peak INL is less than 3/4 LSB, and the peak DNL is less than 1/2 LSB. The chip dissipates 800 mW from +5 V and 5 V supplies and incorporates 2500 transistors on a die which measures 4mm 4mm ( 160mil 160mil ). The ADC utilizes a pipelined feedforward topology with a 4-bit ash coarse quantizer and a 7-bit folding ne quantizer allowing 1 bit of redundancy for digital error correction. The coarse quantizer output is converted back to the analog domain using a 4-bit fully-segmented DAC and then subtracted from the held input signal. Dynamic signals are captured by an input T/H, and pipelined operation is facilitated by an inter-stage T/H. Both of these circuits employ diode-bridge switches. The ne quantizer utilizes an innovative folding architecture, shared by a companion 8bit A/D converter chip, to achieve high-speed, low-power operation. All circuits, including the ECL compatible clock inputs and digital outputs, are differential in the ADC chip which utilizes only
302
Chapter 10 Conclusions and Suggested Further Research
NPN transistors and resistors. An 8-bit, untrimmed A/D converter was developed using the same architecture as the 7-bit ne quantizer from the 10-bit converter. The 8-bit ADC operates at 175 Msps delivering 47 dB SNR and 58 dBc SFDR for input sinusoids up to 10 MHz. The measured peak INL is less than 60% LSB at or below room temperature rising to 90% LSB at 125 C. The chip dissipates 550mW from +5 V and 5 V supplies and employs 1200 transistors on a die which measures
3mm 3mm ( 120mil 120mil ).

Both the 7-bit and the 8-bit folding quantizers incorporate two analog folding ampliers whose input-output characteristics are quadrature sinusoids. ADC thresholds are generated using non-uniform interpolation between the zero-crossings of these quadrature waveforms. The resultant array of phase-shifted sinusoids is digitized and encoded using an efcient logic tree consisting of analog multipliers followed by exclusive-OR gates. Because the sinusoidal waveforms are periodic, this encoding generates an ambiguous estimate of the input signal amplitude. To resolve this uncertainty, a ash quantizer called the cycle pointer identies within which period of the sinusoidal waveforms the input signal lies. A simple digital error correction algorithm then ensures proper alignment of the coarse quantizer and ne quantizer thresholds. Several architectural and circuit innovations enabled development of the A/D converters described in this manuscript. The techniques utilized which were fundamental to the achieved performance are tabulated below. Architectural innovations which enhanced performance over more traditional approaches include: a pipelined feedforward A/D converter employing an efcient high-resolution ne quantizer with a low-resolution coarse quantizer to minimize overall complexity. a pipelining arrangement which reduces the linearity required of the inter-stage T/H to a level commensurate with the resolution of the ne quantizer, thereby reducing the complexity and power dissipation of the T/H. This arrangement is only possible when the coarse quantizer exhibits very low resolution as in the partitioning mentioned above. a scheme which assures proper gain settings for the coarse quantizer, reconstruction DAC, and ne quantizer. This technique utilizes scaled replicas of the pertinent
10.1 Conclusions
303
ADC components to recreate conditions within the actual circuits. The replicas are enclosed within feedback loops which control replica bias (and hence gain) to ensure that the replica gains are properly set. The bias of the actual ADC components equals that of the corresponding replica components; therefore proper gain adjustment of the actual ADC components obtains.
New circuits within the input T/H and the inter-stage T/H which enhanced performance include: a compensation technique which eliminates static distortion induced by nite resistance loading diode-bridges. This method was generalized to mitigate the dynamic distortion caused by the load presented by the hold capacitor itself. a very low power, highly linear, unity-gain postamplier with no signal-dependent thermal effects and utilizing only NPN transistors and resistors.
The coarse quantizer utilizes two unconventional techniques: a 4-bit ash quantizer incorporating a differential reference ladder to eliminate threshold errors induced by comparator bias current. The emitter followers comprising the differential ladder also provide buffering to minimize the capacitive load presented by the quantizer. an interpolation method which halves the required number of comparator preampliers. This implementation reduces power dissipation and also reduces settling time in the resistive reference ladder by halving the capacitive load.
Design approaches central to the performance of the reconstruction DAC and residue amplier include: a fully-segmented D/A converter topology which provides the simplest possible interface to the ash coarse quantizer with the lowest sensitivity of DAC linearity to current source mismatches. The individual segments are connected in a specic order which minimizes the effects of spatial correlations among current source errors on the INL of the DAC transfer function. a current-mode subtraction technique which reduces signal-dependent modulation
304

of bias levels in active devices to an amount proportional to the amplitude of the residue signal rather than the input signal. This arrangement reduces by a factor of 16 compared to a more traditional approach the signal-induced bias modulation in active devices, thus affording a commensurate improvement in linearity.
Many innovations contributed to the efciency and performance of the unorthodox ne quantizer including: a pair of folding circuits constructed with a number of simply inter-connected differential pairs which exhibit quadrature sinusoidal input-output characteristics when driven by a differential reference ladder (identical in form to that used in the coarse quantizer). As in the coarse quantizer, this symmetric arrangement eliminates errors caused by bias currents owing into the folding circuits. a non-uniform interpolation method based on trigonometric identities which generates from the two quadrature signals at the folding circuits outputs an array of sinusoids uniformly-spaced in phase. The zero-crossings of these sinusoids correspond to the threshold locations of the quantizer and are uniformly-spaced along the quantizer input voltage range as desired. The interpolation is achieved with a simple resistive ladder whose symmetry minimizes signal current ow, thereby minimizing distortion in the buffers driving the ladder. an analog encoding technique based on simple multiplier cells (equivalent to digital XOR gates) which halves the number of comparators required and signicantly reduces the complexity of the further digital encoding necessary. a simple digital encoding algorithm consistent with the analog encoding procedure described above which employs a logic tree of XOR gates and generates Gray coded output data from the digitized sinusoids. a coarse quantizer, sometimes called a cycle pointer, which ascertains in which period of the quadrature sinusoids input-output characteristic the input signal is located. This 3-bit (plus overow) quantizer utilizes a differential reference scheme to eliminate errors induced by comparator bias currents, and exploits analog encoding to reduce the required number of comparators from 9 to 4.
10.2 Further Research Opportunities
305
The research leading to this thesis, and the results obtained therefrom enable some conclusions to be drawn regarding performance limits imposed upon the types of A/D converters studied. In multistage ADCs employing digital error correction, converter resolution is primarily limited by the accuracy of the internal D/A converters and by the relative accuracy of the gain matching between the composite stages. D/A converter design is a mature eld, and many ingenious techniques exist to produce high-accuracy, high-resolution DACs. The problem in multi-stage ADCs is slightly different however, since, in most cases, a high-accuracy, low-resolution DAC is necessary. Nonetheless, techniques exist to produce accurate DACs for use in pipelined A/D converters. Therefore, accurate gain matching among multistage A/D components remains as the factor limiting resolution. Where high-gain op-amps are available, the problem is mitigated, but since pipelined A/D converters are relied upon for their speed potential, op-amp based (and hence frequency limited) implementations are often inappropriate. Open-loop, untrimmed matching of pipelined A/D converter components is therefore limited by the intrinsic matching of integrated circuit components to about 0.1%. Depending upon the particular partitioning involved, such ADC component gain mismatch places a limit on achievable resolution in multistage A/D converters which is approximately 10 to 12 bits. New conversion algorithms which alleviate this constraint imposed by component gain matching should be developed. Resolution in folding A/D converters of the type developed here is limited by mismatches in transistor V BE . Since the full-scale range of a high-speed folding ADC is practically limited (by several considerations including speed) to about 2 Volts, typical transistor mismatches ( V
BE
1 2mV ) limit converter resolution to about 9 bits.
10.2Further Research Opportunities

Several opportunities exist to extend the analysis presented here or to enhance the performance of the circuits developed. Some of the more promising areas for investigation are delineated below. As mentioned above, one limit to achievable resolution in untrimmed multi-stage ADCs is imposed by the linearity of the reconstruction DAC. The segmented D/A converter topology provides excellent performance in this regard but is still limited to approximately 10 bit performance. Other approaches amenable to implementation in bipolar technology which exceed this linearity invoke dynamic averaging techniques to improve matching [1], [2], [3], [4], [5].
306
Because of their increased complexity over the conventional segmented approach, these dynamic element matching topologies were not considered for this project. However, the prospect of improved linearity promised by such D/A converters make their adoption worthy of further consideration. Threshold errors in ash ADCs and in folding ADCs arise from offset voltages inherent in the comparators which comprise the converter. The effect of these offsets can be mitigated by spatially averaging the offsets from a number of neighboring comparators. An ingenious method for performing this operation resistively couples outputs from adjacent comparator pre-ampliers to obtain the necessary averaging of offset voltages [6]. A similar method could be applied to the analog encoders interposed between the non-uniform interpolation ladder and the comparator bank of the folding quantizer. This technique should improve linearity of the folding converter. A similar technique applied to the outputs of the folding ampliers themselves would greatly improve achievable linearity since transistor mismatches in the folding circuits currently limit folding A/D resolution. The details and effectiveness of such an implementation are not clear. Gain matching in multi-stage A/D converters places a fundamental limit on achievable performance. New algorithms which do not rely upon accurate gain matching would greatly improve capabilities of high-speed converters. However, no simple solution to this fundamental problem currently presents itself. As such, this area remains an important and interesting eld of inquiry. The effect of deterministic threshold perturbations on the spectra of quantized signals remains an important area where better understanding is needed. Certain A/D converter architectures give rise to predictable threshold errors which ultimately limit linearity; however, determining distortion spectra based upon these errors is still impractical. For example, reference bowing in bipolar ash converters, gain mismatches among components in multi-stage ADCs, and temperature changes in folding converters all give rise to deterministic threshold errors which are easily characterized as functions of the relevant parameters. Development of techniques for predicting A/D converter output spectra including such threshold perturbations would prove invaluable for high-performance data converter design.
10.2 Further Research Opportunities
307
References
[1] [2] [3] [4] R. J. van de Plassche, Dynamic element matching for high-accuracy monolithic D/A converters, IEEE Journal of Solid State Circuits, vol. SC-11, pp. 795800, Dec. 1976. R. J. van de Plassche and D. Goedhart, A monolithic 14 bit D/A converter, IEEE Journal of Solid State Circuits, vol. SC-14, pp. 552556, June 1979. R. J. van de Plassche and H. J. Schouwennars, A monolithic 14 bit A/D converter, IEEE Journal of Solid State Circuits, vol. SC-17, pp. 11121117, Dec. 1982. E. C. Kwong, G. L. Baldwin, and T. Hornak, A frequency-ratio-based 12-bit MOS precision binary current source, IEEE Journal of Solid State Circuits, vol. SC-19, pp. 1029 1037, Dec. 1984. H. J. Schouwenaars, E. C. Dijkmans, B. M. J. Kup, and E. J. M. van Tuijl, A monolithic dual 16-bit D/A converter, IEEE Journal of Solid State Circuits, vol. SC-21, pp. 424429, June 1986. K. Kattmann and J. Barrow, A technique for reducing differential non-linearity errors in flash A/D converters, in International Solid State Circuits Conference, pp. 170171, IEEE, Feb. 1991.
[5]
[6]
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ADC - A 10bit 100Msps ADC With Folding Interpolation and Analog Encoding - Thesis

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A 10-bit, 100 MS/s A/D Converter using Folding, Interpolation, and Analog Encoding

EPORT FINAL REPORT

Design Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.2.1 SHPi Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.2.10 Thermal Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 3.3 Track-and-Hold Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Interstage TrackandHold Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 212

Sinusoidal Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 6.2.2 Sinusoidal Folding Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 1.12. Cross-section and plan view of minimum-size SHPi device. . . . . . . . . . . . . . . . 16

Figure 1.44. Segment of quantization error waveform with non-zero threshold

Figure 2.15. Modified timing scheme for pipelined A/D converter. . . . . . . . . . . . . . . . . . . . . . 97

Figure 3.3. Diode-bridge track-and-hold with differential pair controlling bridge

Figure 3.27. Feedthrough versus cross-coupling capacitance normalized to optimum

Figure 3.29. Feedthrough versus area of cross-coupled diode structure normalized to

Figure 3.41. A differential track-and-hold implementation with linearity compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 3.44. Postamplifier implementations. (a) An operational amplifier connected

Figure 6.8. Linear superposition implements non-uniform interpolation to generate

Figure 6.14. Differential non-uniform interpolation ladder generates sinusoids equally

Figure 6.18. Improved encoding scheme significantly reduces hardware complexity.

ABSTRACT OF THE DISSERTATION

William Thomas Colleran

(a) RF Signal IF Signal

A/D Converter (b)

Digital Demodulator & Processing

A/D Converter (c)

Digital Mixer, Demodulator, & Processing

1.1 Applications for High-Speed Low-Power A/D Converters

HDTV Ultrasound Requirement Requirement

Table 1.1. Comparison of performance requirements for HDTV and medical

1.1 Applications for High-Speed Low-Power A/D Converters

1.1.1 Ultrasound Imaging Systems

Figure 1.2. Basic Reection imaging system.

1.1 Applications for High-Speed Low-Power A/D Converters

Signal Processor Summer

Figure 1.3. Phased array imaging system.

Delay Delay Delay Delay Transducer Array Control Unit

1.1 Applications for High-Speed Low-Power A/D Converters

Table 1.2. Requirements for medical ultrasound imaging applications.

1.1.2 HighDenition Television

Figure 1.6. A typical digital television system.

Motion Vector Detection

16.2 Ms/s Transmission Equalization LPF

32.4 Ms/s MUSE OUT D/A LPF FM Modulation

LPF 12.15 MBd Audio/VIT Signal Adder 13 MHz 32.4 MHz

1.1 Applications for High-Speed Low-Power A/D Converters

Table 1.3. Requirements for HDTV applications.

"I" (In-Phase) Channel Detector ADC

RF Weighting, Delay, and Combining Network

Local Oscillator Digital Processor 90 degree Phase Shifter Detector ADC

"Q" (Quadrature) Channel

Figure 1.8. Typical phased array radar system.

1.1.4 Digital Sampling Oscilloscopes

Low Rate Digital Play back

Clock & Control Gain Adjust Write Read

Figure 1.9. Typical sampling oscilloscope.

1.2 Design Goals

1.2 Design Goals

650mW [18] 400mW [26]

Bipolar CMOS BiCMOS This work

500mW [19] 150mW [17] 900mW [20]

750mW, Design Goal

300mW [22] 2.0W [28] 2.7W [27]

10 100 Sampling Frequency (Msps)

Figure 1.10. A/D converter performance comparison.

Table 1.4. Performance goals for this development.