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Lecture Introduction to VHDL

Janak H Patel H. Department of Electrical and Computer Engineering y p g University of Illinois at Urbana-Champaign

Topics p
Programmable Logic PLAs, PLDs PLAs PLDs, FPGAs Design Description Languages Introduction t I t d ti to VHDL Logic Value System of VHDL Entity E tit Architecture Concurrent S C Statements

Programmable Logic g g
Programmable Logic Arrays (PLAs) and PALs Two-level AND-OR array with True and Complemented inputs
Primarily used in large chip designs

Programmable Logic Devices (PLDs) A variety of proprietary designs consisting of several PLA lik bl k and programmable l like blocks d bl switches to interconnect them Field Programmable Gate Arrays (FPGAs) Thousands of identical macro-cells that can be interconnected by programmable switches yp g Each macro-cell is a Programmable Logic Gate
Truth Table is stored in a RAM, called the Look-up Table T bl (LUT)

PLDs and FPGAs

Speed PLDs give predictable timing and give higher timing, system clock frequency FPGA clock frequency is design dependent and q y g p usually much slower than PLDs Size PLDs can accommodate up to 10,000 gates FPGAs can accommodate up to 25 million gates Design flexibility D i fl ibilit FPGAs often come with large memory and predefined function units Manufacturers Xilinx, Altera, Lucent, Cypress, Lattice

Hardware Description Languages p g g

Two Widely Used Languages Verilog HDL
C-language like syntax, easy to learn

VHSIC Hardware Description Language VHSIC - Very High Speed Integrated Circuits Follows the structure of ADA programming Language Originally intended as a Simulation Language for very large systems Very Strongly Typed Language, for example, bit vector 0011 and i t t d integer 3 are not easily t il interchangeable

Verilog and VHDL each have about 50% share of the commercial user base

Uses 9 Signal Values (IEEE standard) A Signal Val e m st be enclosed in single q otes Value must quotes
0 -- Forcing 0 1 -- Forcing 1 1 X -- Forcing Unknown - -- Dont Care Don t Z -- High Impedance U -- Uninitialized U L -- Weak 0 H -- Weak 1

Bit Vectors are enclosed in double quotes An example of VHDL assignment statement p g Y <=1 when STATE =0101 else 0;

Entities and Architectures

Entity External View: Pin Out description, Interface Pin-Out description, Input-Output Port definition etc. Architecture Internal View
Structural Description - e.g. Gates and wires Behavioral Description - e.g. f B h i lD i ti functions and processes, ti d RTL description, if-then-else, Add, Subtract

4 Din 2 sel


mux Dout


4-to-1 Multiplexer ( p (behavioral) )

library IEEE; -- libraries needed for use IEEE.std_logic_1164.all; -- simple logic functions entity mux is port (sel: in std_logic_vector(1 downto 0); Din: in std logic vector (3 downto 0); std_logic_vector Dout: out std_logic); end entity mux; architecture my_mux_behavior of mux is begin -- all comments are preceded by two dashes Dout <= Din(3) when sel=11 else -- first evaluate this < sel 11 Din(2) when sel=10 else -- next evaluate this Din(1) when sel=01 else -- then evaluate this Din(0) when sel=00 else -- then evaluate this h l h X; -- if all fails then X end architecture my mux_behavior; y_ ;
(when <condition> else construct forces a priority structure in hardware synthesis)

4-to-1 Multiplexer (better behavioral)

library IEEE; use IEEE.std_logic_1164.all; entity mux is port (sel: in std_logic_vector(1 downto 0); Din: in std logic vector (3 downto 0); std_logic_vector Dout: out std_logic); end entity mux; architecture behavior of mux is begin with sel select Dout <= Din(3) when 11, -- there is no specific order under Din(2) when 10, -- which conditions are evaluated Din(1) when 01 i (1) h 01, Din(0) when 00, X when others; --default case must be included end architecture behavior;
(with <signal> select construct results in better optimized hardware in synthesis)

4-to-1 Multiplexer using g p g gates

s1bar s0bar Din(3) Din(2) Din(1) Di (1) Din(0) Dout = Din(3)sel(1)sel(0) + Din(2)sel(1)s0bar + Din(1)s1barsel(0) + ( ) ( ) Din(0)s1bars0bar

sel(1) sel(0) architecture structure of mux is signal s0bar, s1bar; std_logic; -- internal signals begin b i s0bar <= not(sel(0)); s1bar <= not(sel(1)); Dout <= (Din(3) and sel(1) and sel(0)) or (Din(2) and sel(1) and s0bar) or (Din(1) and s1bar and sel(0)) or (Din(0) and s1bar and s0bar); end architecture structure;


4-to-1 Multiplexer ( p (Structural) )

library IEEE; use IEEE.std_logic_1164.all; entity mux is port (sel: in std_logic_vector(1 downto 0); Din: in std logic vector (3 downto 0); std_logic_vector Dout: out std_logic); end entity mux; architecture structure of mux is signal s0bar, s1bar; std_logic; -- internal signals g -- following three are concurrent signal assignments (CSAs) f g g g ( ) begin s0bar <= not(sel(0)); -- these are not executed sequentially s1bar <= not(sel(1)); -- order of these CSAs is unimportant! Dout <= (Din(3) and sel(1) and sel(0))or < (Din(2) and sel(1) and s0bar) or (Din(1) and s1bar and sel(0)) or (Din(0) and s1bar and s0bar); end architecture structure;

A Note about Libraries

In almost all designs from now on, we will use the following Libraries library IEEE; use IEEE STD LOGIC 1164 ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE STD LOGIC UNSIGNED ALL IEEE.STD_LOGIC_UNSIGNED.ALL These libraries permit use of predefined logic values, values logic operations like AND, OR and AND OR, arithmetic operations like + (add) etc.


A Bit-Serial Logic Unit g


A_in A in B_in

A_out One-bit wide Logic Unit compute compute


B_out entity compute is Port ( F : in std logic vector(2 downto 0); std_logic_vector(2 A_In, B_In : in std_logic; A_Out, B_Out : out std_logic; F_A_B F A B : o t std logic) out std_logic); end entity compute;


Behavioral of Logic Processor g

architecture Behavioral of compute is begin with F select F_A_B <= A_In and B_In when "000", A_In or B_In when "001", , A_In xor B_In when "010", '1' when "011", A_In A In nand B In when "100", B_In 100 , A_In nor B_In when "101", A_In xnor B_In when "110", '0' when others; -- must be included A_Out <= A_In; B_Out <= B_In; end architecture Behavioral;


Concurrency in VHDL y
Concurrent Signal Assignments (CSA) All statements in a VHDL description are e ec ted executed concurrently unless specified within a process Concurrency is useful in describing combinational logic circuits A concurrent statement is evaluated when any of its arguments change its value A process executes only on specified triggers A process declaration includes a sensitivity list A process executes only when one of the arguments in the sensitivity list changes Processes are useful in describing sequential g q circuits and state transition diagrams

Sequential Circuit Example q p

entity up_down_counter is port ( lk enable, up_down : i std_logic; t (clk, bl d in td l i asynch_clr: in std_logic; Q: out std logic vector(7 downto 0); std_logic_vector(7 end entity;

enable up down p_ asynch_clr clk

8-bit U D 8 bit Up-Down C Counter t

Q(7) Q(6) . . . . .



Counter Behavior
architecture counter_behavior of up_dn_counter is signal count: std_logic_vector(7 downto 0); Begin -- count is an internal signal to this process process(clk, asynch_reset) -- sensitivity list begin if (asynch reset=1) then count <= 00000000; (asynch_reset= 1 ) 00000000 ; elsif (rising_edge(clk)) then synchronous state transitions if (enable=1) then if (up down=1) then count <= count+00000001; (up_down 1 ) < count+ 00000001 ; else count <= count-00000001; end if; end if; ; -- end if is not permitted here to match elsif end if; end process; p Q <= count; end architecture counter_behavior; Note: We cannot use Q <= Q + 1 since Q is defined as output only

Sequential Circuit Example-2 q p

entity up_down_counter is port ( lk enable, up_down : i std_logic; t (clk, bl d in td l i synch_clr: in std_logic; Q: buf std logic vector(7 downto 0); std_logic_vector(7 -- buf is same as out but can be read inside the process end entity; enable up down p_ synch_clr clk Q(7) Q(6) . . . . . Q(1)Q(0)

8-bit U D 8 bit Up-Down C Counter t


Counter Behavior-2
architecture counter_behavior of up_dn_counter is begin process(clk, synch_reset) -- sensitivity list begin if (rising_edge(clk) then _ if(synch_reset=1) then Q <= 00000000; elsif (enable=1) then --notice no e in elsif if (up down=1) then Q <= Q + 1 ( p_ ) else Q <= Q - 1; end if; end if elsif -- end if is not permitted here to match the elsif end if; end if; -- notice it is end if not endif end process; end architecture counter_behavior;


4-Bit Shift Register g

entity reg_4 is Port (Shift_In, Load, Shift_En, Clk : in std_logic; D : in std_logic_vector(3 downto 0); Shift_Out : out std_logic; g Data_Out : out std_logic_vector(3 downto 0); end entity reg_4;

D Shift_In Load Shift_En Clk

4 4 4-Bit Register reg 4 reg_4 Data_Out Shift_Out Shift Out


Shift-Register Behavior g
architecture Behavioral of reg_4 is signal reg_value: std_logic_vector(3 downto 0); begin b i operate_reg: process (Load, Shift_En, Clk, Shift_In) begin if (rising_edge(Clk)) then if (Shift_En = '1') then reg value <= Shift_In & reg value(3 downto 1); g_ g_ ( ) -- operator & concatenates two bit-fields elsif (Load = '1') then reg_value < reg value <= D; -- parallel load (lower priority than shift) else reg_value <= reg_value; --keep data unchanged end if; end if; end process;
Data_Out <= D t O t < reg_value; l Shift_Out <= reg_value(0); end architecture Behavioral;

Control Unit
entity control is Port ( Reset, LoadA, LoadB, Execute : in std_logic; Clk : in std_logic; Shift_En, Ld_A, Ld_B : out std_logic); _ _ _ _ end entity control; Input switches Reset LoadA LoadB Execute Clk Ld_B Control (state machine) Control Bi C l Bits Shift_En Ld_A

0 0







Controller State Machine

architecture Behavioral of control is type cntrl state is (A, B, C, D, E, F); cntrl_state -- User defined type cntrl_state has 6 symbolic values signal state, next_state : cntrl_state; begin control_reg: process (Reset, Clk, LoadA, LoadB) begin if (Reset = '1') then state <= A; _ elsif (rising_edge(Clk)) then state <= next_state; end if; end process; p ; -- Behavioral continued on next two slides for Next State and Output Functions See Sequence Recognizer Example in Mano and Kime (ECE 290 Text Book)

State Transitions
get_next_state: process (Execute, state) begin case state is when A => if (Execute = '1') then next_state <= B; else next_state <= A; end if; when B => next_state <= C; when C => next_state <= D; when D => next_state <= E; when E => next_state <= F; --wait at state F until 'Execute' = 0 when F => if (Execute = '0') then next_state <= A; else next_state next state <= F; end if; -- when others => default case is not needed here since there are -- only six values for state and we have exhausted them all. end case; end process;

Outputs ( p (Moore machine) )

get_cntrl_out: process (LoadA, LoadB, state) begin case state is when A => -- Enable Register-Loads only when in state A Ld_A <= LoadA; Ld_B <= LoadB; Shift_En <= '0; when F => Ld A <= '0' Ld B <= '0' h Ld_A '0'; Ld_B '0'; Shift_En <= '0'; when others => -- others are states B,C,D and E others BCD Ld_A <= '0'; Ld_B <= '0'; Shift_En <= 1'; end case; end process; end architecture Behavioral; -- started on page 23 d

State Machine Encoding g

State Machine Encoding and Synthesis Synthesis a tomaticall S nthesis automatically picks the best encoding Or, you can specify the encoding for your state machine explicitly Examples of State Encodings (for 5 States)
Arbitrary Binary Encoding: 011 101 000 111 010 011, 101, 000, 111, Enumerated Binary: 000, 001, 010, 011, 100 One Hot: 00001, 00010, 00100, 01000,10000 One-Hot: 00001 00010 00100 01000 10000

See VHDL example code from Xilinx

http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/vtex9.html p


Using Components g p
entity full_adder is p port (x, y, z : in std_logic); y g x y z s, c : out std_logic); full_adder end entity; c s -- we will use the component full_adder to sum carry -- build a 4-bit ripple carry adder entity ADDER4 is port (A B : in std logic vector (3 down to 0); (A,B std_logic_vector S : out std_logic_vector (3 down to 0); c_in : in std_logic; c_out : out std_logic); t t td l i ) end entity; A3 B3 S3 A2 B2 A1 B1 ADDER4 S2 S1 A0 B0 c_in S0


Connecting Components g p
architecture structural of ADDER4 is component full_adder is port(x,y,z: i std_logic; s,c: out std_logic); -- reproduce the entity d t( in td l i t td l i ) d h description end component full_adder; -- omit name full_adder for older simulators signal c0,c1,c2: std_logic; -- internal wires needed to connect full adders begin -- this illustrates how to instantiate and connect components FA0: full_adder port map(x =>A(0), y =>B(0), z =>c_in, s =>S(0), c =>c0); FA1: full_adder port map(x =>A(1), y =>B(1), z =>c0, s =>S(1), c =>c1); p p( ( ), ( ), , ( ), ); FA2: full_adder port map(x =>A(2), y =>B(2), z =>c1, s =>S(2), c =>c2); FA3: full_adder port map(x =>A(3), y =>B(3), z =>c2, s =>S(3), c =>c_out); end architecture structural ADDER4 A3 B3
x y c_out FA3 c z s

A2 B2 c2
x y FA2 c z s

A1 B1 c1
x y FA1 c z s

A0 B0 c0
x y FA0 c z s






Putting it all together g g


entity my_system


Register Unit Compute Unit 6


LoadA LoadB Execute Reset Clock Routing R ti Unit Control C t l Unit


Architecture of my_system y_ y
architecture structural of my_system is component compute is -- entity description reproduced F2-F0 port(A_in, B_in: port(A in B in: in std logic; std_logic; A_out A_out, B_out, F_A_B: out std_logic; A_inentity F: in std_logic_vector(2 downto 0)); compute F_A_B end component compute; B_in B in B_out B out component register_unit is ... -- reproduce entity description here component router is ... -- reproduce entity description here component control is ... -- reproduce entity description here p y p end component control; signal ...; - declare all signals needed to interconnect components begin ... -- instantiate and connect all components in main body computation_unit: compute port map(F=>F, A_in=> ..., B_in=>..., F_A_B=>...); ... end architecture structural my_system;


Summary y
VHDL is a design description language not a language that automatically designs for you! The design process is very similar to the designing with TTL chips and wires, but with much more flexibility d functionality fl ibili and f i li In VHDL you create your own chips (entities) and connect the pins (ports) with wires (signals) pins wires You cannot make bigger TTL chips out of smaller chips, but with VHDL you can make bigger and p , y gg more complex entities out of smaller entities (e.g. a 16-bit ALU out of 16 one-bit ALU slices) You Y must first design on paper using block t fi t d i i bl k diagrams and interconnections, before you can describe it in VHDL!