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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS Int. J. Circ. Theor. Appl.

2008; 36:813823 Published online 6 November 2007 in Wiley InterScience (www.interscience.wiley.com). DOI: 10.1002/cta.461

Analysis and selection criteria of BSIM4 icker noise simulation models


T. Noulis1, , , S. Siskos1 and G. Sarrabayrouse2
1 Electronics

Laboratory of Physics Department, Aristotle University of Thessaloniki, Aristotle University Campus, 54124 Thessaloniki, Greece 2 Laboratoire dAnalyse et dArchitecture des Syst` mes LAASCNRS, 7 Avenue du colonel Roche, e 31077 Toulouse Cedex 4, France

SUMMARY CMOS transistors noise performance is mainly dominated by icker (1/ f ) noise. BSIM4.X MOSFET simulation model develops two distinct models, SPICE-Flicker and BSIM-Flicker, to calculate icker noise. In this paper, these two models are analytically examined and compared to noise measurements, using an NMOS and a PMOS device fabricated in 0.6 m process by Austria Mikro Systeme (AMS). MOSFET 1/ f noise measurements and the respective simulations were obtained under various bias conditions, as to study which icker noise model is the optimum in each operating region. Measurement temperature was constant at 295 K. Comparisons suggest that in an NMOS transistor operating in the triode or saturation region, BSIM-Flicker model is accurate and therefore preferable. In a PMOS transistor, the most suitable model to describe its 1/ f noise performance in the linear regime is also BSIM-Flicker, whereas SPICEFlicker is more preferable in saturation. In NMOS transistors, the selected model provides a great accurate description of icker noise, contrary to PMOS transistors, where simulation models appear to be quite unreliable and need further improvement. Copyright q 2007 John Wiley & Sons, Ltd.
Received 21 October 2006; Revised 22 August 2007; Accepted 3 September 2007 KEY WORDS:

BSIM4 MOSFET model; icker noise exponent; SPICE-Flicker and BSIM-Flicker noise models

1. INTRODUCTION Noise performance is a crucial part of microelectronics systems reliability and becomes extremely important in readout amplication stages. The noise behavior of CMOS devices is primarily dominated by two sources, thermal and icker noise. MOS transistor thermal noise is generated mainly by the channel resistance. Flicker noise phenomenon appears through both quality-dependent and
Correspondence

to: T. Noulis, Electronics Laboratory of Physics Department, Aristotle University of Thessaloniki, Aristotle University Campus, 54124 Thessaloniki, Greece. E-mail: tnoul@physics.auth.gr

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T. NOULIS, S. SISKOS AND G. SARRABAYROUSE

fundamental noise processes. It seems to be large in MOSFETs and therefore sets the lower limit to the level of the signal that can be processed by VLSI devices and circuits. It is also commonly called 1/ f noise because the noise spectrum varies as 1/ f , where the exponent is very close to unity ( = 10.2). In contrast to the channel thermal noise which is quite understood, icker noise is not yet fully known, although its presence is surprisingly universal in all types of semiconductor devices [1]. A lot of studies have been done so far in order to explain and describe the icker noise phenomenon [219]. However, controversy still exists in the modeling of 1/ f noise in CMOS transistors. The number and mobility uctuation models are the two models that explain 1/ f noise origin. The number uctuation theory states that 1/ f noise is generated by uctuations in the carrier number [27]. On the other hand, the mobility uctuation suggests that icker noise is essentially a bulk phenomenon. In particular, the uctuations in the conductivity are due to uctuations in the mobility of charge carriers [813]. Other researches have combined these two theories into a single model and proposed that charges, when trapped, cause correlated mobility uctuations [14]. This model was further developed and used in circuit simulators such as SPICE [15, 16]. In integrated circuits design, noise simulation is a key point of the process. To evaluate circuit noise performance, the designer uses one of the noise models available in the simulator. While conclusions and design criteria concerning noise are extracted using simulations in different types of typical analog integrated circuits [2023] and while other issues like the MOS transient response were studied with respect to the simulation model and level [24, 25], no extended research has been performed on the validity of the available used 1/ f noise simulation models in relation to the MOS transistor model that is developed in the simulator. In particular, BSIM4 model, which is one of the most commonly used Spice MOS transistor simulation models, develops two distinct models, SPICE-Flicker and BSIM-Flicker, to calculate icker noise. The selection of the noise model is very important in icker noise evaluation depending upon the type of MOSFET (n or p) and the operating mode. Hence, any information or rule about the model to select is very essential and useful to the designer. Only two previous works that examine which icker noise simulation model is more appropriate have been published so far [26, 27]. They concern NMOS devices operating from subthreshold to strong inversion and PMOS transistors only in the saturation region. In addition, noise comparisons refer to old versions of the BSIM MOSFET model. 1/ f noise performance is examined in relation to the gatesource bias, the transconductance and its linearity, and the MOSFET channel length. Different 1/ f noise models are considered suitable for different MOS-operating regions and the accuracy of each 1/ f model is examined at only two particular frequencies (1 Hz and 1 kHz). Only fragmentary results are obtained, which cannot be directly addressed to the entire icker noise frequency bandwidth. In this paper, as a complementary work, icker noise performance of both n- and p-type transistors is examined in all operating regions. Flicker noise measurements were obtained for various drain currents, from threshold to saturation and in a frequency bandwidth from 10 Hz to 10 kHz where 1/ f noise dominates. In order to study the accuracy of the simulation noise models, 1/ f noise measurements are directly compared to the respective simulations. Suggestions about which model is the more suitable to describe MOSFET icker noise behavior in each operating region are given and icker noise model selection criteria are proposed in relation to the type (n or p) of the MOS transistor. In addition, the dependence of the MOSFET icker noise performance in relation to frequency and drain current variation was also studied in order to achieve a detailed analysis of the models accuracy in describing the 1/ f noise phenomenon.
Copyright q 2007 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2008; 36:813823 DOI: 10.1002/cta

ANALYSIS AND SELECTION CRITERIA OF BSIM4 FLICKER NOISE SIMULATION MODELS

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2. BSIM4.X 1/ f NOISE SIMULATION MODELS BSIM4 MOSFET model uses two different icker noise models, SPICE-Flicker and BSIM-Flicker. The SPICE-Flicker noise model states the average value of the square of the icker noise drain current at a particular frequency and is given by
2 i 1/ f

= KF

|IDS |AF Cox,e L 2 f EF eff

(1)

where IDS is the input MOS drain current, KF is the icker noise coefcient, which is the proportional factor and depends critically on processing, AF (icker exponent) and EF (icker 2 frequency exponent) characterize the power dependence of the measured i d on IDS and frequency, respectively, L eff is the effective channel length and Cox,e is the gate capacitance per unit area. This model is identical to the respective BSIM3 icker noise model, except for the difference in use of Cox in BSIM3 and Cox,e in BSIM4 [2830]. BSIM-Flicker noise model appears to be quite complicated. It also follows the basic framework of BSIM3, but with the improvements of using smoothing functions and considering the bulk charge effect. It is given in a simplied form by
2 i 1/ f

h(NOIA, NOIB, NOIC)

g(EM)IDS IDS + 2 f EF Cox,e L eff Weff L 2 f EF eff

(2)

where h is a function of the Spice parameters NOIA, NOIB and NOIC, and g is a function of the Spice parameter EM. NOIA, NOIB and NOIC can be treated as tting parameters, such as KF in SPICE-Flicker noise model. EM represents the eld at which the carrier velocity saturates and Weff is the effective channel width. SPICE-Flicker noise model is simple with one primary parameter (KF), which can vary the noise magnitude, contrary to BSIM-Flicker model, which is quite complicated. The exact model used for calculating MOS transistor icker noise performance depends on the value of BSIM4 model parameter fnoimod (Flicker Noise Models). The selector parameter fnoimod is the ag to choose among the BSIM4 noise models and takes on values 0 or 1. In particular, when fnoimod is 0, SPICE-Flicker noise model is used and when fnoimod is 1, BSIM-Flicker model is selected [2830]. 3. LOW-FREQUENCY NOISE MEASUREMENT SETUP The schematic of the noise measurement system is shown in Figure 1. The dc bias used are two noiseless homemade power supplies. Variable biasing is available at the gate, drain and substrate terminals of the device. The drain of the device under test (DUT) is biased through an impedance network. The amplication of the DUT output signal was performed using the 5182 model current-sensitive preamplier of low noise and low impedance, commercially available by signal recovery. This preamplier is designed to amplify extremely low currents encountered in areas such as photometry and semiconductor research. It has four standard conversion factors but in addition includes a special low noise mode on the highest gain position for even better low-current measurement capability. The preamplier has an equivalent noise current of the order
Copyright q 2007 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2008; 36:813823 DOI: 10.1002/cta

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Figure 1. Schematic of the low-frequency noise measurement system using a MOS transistor as DUT.

of 10 pA/ Hz (at 1 kHz). The respective maximum dc input current is 9 mA and sensitivity is 105 . The unit features two outputs allowing both the ac and dc components of the input signal to be independently monitored [31, 32]. With this experimental implementation, the gate and drain voltages were independently controlled and varied in order to examine the noise performance of DUT under different biasing conditions. The amplied noise power was measured by the Agilent 89410A spectrum analyzer.

4. SIMULATION, MEASUREMENT RESULTS AND COMPARISONS The n- and p-type MOS transistors were fabricated in 0.6 m CMOS process by Austria Mikro Systeme (AMS) and their dimensions were (400 m/1.2 m) for the NMOS and (1000 m/1.2 m) for the PMOS transistors. The specic technology is based on thermal oxide gate insulator, which in comparison with a nitrided oxide provides better 1/ f noise performance [33, 34]. Bias conditions varied so as to measure MOS icker noise performance from the threshold of the linear operating region to saturation. The measurements were obtained for a frequency range of 10 Hz10 kHz and the temperature was constant at 295 K. In order to nd out the exact icker noise dependence on frequency variations and compare it to the respective simulation parameter (EF), which is common to both models, these measurements were exponentially tted. Tables I and II list the experimental values of 1/ f noise exponent for a range of NMOS and PMOS transistor measurements, respectively. The icker noise measurements of an NMOS and a PMOS FET in the linear and saturation regions are shown in Figures 2 and 3. As it can be seen in Table I, regarding the description of an NMOS transistor noise behavior in linear and saturation regions, the experimental results for the icker noise exponent, which varies from 0.91 to 0.98, are quite close to the given value of the simulation parameter EF, which is unity. Therefore, both models can describe with accuracy the noise spectral density dependence on frequency. The icker noise exponent of an N-MOSFET at the threshold of a linear region, for a drain current of 17 A, is an exception, since it was found to be 0.85 due to harmonics in the kHz range. On the contrary, P-MOSFET 1/ f noise measurements (Table II) show a different dependence on frequency. Particularly, in the saturation region, the noise parameter EF ranges from 0.63 to 0.79, whereas in the linear region it ranges from 0.53 to 0.58. These values, in all operating regions
Copyright q 2007 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2008; 36:813823 DOI: 10.1002/cta

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Table I. Flicker noise exponent of an NMOS transistor.


Drain current Saturation region 460 A 470 A 480 A 1.50 mA 1.55 mA Linear region 17 A 220 A 590 A 1.05 mA 1/ f noise exponent 0.93 0.93 0.93 0.98 0.97 0.85 0.91 0.95 0.92 Error % 0.32 0.33 0.31 0.34 0.33 0.74 0.41 0.34 0.36

Table II. Flicker noise exponent of a PMOS transistor.


Drain current Saturation region 300 A 320 A 350 A 1.1 mA 1.2 mA Linear region 217 A 740 A 1/ f noise exponent 0.65 0.64 0.63 0.77 0.79 0.53 0.58 Error % 0.71 0.75 0.68 0.62 0.72 0.77 0.72

Figure 2. NMOS transistor noise performance in: (a) linear and (b) saturation region for various values of drain current.
Copyright q 2007 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2008; 36:813823 DOI: 10.1002/cta

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T. NOULIS, S. SISKOS AND G. SARRABAYROUSE

Figure 3. PMOS transistor noise performance in: (a) linear and (b) saturation region for various values of drain current.

Figure 4. Noise measurements and simulations of an NMOS transistor operating in saturation region for a drain current of: (a) 1.55 mA and (b) 460 A.

and especially in the triode region, appear to be quite lower than unity. The respective error on the icker noise exponent in the PMOS transistor is much higher than that on the NMOS. This implies even more difculty in the PMOS 1/ f noise estimation using the above simulation models. In addition, as Figures 2 and 3 show, the noise behavior of both n- and p-type MOSFETs depends mainly on the drain current. Equations (1) and (2) indicate that as the drain current decreases, so does the MOSFET 1/ f noise. In order to examine the accuracy of the two icker noise models, respective simulations were performed using HSPICE simulator and the BSIM4 MOSFET model. Comparison between measurement and simulation concerns the same MOSFET drain current and the same bias conditions. Figure 4 shows the noise current spectrum of an n-channel transistor biased in the saturation region. In Figure 4(a) the comparison between the two 1/ f noise models refers to a drain current of 1.55 mA and in Figure 4(b) to 460 A. As can be seen, for a high drain current, SPICE-Flicker noise model overestimates noise, whereas BSIM-Flicker estimates it with good accuracy and is
Copyright q 2007 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2008; 36:813823 DOI: 10.1002/cta

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Figure 5. Noise measurement and simulations of an NMOS transistor operating in linear region for a drain current of: (a) 220 A and (b) 1.05 mA.

Figure 6. Noise measurement and simulations of an NMOS transistor at threshold for a drain current of 17 A.

therefore the optimum model. For a lower current (Figure 4(b)), SPICE-Flicker also overestimates icker noise and BSIM-Flicker provides a more accurate description. As a result, BSIM-Flicker is the optimum noise model to describe N-MOSFET icker noise performance in the saturation region. Figures 5(a) and (b) show the noise current spectral density of an NMOS transistor in the linear region for a drain current of 220 A and 1.05 mA, respectively. In both curves, SPICE-Flicker model overestimates icker noise, whereas BSIM-Flicker underestimates it. However, BSIM-Flicker is more accurate and is therefore selected to estimate an NMOS transistor 1/ f noise performance in the triode region. Figure 6 shows the noise current spectrum of an NMOS transistor operating near threshold and the drain current is 17 A. BSIM-Flicker model is preferred, since it describes 1/ f noise more accurately, despite underestimating it. SPICE-Flicker considers noise to be much higher in comparison to measurements.
Copyright q 2007 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2008; 36:813823 DOI: 10.1002/cta

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Figure 7. Noise measurement and simulations of a PMOS transistor operating in saturation region for a drain current of: (a) 1.2 mA and (b) 300 A.

Figure 8. Noise measurement and simulations of a PMOS transistor operating in linear region for a drain current of: (a) 217 A and (b) 740 A.

Figure 9. Noise measurement and simulations of a PMOS transistor at threshold for a drain current of 6 A.
Copyright q 2007 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2008; 36:813823 DOI: 10.1002/cta

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A PMOS transistor was also examined regarding the two 1/ f noise models. Figures 7(a) and (b) show the noise current spectrum of a PMOS transistor operating in the saturation region for a drain current of 1.2 mA and 300 A, respectively. In both cases, the models overestimate icker noise and SPICE-Flicker model, which is closer to the measurements, is the optimum. In Figure 8, the two icker noise models are compared to the measurement results of a p-type MOSFET operating in the linear region. Noise comparison in Figure 8(a) refers to a drain current of 217 A and in Figure 8(b) to 740 A. Both noise models overestimate icker noise; however, BSIM-Flicker is preferred as the most accurate in both cases. Figure 9 also shows a PMOS transistor operating at threshold for a drain current of 6 A. Although BSIM-Flicker model appears to be close to the measurement, such a comparison cannot lead to safe conclusions, since plenty of harmonics appear in the range of 100 Hz10 kHz and is therefore considered to be unreliable.

5. CONCLUSION In this work, BSIM4.X MOSFET icker noise models have been analytically described and examined. Direct comparison was performed between CMOS transistors output 1/ f noise spectral density and respective simulations, in all operating regions and in the entire 1/ f noise dominance frequency bandwidth. Safe conclusions about the above icker noise models accuracy are extracted and model selection criteria in order to achieve a correct description of icker noise phenomenon in MOS transistors are suggested. In particular, icker noise exponent was calculated using several NMOS and PMOS transistor noise measurements and was compared with the respective simulation parameter EF. Specically for the NMOS transistor, icker noise exponent was calculated to be close to unity, which is the given value, while in p-channel devices, this exponent was unexpectedly much lower. In addition, it was shown that NMOS and PMOS icker noise depends on the variation of the drain current and lower drain current implies icker noise reduction. Moreover, BSIM-Flicker and SPICE-Flicker MOSFET noise models have been described and analytically compared using simulations with 1/ f noise measurements. In particular, for an NMOS transistor operating in the linear or saturation region, BSIM-Flicker is the best simulation model, since it appears to be closer to the experimental results. In both operating regions, and especially in saturation, the selected model provides an accurate description of the NMOS icker noise behavior. Additionally, for a p-type MOS transistor, SPICE-Flicker noise model is more preferable in the saturation region and BSIM-Flicker in the triode region. In both operating regions, the selected models overestimate icker noise. However, the best noise model for a PMOS transistor is not as accurate as it is for an NMOS transistor. The above study implies that NMOS transistor icker noise performance can be simulated with reliability using the BSIM-icker noise model of BSIM4.X instead of SPICE-icker 1/ f model. However, both noise models appear to be quite problematic for a PMOS transistor. This suggests the necessity to develop a new model to calculate PMOS icker noise performance and to implement it in the simulator. Finally, the results about the reliability of the specic 1/ f noise simulation models can be considered as valid for other typical analog CMOS-scaled processes, since relatively long channel MOSFETs in analog circuit applications are used. However, the accuracy of the noise magnitude that each model provides is process dependent, since the majority of the model parameters depend
Copyright q 2007 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2008; 36:813823 DOI: 10.1002/cta

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critically on processing. Therefore, the models reliability is also conditioned by an effective noise characterization of the used CMOS process.
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2007 John Wiley & Sons, Ltd.

Int. J. Circ. Theor. Appl. 2008; 36:813823 DOI: 10.1002/cta

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